mpm: Harmonize imports, tidy + sort modules

- Moved nijesdcore to cores/
- Moved udev, net, dtoverlay, uio to sys_utils/
- Made all imports non-relative (except in __init__.py files)
- Removed some unnecessary imports
- Reordered some imports for Python conventions

34 files changed, 88 insertions, 71 deletions

diff --git a/mpm/python/setup.py.in b/mpm/python/setup.py.in
index 9c6888a74..583f79189 100755
--- a/mpm/python/setup.py.in
+++ b/mpm/python/setup.py.in
@@ -44,6 +44,7 @@ setup(name='usrp_mpm',
           'usrp_mpm.dboard_manager',
           'usrp_mpm.chips',
           'usrp_mpm.cores',
+          'usrp_mpm.sys_utils',
           'usrp_mpm.xports',
       ],
       install_requires=[
diff --git a/mpm/python/usrp_mpm/CMakeLists.txt b/mpm/python/usrp_mpm/CMakeLists.txt
index b308625ca..81af6eb6b 100644
--- a/mpm/python/usrp_mpm/CMakeLists.txt
+++ b/mpm/python/usrp_mpm/CMakeLists.txt
@@ -24,23 +24,19 @@ SET(USRP_MPM_TOP_FILES
     ${CMAKE_CURRENT_SOURCE_DIR}/aurora_control.py
     ${CMAKE_CURRENT_SOURCE_DIR}/bfrfs.py
     ${CMAKE_CURRENT_SOURCE_DIR}/discovery.py
-    ${CMAKE_CURRENT_SOURCE_DIR}/dtoverlay.py
     ${CMAKE_CURRENT_SOURCE_DIR}/eeprom.py
     ${CMAKE_CURRENT_SOURCE_DIR}/ethtable.py
     ${CMAKE_CURRENT_SOURCE_DIR}/liberiotable.py
     ${CMAKE_CURRENT_SOURCE_DIR}/mpmlog.py
     ${CMAKE_CURRENT_SOURCE_DIR}/mpmtypes.py
     ${CMAKE_CURRENT_SOURCE_DIR}/mpmutils.py
-    ${CMAKE_CURRENT_SOURCE_DIR}/net.py
-    ${CMAKE_CURRENT_SOURCE_DIR}/nijesdcore.py
     ${CMAKE_CURRENT_SOURCE_DIR}/rpc_server.py
-    ${CMAKE_CURRENT_SOURCE_DIR}/sysfs_gpio.py
-    ${CMAKE_CURRENT_SOURCE_DIR}/uio.py
 )
 LIST(APPEND USRP_MPM_FILES ${USRP_MPM_TOP_FILES})
-ADD_SUBDIRECTORY(periph_manager)
-ADD_SUBDIRECTORY(dboard_manager)
 ADD_SUBDIRECTORY(chips)
 ADD_SUBDIRECTORY(cores)
+ADD_SUBDIRECTORY(dboard_manager)
+ADD_SUBDIRECTORY(periph_manager)
+ADD_SUBDIRECTORY(sys_utils)
 ADD_SUBDIRECTORY(xports)
 SET(USRP_MPM_FILES ${USRP_MPM_FILES} PARENT_SCOPE)
diff --git a/mpm/python/usrp_mpm/__init__.py b/mpm/python/usrp_mpm/__init__.py
index 7a907312d..b2b23f494 100644
--- a/mpm/python/usrp_mpm/__init__.py
+++ b/mpm/python/usrp_mpm/__init__.py
@@ -18,10 +18,13 @@
 MPM Module
 """
 
+from . import libpyusrp_periphs as lib
 from .discovery import spawn_discovery_process
 from .rpc_server import spawn_rpc_process
 from . import mpmtypes
 from . import periph_manager
 from . import dboard_manager
 from . import xports
+from . import cores
+from . import chips
 from .mpmlog import get_main_logger
diff --git a/mpm/python/usrp_mpm/aurora_control.py b/mpm/python/usrp_mpm/aurora_control.py
index 6531e8502..cef9280b6 100644
--- a/mpm/python/usrp_mpm/aurora_control.py
+++ b/mpm/python/usrp_mpm/aurora_control.py
@@ -22,7 +22,7 @@ import math
 import time
 from builtins import str
 from builtins import object
-from .mpmlog import get_logger
+from usrp_mpm.mpmlog import get_logger
 
 def mean(vals):
     " Calculate arithmetic mean of vals "
diff --git a/mpm/python/usrp_mpm/chips/lmk04828.py b/mpm/python/usrp_mpm/chips/lmk04828.py
index d9907a49f..7be0c8358 100644
--- a/mpm/python/usrp_mpm/chips/lmk04828.py
+++ b/mpm/python/usrp_mpm/chips/lmk04828.py
@@ -20,7 +20,7 @@ LMK04828 parent driver class
 
 import math
 from builtins import object
-from ..mpmlog import get_logger
+from usrp_mpm.mpmlog import get_logger
 
 class LMK04828(object):
     """
diff --git a/mpm/python/usrp_mpm/cores/CMakeLists.txt b/mpm/python/usrp_mpm/cores/CMakeLists.txt
index 9103ad994..25949099d 100644
--- a/mpm/python/usrp_mpm/cores/CMakeLists.txt
+++ b/mpm/python/usrp_mpm/cores/CMakeLists.txt
@@ -19,6 +19,7 @@ SET(USRP_MPM_FILES ${USRP_MPM_FILES})
 SET(USRP_MPM_CORE_FILES
     ${CMAKE_CURRENT_SOURCE_DIR}/__init__.py
     ${CMAKE_CURRENT_SOURCE_DIR}/tdc_sync.py
+    ${CMAKE_CURRENT_SOURCE_DIR}/nijesdcore.py
 )
 LIST(APPEND USRP_MPM_FILES ${USRP_MPM_CORE_FILES})
 SET(USRP_MPM_FILES ${USRP_MPM_FILES} PARENT_SCOPE)
diff --git a/mpm/python/usrp_mpm/nijesdcore.py b/mpm/python/usrp_mpm/cores/nijesdcore.py
index f46809d94..12be51181 100644
--- a/mpm/python/usrp_mpm/nijesdcore.py
+++ b/mpm/python/usrp_mpm/cores/nijesdcore.py
@@ -21,7 +21,7 @@ JESD FPGA Core Interface
 import time
 from builtins import hex
 from builtins import object
-from .mpmlog import get_logger
+from usrp_mpm.mpmlog import get_logger
 
 class NIMgJESDCore(object):
     """
diff --git a/mpm/python/usrp_mpm/cores/tdc_sync.py b/mpm/python/usrp_mpm/cores/tdc_sync.py
index 194449b65..255810710 100644
--- a/mpm/python/usrp_mpm/cores/tdc_sync.py
+++ b/mpm/python/usrp_mpm/cores/tdc_sync.py
@@ -19,8 +19,8 @@ TDC clock synchronization
 
 import time
 import math
-from builtins import object
 from functools import reduce
+from builtins import object
 from usrp_mpm.mpmutils import poll_with_timeout
 from usrp_mpm.mpmlog import get_logger
 
diff --git a/mpm/python/usrp_mpm/dboard_manager/__init__.py b/mpm/python/usrp_mpm/dboard_manager/__init__.py
index a06591c81..96d1dfcbe 100644
--- a/mpm/python/usrp_mpm/dboard_manager/__init__.py
+++ b/mpm/python/usrp_mpm/dboard_manager/__init__.py
@@ -17,7 +17,6 @@
 """
 dboards module __init__.py
 """
-from .. import libpyusrp_periphs as lib
 from .base import DboardManagerBase
 from .magnesium import Magnesium
 from .eiscat import EISCAT
diff --git a/mpm/python/usrp_mpm/dboard_manager/base.py b/mpm/python/usrp_mpm/dboard_manager/base.py
index 3f5f3adb8..ba82ddb3a 100644
--- a/mpm/python/usrp_mpm/dboard_manager/base.py
+++ b/mpm/python/usrp_mpm/dboard_manager/base.py
@@ -20,7 +20,7 @@ dboard base implementation module
 
 from builtins import object
 from six import iteritems
-from ..mpmlog import get_logger
+from usrp_mpm.mpmlog import get_logger
 
 class DboardManagerBase(object):
     """
diff --git a/mpm/python/usrp_mpm/dboard_manager/eiscat.py b/mpm/python/usrp_mpm/dboard_manager/eiscat.py
index 15037086f..bfd3b42a9 100644
--- a/mpm/python/usrp_mpm/dboard_manager/eiscat.py
+++ b/mpm/python/usrp_mpm/dboard_manager/eiscat.py
@@ -21,11 +21,11 @@ EISCAT rx board implementation module
 import time
 from builtins import range
 from builtins import object
-from ..mpmlog import get_logger
-from ..uio import UIO
-from . import lib
-from .base import DboardManagerBase
-from .lmk_eiscat import LMK04828EISCAT
+from usrp_mpm.mpmlog import get_logger
+from usrp_mpm.sys_utils.uio import UIO
+from usrp_mpm import lib
+from usrp_mpm.dboard_manager import DboardManagerBase
+from usrp_mpm.dboard_manager.lmk_eiscat import LMK04828EISCAT
 from usrp_mpm.cores import ClockSynchronizer
 
 def create_spidev_iface_sane(dev_node):
diff --git a/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py b/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py
index 774c10277..421bb0d47 100644
--- a/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py
+++ b/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py
@@ -19,7 +19,7 @@ LMK04828 driver for use with Magnesium
 """
 
 import time
-from ..chips import LMK04828
+from usrp_mpm.chips import LMK04828
 
 class LMK04828EISCAT(LMK04828):
     """
diff --git a/mpm/python/usrp_mpm/dboard_manager/lmk_mg.py b/mpm/python/usrp_mpm/dboard_manager/lmk_mg.py
index dc3fe203b..1e19aa2f8 100644
--- a/mpm/python/usrp_mpm/dboard_manager/lmk_mg.py
+++ b/mpm/python/usrp_mpm/dboard_manager/lmk_mg.py
@@ -22,8 +22,7 @@ import time
 import math
 from builtins import zip
 from builtins import hex
-from ..mpmlog import get_logger
-from ..chips import LMK04828
+from usrp_mpm.chips import LMK04828
 
 class LMK04828Mg(LMK04828):
     def __init__(self, regs_iface, spi_lock, ref_clock_freq, master_clock_freq, log=None):
diff --git a/mpm/python/usrp_mpm/dboard_manager/magnesium.py b/mpm/python/usrp_mpm/dboard_manager/magnesium.py
index 9cbb2bd9b..e43f324af 100644
--- a/mpm/python/usrp_mpm/dboard_manager/magnesium.py
+++ b/mpm/python/usrp_mpm/dboard_manager/magnesium.py
@@ -24,15 +24,15 @@ import time
 import threading
 import math
 from six import iterkeys, iteritems
-from . import lib # Pulls in everything from C++-land
-from .base import DboardManagerBase
-from .. import nijesdcore
-from ..uio import UIO
-from ..mpmlog import get_logger
-from .lmk_mg import LMK04828Mg
-from usrp_mpm.periph_manager.udev import get_eeprom_paths
+from usrp_mpm import lib # Pulls in everything from C++-land
+from usrp_mpm.dboard_manager import DboardManagerBase
+from usrp_mpm.dboard_manager.lmk_mg import LMK04828Mg
+from usrp_mpm.cores import nijesdcore
+from usrp_mpm.mpmlog import get_logger
+from usrp_mpm.sys_utils.uio import UIO
+from usrp_mpm.sys_utils.udev import get_eeprom_paths
+from usrp_mpm.sys_utils.sysfs_gpio import SysFSGPIO
 from usrp_mpm.cores import ClockSynchronizer
-from ..sysfs_gpio import SysFSGPIO
 from usrp_mpm.bfrfs import BufferFS
 from usrp_mpm.mpmutils import poll_with_timeout
 
diff --git a/mpm/python/usrp_mpm/dboard_manager/test.py b/mpm/python/usrp_mpm/dboard_manager/test.py
index 3dfeab167..eedafe4fd 100644
--- a/mpm/python/usrp_mpm/dboard_manager/test.py
+++ b/mpm/python/usrp_mpm/dboard_manager/test.py
@@ -19,9 +19,7 @@ magnesium dboard implementation module
 """
 
 from builtins import object
-from . import lib
-from .base import DboardManagerBase
-from logging import getLogger
+from usrp_mpm.dboard_manager import DboardManagerBase
 
 class fake_spi(object):
     def __init__(self, addr):
diff --git a/mpm/python/usrp_mpm/dboard_manager/unknown.py b/mpm/python/usrp_mpm/dboard_manager/unknown.py
index d954154f9..94e1344cc 100644
--- a/mpm/python/usrp_mpm/dboard_manager/unknown.py
+++ b/mpm/python/usrp_mpm/dboard_manager/unknown.py
@@ -17,8 +17,7 @@
 """
 EISCAT rx board implementation module
 """
-from .base import DboardManagerBase
-from logging import getLogger
+from usrp_mpm.dboard_manager import DboardManagerBase
 
 class unknown(DboardManagerBase):
     hw_pid = 0
diff --git a/mpm/python/usrp_mpm/discovery.py b/mpm/python/usrp_mpm/discovery.py
index 47088c7e7..2e97f3535 100644
--- a/mpm/python/usrp_mpm/discovery.py
+++ b/mpm/python/usrp_mpm/discovery.py
@@ -24,7 +24,7 @@ import socket
 from builtins import bytes
 from six import iteritems
 from usrp_mpm.mpmtypes import MPM_DISCOVERY_PORT
-from .mpmlog import get_main_logger
+from usrp_mpm.mpmlog import get_main_logger
 
 RESPONSE_PREAMBLE = "USRP-MPM"
 RESPONSE_SEP = ";"
diff --git a/mpm/python/usrp_mpm/ethtable.py b/mpm/python/usrp_mpm/ethtable.py
index f0c622492..9657f54c7 100644
--- a/mpm/python/usrp_mpm/ethtable.py
+++ b/mpm/python/usrp_mpm/ethtable.py
@@ -21,9 +21,9 @@ Ethernet dispatcher table control
 from builtins import str
 from builtins import object
 import netaddr
-from .mpmlog import get_logger
-from .uio import UIO
-from .net import get_mac_addr
+from usrp_mpm.mpmlog import get_logger
+from usrp_mpm.sys_utils.uio import UIO
+from usrp_mpm.sys_utils.net import get_mac_addr
 
 class EthDispatcherTable(object):
     """
diff --git a/mpm/python/usrp_mpm/liberiotable.py b/mpm/python/usrp_mpm/liberiotable.py
index 6f2454379..be19c7c17 100644
--- a/mpm/python/usrp_mpm/liberiotable.py
+++ b/mpm/python/usrp_mpm/liberiotable.py
@@ -9,8 +9,8 @@ Liberio DMA dispatcher table control
 
 from builtins import str
 from builtins import object
-from .mpmlog import get_logger
-from .uio import UIO
+from usrp_mpm.mpmlog import get_logger
+from usrp_mpm.sys_utils.uio import UIO
 
 class LiberioDispatcherTable(object):
     """
diff --git a/mpm/python/usrp_mpm/periph_manager/CMakeLists.txt b/mpm/python/usrp_mpm/periph_manager/CMakeLists.txt
index 49ca8e411..51bbf457c 100644
--- a/mpm/python/usrp_mpm/periph_manager/CMakeLists.txt
+++ b/mpm/python/usrp_mpm/periph_manager/CMakeLists.txt
@@ -24,7 +24,6 @@ SET(USRP_MPM_PERIPHMGR_FILES
     ${CMAKE_CURRENT_SOURCE_DIR}/base.py
     ${CMAKE_CURRENT_SOURCE_DIR}/n310.py
     ${CMAKE_CURRENT_SOURCE_DIR}/test.py
-    ${CMAKE_CURRENT_SOURCE_DIR}/udev.py
     )
 LIST(APPEND USRP_MPM_FILES ${USRP_MPM_PERIPHMGR_FILES})
 SET(USRP_MPM_FILES ${USRP_MPM_FILES} PARENT_SCOPE)
diff --git a/mpm/python/usrp_mpm/periph_manager/__init__.py.in b/mpm/python/usrp_mpm/periph_manager/__init__.py.in
index 34d29137a..5d99b0b5e 100644
--- a/mpm/python/usrp_mpm/periph_manager/__init__.py.in
+++ b/mpm/python/usrp_mpm/periph_manager/__init__.py.in
@@ -18,9 +18,7 @@
 periph_manager __init__.py
 """
 
-# This is where the import magic happens
-from .. import libpyusrp_periphs as lib
-from .. import dboard_manager
-from .. import mpmtypes
+from .base import PeriphManagerBase
 
+# This is where the import magic happens
 from .${MPM_DEVICE} import ${MPM_DEVICE} as periph_manager
diff --git a/mpm/python/usrp_mpm/periph_manager/base.py b/mpm/python/usrp_mpm/periph_manager/base.py
index ff86137df..c73ba6ef4 100644
--- a/mpm/python/usrp_mpm/periph_manager/base.py
+++ b/mpm/python/usrp_mpm/periph_manager/base.py
@@ -20,16 +20,16 @@ Mboard implementation base class
 
 from __future__ import print_function
 import os
-from concurrent import futures
 from hashlib import md5
+from concurrent import futures
 from builtins import str
 from builtins import range
 from builtins import object
 from six import iteritems, itervalues
-from ..mpmlog import get_logger
-from .udev import get_eeprom_paths
-from .udev import get_spidev_nodes
-from usrp_mpm import dtoverlay
+from usrp_mpm.mpmlog import get_logger
+from usrp_mpm.sys_utils.udev import get_eeprom_paths
+from usrp_mpm.sys_utils.udev import get_spidev_nodes
+from usrp_mpm.sys_utils import dtoverlay
 from usrp_mpm import eeprom
 from usrp_mpm.rpc_server import no_claim, no_rpc
 
@@ -37,7 +37,7 @@ def get_dboard_class_from_pid(pid):
     """
     Given a PID, return a dboard class initializer callable.
     """
-    from .. import dboard_manager
+    from usrp_mpm import dboard_manager
     for member in itervalues(dboard_manager.__dict__):
         try:
             if issubclass(member, dboard_manager.DboardManagerBase) and \
diff --git a/mpm/python/usrp_mpm/periph_manager/n310.py b/mpm/python/usrp_mpm/periph_manager/n310.py
index 384c69e97..ed1b5d164 100644
--- a/mpm/python/usrp_mpm/periph_manager/n310.py
+++ b/mpm/python/usrp_mpm/periph_manager/n310.py
@@ -25,17 +25,13 @@ import shutil
 import subprocess
 from six import iteritems, itervalues
 from builtins import object
-from .base import PeriphManagerBase
-from ..net import get_iface_addrs
-from ..net import byte_to_mac
-from ..mpmtypes import SID
+from usrp_mpm.periph_manager import PeriphManagerBase
+from usrp_mpm.mpmtypes import SID
 from usrp_mpm.rpc_server import no_rpc
-from usrp_mpm import net
-from usrp_mpm import dtoverlay
+from usrp_mpm.sys_utils import dtoverlay
+from usrp_mpm.sys_utils.sysfs_gpio import SysFSGPIO
+from usrp_mpm.sys_utils.uio import UIO
 from usrp_mpm.xports import XportMgrUDP, XportMgrLiberio
-from ..sysfs_gpio import SysFSGPIO
-from .. import libpyusrp_periphs as lib
-from ..uio import UIO
 
 N3XX_DEFAULT_EXT_CLOCK_FREQ = 10e6
 N3XX_DEFAULT_CLOCK_SOURCE = 'external'
diff --git a/mpm/python/usrp_mpm/periph_manager/test.py b/mpm/python/usrp_mpm/periph_manager/test.py
index 03bd28956..dd99b56b2 100644
--- a/mpm/python/usrp_mpm/periph_manager/test.py
+++ b/mpm/python/usrp_mpm/periph_manager/test.py
@@ -19,10 +19,10 @@ test periph_manager implementation module
 """
 
 from __future__ import print_function
-from .base import PeriphManagerBase
-from . import dboard_manager
 import random
 import string
+from usrp_mpm.periph_manager import PeriphManagerBase
+from usrp_mpm import dboard_manager
 
 
 class test(PeriphManagerBase):
diff --git a/mpm/python/usrp_mpm/rpc_server.py b/mpm/python/usrp_mpm/rpc_server.py
index 086ba5812..d645cb396 100644
--- a/mpm/python/usrp_mpm/rpc_server.py
+++ b/mpm/python/usrp_mpm/rpc_server.py
@@ -33,7 +33,7 @@ monkey.patch_all()
 from builtins import str, bytes
 from builtins import range
 from mprpc import RPCServer
-from .mpmlog import get_main_logger
+from usrp_mpm.mpmlog import get_main_logger
 
 TIMEOUT_INTERVAL = 3.0 # Seconds before claim expires
 TOKEN_LEN = 16 # Length of the token string
diff --git a/mpm/python/usrp_mpm/sys_utils/CMakeLists.txt b/mpm/python/usrp_mpm/sys_utils/CMakeLists.txt
new file mode 100644
index 000000000..1b5a4ed0e
--- /dev/null
+++ b/mpm/python/usrp_mpm/sys_utils/CMakeLists.txt
@@ -0,0 +1,18 @@
+#
+# Copyright 2017 Ettus Research, National Instruments Company
+#
+# SPDX-License-Identifier: GPL-3.0
+#
+
+SET(USRP_MPM_FILES ${USRP_MPM_FILES})
+SET(USRP_MPM_SYSUTILS_FILES
+    ${CMAKE_CURRENT_SOURCE_DIR}/__init__.py
+    ${CMAKE_CURRENT_SOURCE_DIR}/dtoverlay.py
+    ${CMAKE_CURRENT_SOURCE_DIR}/net.py
+    ${CMAKE_CURRENT_SOURCE_DIR}/sysfs_gpio.py
+    ${CMAKE_CURRENT_SOURCE_DIR}/udev.py
+    ${CMAKE_CURRENT_SOURCE_DIR}/uio.py
+)
+LIST(APPEND USRP_MPM_FILES ${USRP_MPM_SYSUTILS_FILES})
+SET(USRP_MPM_FILES ${USRP_MPM_FILES} PARENT_SCOPE)
+
diff --git a/mpm/python/usrp_mpm/sys_utils/__init__.py b/mpm/python/usrp_mpm/sys_utils/__init__.py
new file mode 100644
index 000000000..61be8ac53
--- /dev/null
+++ b/mpm/python/usrp_mpm/sys_utils/__init__.py
@@ -0,0 +1,11 @@
+#
+# Copyright 2017 Ettus Research, National Instruments Company
+#
+# SPDX-License-Identifier: GPL-3.0
+#
+"""
+System/OS Utilities
+
+These are convenience functions to access Linux subsystems.
+"""
+
diff --git a/mpm/python/usrp_mpm/dtoverlay.py b/mpm/python/usrp_mpm/sys_utils/dtoverlay.py
index 7f1bf653f..577bafed9 100644
--- a/mpm/python/usrp_mpm/dtoverlay.py
+++ b/mpm/python/usrp_mpm/sys_utils/dtoverlay.py
@@ -19,7 +19,7 @@ Manipulation of device tree overlays (Linux kernel)
 """
 
 import os
-from .mpmlog import get_logger
+from usrp_mpm.mpmlog import get_logger
 
 SYSFS_OVERLAY_BASE_DIR = '/sys/kernel/config/device-tree/overlays'
 OVERLAY_DEFAULT_PATH = '/lib/firmware'
diff --git a/mpm/python/usrp_mpm/net.py b/mpm/python/usrp_mpm/sys_utils/net.py
index be2d3f754..e3deea3e7 100644
--- a/mpm/python/usrp_mpm/net.py
+++ b/mpm/python/usrp_mpm/sys_utils/net.py
@@ -21,7 +21,7 @@ import itertools
 import socket
 from six import iteritems
 from pyroute2 import IPRoute
-from .mpmlog import get_logger
+from usrp_mpm.mpmlog import get_logger
 
 
 def get_valid_interfaces(iface_list):
diff --git a/mpm/python/usrp_mpm/sysfs_gpio.py b/mpm/python/usrp_mpm/sys_utils/sysfs_gpio.py
index b2d982059..f8384a3b8 100644
--- a/mpm/python/usrp_mpm/sysfs_gpio.py
+++ b/mpm/python/usrp_mpm/sys_utils/sysfs_gpio.py
@@ -21,7 +21,7 @@ Access to GPIOs mapped into the PS via sysfs
 import os
 from builtins import object
 import pyudev
-from .mpmlog import get_logger
+from usrp_mpm.mpmlog import get_logger
 
 GPIO_SYSFS_BASE_DIR = '/sys/class/gpio'
 GPIO_SYSFS_LABELFILE = 'label'
diff --git a/mpm/python/usrp_mpm/periph_manager/udev.py b/mpm/python/usrp_mpm/sys_utils/udev.py
index 33cb3367a..87d264d2d 100644
--- a/mpm/python/usrp_mpm/periph_manager/udev.py
+++ b/mpm/python/usrp_mpm/sys_utils/udev.py
@@ -17,7 +17,6 @@
 
 import os
 import pyudev
-from ..mpmlog import get_logger
 
 def get_eeprom_paths(address):
     """
diff --git a/mpm/python/usrp_mpm/uio.py b/mpm/python/usrp_mpm/sys_utils/uio.py
index 40991f1eb..c07227776 100644
--- a/mpm/python/usrp_mpm/uio.py
+++ b/mpm/python/usrp_mpm/sys_utils/uio.py
@@ -24,7 +24,7 @@ import mmap
 from builtins import hex
 from builtins import object
 import pyudev
-from .mpmlog import get_logger
+from usrp_mpm.mpmlog import get_logger
 
 UIO_SYSFS_BASE_DIR = '/sys/class/uio'
 UIO_DEV_BASE_DIR = '/dev'
diff --git a/mpm/python/usrp_mpm/xports/xportmgr_liberio.py b/mpm/python/usrp_mpm/xports/xportmgr_liberio.py
index 29a3d6673..8ac2f06f3 100644
--- a/mpm/python/usrp_mpm/xports/xportmgr_liberio.py
+++ b/mpm/python/usrp_mpm/xports/xportmgr_liberio.py
@@ -9,7 +9,7 @@ Liberio Transport manager
 
 from builtins import object
 from usrp_mpm.liberiotable import LiberioDispatcherTable
-from usrp_mpm import libpyusrp_periphs as lib
+from usrp_mpm import lib
 
 class XportMgrLiberio(object):
     """
diff --git a/mpm/python/usrp_mpm/xports/xportmgr_udp.py b/mpm/python/usrp_mpm/xports/xportmgr_udp.py
index 18c736150..18573bad9 100644
--- a/mpm/python/usrp_mpm/xports/xportmgr_udp.py
+++ b/mpm/python/usrp_mpm/xports/xportmgr_udp.py
@@ -10,9 +10,9 @@ UDP Transport manager
 from builtins import object
 from six import iteritems, itervalues
 from usrp_mpm.ethtable import EthDispatcherTable
-from usrp_mpm import net
+from usrp_mpm.sys_utils import net
 from usrp_mpm.mpmtypes import SID
-from usrp_mpm import libpyusrp_periphs as lib
+from usrp_mpm import lib
 
 class XportMgrUDP(object):
     """