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| author | Ashish Chaudhari <ashish@ettus.com> | 2017-12-19 16:54:35 -0800 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2017-12-22 15:06:03 -0800 |
| commit | 2e32f96291ac9c0e4d6514d6e4f8edc36ef4d426 (patch) | |
| tree | 4f66895d68d6996e316ee0eb585173a7f4a3a8f9 /mpm/python | |
| parent | 7ca25b6f1f3e111578993e6e8fdd90bdbf2fa7d6 (diff) | |
| download | uhd-2e32f96291ac9c0e4d6514d6e4f8edc36ef4d426.tar.gz uhd-2e32f96291ac9c0e4d6514d6e4f8edc36ef4d426.tar.bz2 uhd-2e32f96291ac9c0e4d6514d6e4f8edc36ef4d426.zip | |
n3xx: Updated Aurora BIST reg offsets
- Aurora registers moved around after SFP refactoring
in the FPGA. Reflecting changes in MPM
Diffstat (limited to 'mpm/python')
| -rw-r--r-- | mpm/python/usrp_mpm/aurora_control.py | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/mpm/python/usrp_mpm/aurora_control.py b/mpm/python/usrp_mpm/aurora_control.py index b679ce693..b78960007 100644 --- a/mpm/python/usrp_mpm/aurora_control.py +++ b/mpm/python/usrp_mpm/aurora_control.py @@ -27,14 +27,13 @@ class AuroraControl(object): Controls an Aurora core. """ # These are relative addresses - REG_AURORA_MAC_CTRL = 0x30 - REG_AURORA_MAC_CTRL_STATUS = 0x30 - REG_AURORA_PHY_CTRL_STATUS = 0x34 - REG_AURORA_OVERRUNS = 0x38 - REG_CHECKSUM_ERRORS = 0x3C - REG_BIST_CHECKER_SAMPS = 0x40 - REG_BIST_CHECKER_ERRORS = 0x44 - REG_AURORA_ENABLED_CHECK = 0x48 + REG_AURORA_PORT_INFO = 0x00 + REG_AURORA_MAC_CTRL_STATUS = 0x04 + REG_AURORA_PHY_CTRL_STATUS = 0x08 + REG_AURORA_OVERRUNS = 0x20 + REG_CHECKSUM_ERRORS = 0x24 + REG_BIST_CHECKER_SAMPS = 0x28 + REG_BIST_CHECKER_ERRORS = 0x2C MAC_STATUS_LINK_UP_MSK = 0x00000001 MAC_STATUS_HARD_ERR_MSK = 0x00000002 @@ -45,7 +44,7 @@ class AuroraControl(object): RATE_RES_BITS = 6 - DEFAULT_BUS_CLK_RATE = 208e6 + DEFAULT_BUS_CLK_RATE = 200e6 def __init__(self, peeker_poker32, base_addr=None, bus_clk_rate=None): assert hasattr(peeker_poker32, 'peek32') \ @@ -111,7 +110,7 @@ class AuroraControl(object): def set_mac_ctrl(self, mac_ctrl_word): " Write to the MAC ctrl register " self.log.debug("Setting MAC ctrl word to: 0x{:08X}".format(mac_ctrl_word)) - self.poke32(self.REG_AURORA_MAC_CTRL, mac_ctrl_word) + self.poke32(self.REG_AURORA_MAC_CTRL_STATUS, mac_ctrl_word) def set_bist_checker_and_gen(self, enable): " Enable or disable Aurora BIST: Checker + Generator " |