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authorSamuel O'Brien <sam.obrien@ni.com>2020-07-30 13:53:44 -0500
committerAaron Rossetto <aaron.rossetto@ni.com>2020-10-28 15:25:48 -0500
commit5df8202c0cb88fb5c7629fbf0ce5bed32c96e70d (patch)
treedb1755242b6f8267bb918c860bd0b2350c229ae9 /mpm/python/usrp_mpm/simulator/sim_dboard.py
parent687ed5bba07559a314d56e70b0eb727c7c8d9cbf (diff)
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sim: Move Hardware Specific to Config File
This commit moves various magic numbers and hardware specific settings into the configuration file. It also provides default presets for said configuration files which can be inherited from. Signed-off-by: Samuel O'Brien <sam.obrien@ni.com>
Diffstat (limited to 'mpm/python/usrp_mpm/simulator/sim_dboard.py')
-rw-r--r--mpm/python/usrp_mpm/simulator/sim_dboard.py34
1 files changed, 34 insertions, 0 deletions
diff --git a/mpm/python/usrp_mpm/simulator/sim_dboard.py b/mpm/python/usrp_mpm/simulator/sim_dboard.py
index a264eae9c..90f8be724 100644
--- a/mpm/python/usrp_mpm/simulator/sim_dboard.py
+++ b/mpm/python/usrp_mpm/simulator/sim_dboard.py
@@ -7,6 +7,11 @@ from usrp_mpm.dboard_manager import DboardManagerBase
from usrp_mpm.mpmlog import get_logger
from usrp_mpm.mpmutils import to_native_str
+registry = {}
+
+def register_dboard_class(cls):
+ registry[cls.__name__] = cls
+
class SimulatedDboardBase(DboardManagerBase):
"""
A class to simulate daughterboards in a simulated device.
@@ -57,3 +62,32 @@ class SimulatedDboardBase(DboardManagerBase):
self.log.debug("Called {} with args: {}".format(prop_name, args))
return func(*args)
setattr(self, prop_name, wrapped_func)
+
+class SimulatedCatalinaDboard(SimulatedDboardBase):
+ pids = [0x0110]
+
+ extra_methods = [
+ ("set_gain", lambda target, gain: gain),
+ ("catalina_tune", lambda which, freq: freq),
+ ("set_bw_filter", lambda which, freq: freq),
+ "set_dc_offset_auto",
+ "set_iq_balance_auto",
+ "set_agc",
+ "set_active_chains",
+ "set_timing_mode",
+ "data_port_loopback"
+ ]
+
+ def __init__(self, slot_idx, clock_rate_cb, **kwargs):
+ super().__init__(slot_idx, **kwargs)
+ self.clock_rate_cb = clock_rate_cb
+ self.master_clock_rate = 122.88e6
+
+ def get_master_clock_rate(self):
+ return self.master_clock_rate
+
+ def set_catalina_clock_rate(self, rate):
+ self.clock_rate_cb(rate)
+ return rate
+
+register_dboard_class(SimulatedCatalinaDboard)