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| author | Mark Meserve <mark.meserve@ni.com> | 2018-10-15 15:50:50 -0500 |
|---|---|---|
| committer | Brent Stapleton <bstapleton@g.hmc.edu> | 2018-10-18 18:15:25 -0700 |
| commit | d0de7a5812ca1e4caf5b88a075f45a320b29f4c4 (patch) | |
| tree | 948adb721375091b238483ddc6da21618c1016aa /mpm/python/usrp_mpm/periph_manager | |
| parent | cb0a07aa04048ded29b202df0cd9aeb8094a8b20 (diff) | |
| download | uhd-d0de7a5812ca1e4caf5b88a075f45a320b29f4c4.tar.gz uhd-d0de7a5812ca1e4caf5b88a075f45a320b29f4c4.tar.bz2 uhd-d0de7a5812ca1e4caf5b88a075f45a320b29f4c4.zip | |
mpm: identify sysfs gpios more generically
- Allow generic path names to be given for each search parameter instead of
only checking the label
Diffstat (limited to 'mpm/python/usrp_mpm/periph_manager')
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/e320_periphs.py | 2 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/e320_periphs.py b/mpm/python/usrp_mpm/periph_manager/e320_periphs.py index f5c82c0dd..cf9a6335f 100644 --- a/mpm/python/usrp_mpm/periph_manager/e320_periphs.py +++ b/mpm/python/usrp_mpm/periph_manager/e320_periphs.py @@ -37,7 +37,7 @@ class FrontpanelGPIO(GPIOBank): def __init__(self, ddr): GPIOBank.__init__( self, - 'zynq_gpio', + {'label': 'zynq_gpio'}, self.FP_GPIO_OFFSET + self.EMIO_BASE, 0xFF, # use_mask ddr diff --git a/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py b/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py index 0bfae94e1..775431050 100644 --- a/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py +++ b/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py @@ -99,7 +99,7 @@ class TCA6424(object): self.pins = self.pins_list[1] default_val = 0x860101 if rev == 2 else 0x860780 - self._gpios = SysFSGPIO('tca6424', 0xFFF7FF, 0x86F7FF, default_val) + self._gpios = SysFSGPIO({'label': 'tca6424'}, 0xFFF7FF, 0x86F7FF, default_val) def set(self, name, value=None): """ @@ -132,7 +132,7 @@ class FrontpanelGPIO(GPIOBank): def __init__(self, ddr): GPIOBank.__init__( self, - 'zynq_gpio', + {'label': 'zynq_gpio'}, self.FP_GPIO_OFFSET + self.EMIO_BASE, 0xFFF, # use_mask ddr @@ -151,7 +151,7 @@ class BackpanelGPIO(GPIOBank): def __init__(self): GPIOBank.__init__( self, - 'zynq_gpio', + {'label': 'zynq_gpio'}, self.BP_GPIO_OFFSET + self.EMIO_BASE, 0x7, # use_mask 0x7, # ddr |