diff options
| author | Martin Braun <martin.braun@ettus.com> | 2017-07-12 16:32:05 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2017-12-22 15:04:00 -0800 |
| commit | 7cd675833655829655176fb17c9c592aefb63c55 (patch) | |
| tree | 29d757f6c551cd591b6ca3d8c82915eddc007b44 /mpm/python/usrp_mpm/periph_manager | |
| parent | e5a7be445377621ab68740487ed2e0baba5347bc (diff) | |
| download | uhd-7cd675833655829655176fb17c9c592aefb63c55.tar.gz uhd-7cd675833655829655176fb17c9c592aefb63c55.tar.bz2 uhd-7cd675833655829655176fb17c9c592aefb63c55.zip | |
n310/eiscat: Removed 20 MHz as a valid ref clock frequency
Diffstat (limited to 'mpm/python/usrp_mpm/periph_manager')
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/n310.py | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/n310.py b/mpm/python/usrp_mpm/periph_manager/n310.py index 343bab707..24b2cc742 100644 --- a/mpm/python/usrp_mpm/periph_manager/n310.py +++ b/mpm/python/usrp_mpm/periph_manager/n310.py @@ -352,6 +352,9 @@ class n310(PeriphManagerBase): self._gpios.reset("CLK-MAINREF-SEL1") self._clock_source = clock_source ref_clk_freq = self.get_ref_clock_freq() + self.log.info("Reference clock frequency is: {} MHz".format( + ref_clk_freq/1e6 + )) for slot, dboard in enumerate(self.dboards): if hasattr(dboard, 'update_ref_clock_freq'): self.log.trace( @@ -368,6 +371,8 @@ class n310(PeriphManagerBase): Will throw if it's not a valid value. """ assert freq in (10e6, 20e6, 25e6) + self.log.debug("We've been told the external reference clock " \ + "frequency is {} MHz.".format(freq/1e6)) self._ext_clock_freq = freq def get_ref_clock_freq(self): |