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author | Trung Tran <trung.tran@ettus.com> | 2018-10-09 23:26:15 -0700 |
---|---|---|
committer | Martin Braun <martin.braun@ettus.com> | 2018-10-12 10:59:02 -0700 |
commit | 22ec3e4bd6a489d1809760e3fedcd6892798c0e0 (patch) | |
tree | 45adeaceec7489801c1e7e51779e3ce491d7c6ea /mpm/python/usrp_mpm/periph_manager | |
parent | a5b1b401d1d60f2575066e0d76b8ff7055a3eb04 (diff) | |
download | uhd-22ec3e4bd6a489d1809760e3fedcd6892798c0e0.tar.gz uhd-22ec3e4bd6a489d1809760e3fedcd6892798c0e0.tar.bz2 uhd-22ec3e4bd6a489d1809760e3fedcd6892798c0e0.zip |
mpm: dboard_manager: add more args to update_ref_clock_freq
Summary:
This change will allow correct args to pass from mboard to dboards,
that in turn can be useful for dboard manager.
Details:
In N310, the dboard manager needs the time source to be updated before
calling update_ref_clock_source(), because it will trigger a reinit of
the dboard, for which the time_source is essential to determine correct
clock synchronizer settings.
The special case is the white rabbit time source needs a different
internal ref_clock_frequency for the clock synchronizer than the passed
in ref_clock_freq.
Diffstat (limited to 'mpm/python/usrp_mpm/periph_manager')
-rw-r--r-- | mpm/python/usrp_mpm/periph_manager/n3xx.py | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/n3xx.py b/mpm/python/usrp_mpm/periph_manager/n3xx.py index 2615284dd..ccdf29815 100644 --- a/mpm/python/usrp_mpm/periph_manager/n3xx.py +++ b/mpm/python/usrp_mpm/periph_manager/n3xx.py @@ -628,12 +628,13 @@ class n3xx(ZynqComponents, PeriphManagerBase): raise RuntimeError("Failed to lock SFP timebase.") # Update the DB with the correct Ref Clock frequency and force a re-init. for slot, dboard in enumerate(self.dboards): - if hasattr(dboard, 'update_ref_clock_freq'): - self.log.trace( - "Updating reference clock on dboard %d to %f MHz...", - slot, ref_clk_freq/1e6 - ) - dboard.update_ref_clock_freq(ref_clk_freq) + self.log.trace( + "Updating reference clock on dboard %d to %f MHz...", + slot, ref_clk_freq/1e6 + ) + dboard.update_ref_clock_freq(ref_clk_freq, + time_source=time_source, + clock_source=clock_source) def set_ref_clock_freq(self, freq): """ |