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author | Samuel O'Brien <sam.obrien@ni.com> | 2020-07-21 13:59:39 -0500 |
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committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2020-10-07 15:29:19 -0500 |
commit | bfff8b79b950f2f1cebfd2db662a4205df5da65a (patch) | |
tree | 58ebe4d31a9d0c459f03454ebded8bb695a6651d /mpm/python/usrp_mpm/periph_manager/sim.py | |
parent | 6394a7c6ea395e2d21c3e2b9e43e1b2dc84666b5 (diff) | |
download | uhd-bfff8b79b950f2f1cebfd2db662a4205df5da65a.tar.gz uhd-bfff8b79b950f2f1cebfd2db662a4205df5da65a.tar.bz2 uhd-bfff8b79b950f2f1cebfd2db662a4205df5da65a.zip |
sim: Add Daughterboard Methods
This commit adds daughterboard simulation to the simulator. There is a
sim_dboard class which registers it's methods with the rpc server. These
methods are visible over mpm as well as the mpm_shell.
Signed-off-by: Samuel O'Brien <sam.obrien@ni.com>
Diffstat (limited to 'mpm/python/usrp_mpm/periph_manager/sim.py')
-rw-r--r-- | mpm/python/usrp_mpm/periph_manager/sim.py | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/sim.py b/mpm/python/usrp_mpm/periph_manager/sim.py index 00ba5ba38..7c8baeb8f 100644 --- a/mpm/python/usrp_mpm/periph_manager/sim.py +++ b/mpm/python/usrp_mpm/periph_manager/sim.py @@ -6,9 +6,8 @@ """ usrp simulation module -This module is used to emulate a usrp when running on a standard -computer. You can build mpm in this configuration by using the cmake -flag -DMPM_DEVICE=sim +This module is used to emulate simulated devices. You can build mpm in this +configuration by using the cmake flag -DMPM_DEVICE=sim """ from pyroute2 import IPRoute @@ -16,6 +15,7 @@ from usrp_mpm.xports import XportMgrUDP from usrp_mpm.mpmlog import get_logger from usrp_mpm.rpc_server import no_claim from usrp_mpm.periph_manager import PeriphManagerBase +from usrp_mpm.simulator.sim_dboard_catalina import SimulatedCatalinaDboard CLOCK_SOURCE_INTERNAL = "internal" @@ -91,6 +91,9 @@ class sim(PeriphManagerBase): if not args.get('skip_boot_init', False): self.init(args) + def _simulator_frequency(self, freq): + self.log.debug("Setting Simulator Sample Frequency to {}".format(freq)) + @classmethod def generate_device_info(cls, eeprom_md, mboard_info, dboard_infos): """ @@ -144,6 +147,10 @@ class sim(PeriphManagerBase): # Init complete. self.log.debug("Device info: {}".format(self.device_info)) + def _init_dboards(self, dboard_infos, override_dboard_pids, default_args): + self.dboards.append(SimulatedCatalinaDboard(E320_DBOARD_SLOT_IDX, self._simulator_frequency)) + self.log.info("Found %d daughterboard(s).", len(self.dboards)) + ########################################################################### # Device info ########################################################################### @@ -218,10 +225,6 @@ class sim(PeriphManagerBase): ####################################################################### # Timekeeper API ####################################################################### - def get_master_clock_rate(self): - """ Return the master clock rate set during init """ - return self._master_clock_rate - def get_num_timekeepers(self): """ Return the number of timekeepers |