diff options
author | Martin Braun <martin.braun@ettus.com> | 2019-09-09 16:29:32 -0700 |
---|---|---|
committer | Martin Braun <martin.braun@ettus.com> | 2019-11-26 12:21:33 -0800 |
commit | 025ffdce3475585b3f65e955af32afbab9181e13 (patch) | |
tree | faea7b200ec2fa09d61224f21dd8aa7302b011b4 /mpm/python/usrp_mpm/periph_manager/e31x.py | |
parent | d76cca76dd7699ed224b38cd30146c25ad2ac1f8 (diff) | |
download | uhd-025ffdce3475585b3f65e955af32afbab9181e13.tar.gz uhd-025ffdce3475585b3f65e955af32afbab9181e13.tar.bz2 uhd-025ffdce3475585b3f65e955af32afbab9181e13.zip |
mpm: Move common mboard regs code to common location
This assumes an existence of mboard_regs_control in PeriphManagerBase
and implements most TK controls there. All the *_periphs.py files can
now use a common class for registers, including the TK access, but also
git hash, build date, and device ID access.
This also fixes two issues:
- set_timekeeper_time() and set_tick_period() had a bug that would
incorrectly calculate the upper 32 bits of their respective registers.
- N3xx had a bug that would swap around set time now and next PPS. This
got auto-fixed because the common code never had this bug.
Diffstat (limited to 'mpm/python/usrp_mpm/periph_manager/e31x.py')
-rw-r--r-- | mpm/python/usrp_mpm/periph_manager/e31x.py | 70 |
1 files changed, 0 insertions, 70 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/e31x.py b/mpm/python/usrp_mpm/periph_manager/e31x.py index 573e75d55..8ba8ff034 100644 --- a/mpm/python/usrp_mpm/periph_manager/e31x.py +++ b/mpm/python/usrp_mpm/periph_manager/e31x.py @@ -509,39 +509,6 @@ class e31x(ZynqComponents, PeriphManagerBase): }) return device_info - def set_device_id(self, device_id): - """ - Sets the device ID for this motherboard. - The device ID is used to identify the RFNoC components associated with - this motherboard. - """ - self.log.debug("Setting device ID to `{}'".format(device_id)) - self.mboard_regs_control.set_device_id(device_id) - - def get_device_id(self): - """ - Gets the device ID for this motherboard. - The device ID is used to identify the RFNoC components associated with - this motherboard. - """ - return self.mboard_regs_control.get_device_id() - - def get_proto_ver(self): - """ - Return RFNoC protocol version - """ - proto_ver = self.mboard_regs_control.get_proto_ver() - self.log.debug("RFNoC protocol version supported by this device is {}".format(proto_ver)) - return proto_ver - - def get_chdr_width(self): - """ - Return RFNoC CHDR width - """ - chdr_width = self.mboard_regs_control.get_chdr_width() - self.log.debug("CHDR width supported by the device is {}".format(chdr_width)) - return chdr_width - ########################################################################### # Clock/Time API ########################################################################### @@ -738,43 +705,6 @@ class e31x(ZynqComponents, PeriphManagerBase): ####################################################################### # Timekeeper API ####################################################################### - def get_num_timekeepers(self): - """ - Return the number of timekeepers - """ - return self.mboard_regs_control.get_num_timekeepers() - - def get_timekeeper_time(self, tk_idx, last_pps): - """ - Get the time in ticks - - Arguments: - tk_idx: Index of timekeeper - next_pps: If True, get time at last PPS. Otherwise, get time now. - """ - return self.mboard_regs_control.get_timekeeper_time(tk_idx, last_pps) - - def set_timekeeper_time(self, tk_idx, ticks, next_pps): - """ - Set the time in ticks - - Arguments: - tk_idx: Index of timekeeper - ticks: Time in ticks - next_pps: If True, set time at next PPS. Otherwise, set time now. - """ - self.mboard_regs_control.set_timekeeper_time(tk_idx, ticks, next_pps) - - def set_tick_period(self, tk_idx, period_ns): - """ - Set the time per tick in nanoseconds (tick period) - - Arguments: - tk_idx: Index of timekeeper - period_ns: Period in nanoseconds - """ - self.mboard_regs_control.set_tick_period(tk_idx, period_ns) - def get_clocks(self): """ Gets the RFNoC-related clocks present in the FPGA design |