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| author | Mark Meserve <mark.meserve@ni.com> | 2018-10-17 15:46:41 -0500 |
|---|---|---|
| committer | Brent Stapleton <bstapleton@g.hmc.edu> | 2018-10-25 10:30:59 -0700 |
| commit | fad36514e56c2da459637b5abe261033e40fa8fd (patch) | |
| tree | 2eaccf932e4d30cec0dae17a83d104e3f005c864 /mpm/python/usrp_mpm/dboard_manager/mg_init.py | |
| parent | b8abcdbec3447f2c01e65b2b0282e8a9410cf579 (diff) | |
| download | uhd-fad36514e56c2da459637b5abe261033e40fa8fd.tar.gz uhd-fad36514e56c2da459637b5abe261033e40fa8fd.tar.bz2 uhd-fad36514e56c2da459637b5abe261033e40fa8fd.zip | |
nijesdcore: add variable configuration support
Diffstat (limited to 'mpm/python/usrp_mpm/dboard_manager/mg_init.py')
| -rw-r--r-- | mpm/python/usrp_mpm/dboard_manager/mg_init.py | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/mpm/python/usrp_mpm/dboard_manager/mg_init.py b/mpm/python/usrp_mpm/dboard_manager/mg_init.py index 62cc27a4f..d2b597c21 100644 --- a/mpm/python/usrp_mpm/dboard_manager/mg_init.py +++ b/mpm/python/usrp_mpm/dboard_manager/mg_init.py @@ -76,6 +76,11 @@ class MagnesiumInitManager(object): # Variable PPS delay before the RP/SP pulsers begin. Fixed value for the # N3xx devices. N3XX_INT_PPS_DELAY = 4 + # JESD core default configuration. + JESD_DEFAULT_ARGS = {"bypass_descrambler": False, + "lmfc_divider" : 20, + "rx_sysref_delay" : 8, + "tx_sysref_delay" : 11} def __init__(self, mg_class, spi_ifaces): self.mg_class = mg_class @@ -525,7 +530,7 @@ class MagnesiumInitManager(object): read_only=False ) as dboard_ctrl_regs: self.log.trace("Creating jesdcore object...") - jesdcore = nijesdcore.NIMgJESDCore(dboard_ctrl_regs, slot_idx) + jesdcore = nijesdcore.NIJESDCore(dboard_ctrl_regs, slot_idx, **self.JESD_DEFAULT_ARGS) # Now get cracking with the actual init sequence: self.log.trace("Creating dboard clock control object...") db_clk_control = DboardClockControl(dboard_ctrl_regs, self.log) |