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| author | Mark Meserve <mark.meserve@ni.com> | 2018-10-17 15:46:41 -0500 |
|---|---|---|
| committer | Brent Stapleton <bstapleton@g.hmc.edu> | 2018-10-25 10:30:59 -0700 |
| commit | fad36514e56c2da459637b5abe261033e40fa8fd (patch) | |
| tree | 2eaccf932e4d30cec0dae17a83d104e3f005c864 /mpm/python/usrp_mpm/dboard_manager/magnesium.py | |
| parent | b8abcdbec3447f2c01e65b2b0282e8a9410cf579 (diff) | |
| download | uhd-fad36514e56c2da459637b5abe261033e40fa8fd.tar.gz uhd-fad36514e56c2da459637b5abe261033e40fa8fd.tar.bz2 uhd-fad36514e56c2da459637b5abe261033e40fa8fd.zip | |
nijesdcore: add variable configuration support
Diffstat (limited to 'mpm/python/usrp_mpm/dboard_manager/magnesium.py')
| -rw-r--r-- | mpm/python/usrp_mpm/dboard_manager/magnesium.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/mpm/python/usrp_mpm/dboard_manager/magnesium.py b/mpm/python/usrp_mpm/dboard_manager/magnesium.py index 06dff175f..ca3c74e4b 100644 --- a/mpm/python/usrp_mpm/dboard_manager/magnesium.py +++ b/mpm/python/usrp_mpm/dboard_manager/magnesium.py @@ -422,7 +422,8 @@ class Magnesium(DboardManagerBase): db_clk_control = DboardClockControl(dboard_ctrl_regs, self.log) db_clk_control.reset_mmcm() # Place the JESD204b core in reset, mainly to reset QPLL/CPLLs. - jesdcore = nijesdcore.NIMgJESDCore(dboard_ctrl_regs, self.slot_idx) + jesdcore = nijesdcore.NIJESDCore(dboard_ctrl_regs, self.slot_idx, + **MagnesiumInitManager.JESD_DEFAULT_ARGS) jesdcore.reset() # The reference clock is handled elsewhere since it is a motherboard- # level clock. |