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authordjepson1 <daniel.jepson@ni.com>2018-01-18 10:40:43 -0600
committerAshish Chaudhari <ashish.chaudhari@ettus.com>2018-03-07 12:40:28 -0800
commit7d0aec18905802ddc466e69055520e8c42cf23c8 (patch)
treefd4fb27263f06550d5697e75fd1f6a87aeaf9bb9 /mpm/python/usrp_mpm/dboard_manager/lmk_mg.py
parentf9a8098cae1575a34747af2e212248d3bb189783 (diff)
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tdc: support for tdc 2.0
Diffstat (limited to 'mpm/python/usrp_mpm/dboard_manager/lmk_mg.py')
-rw-r--r--mpm/python/usrp_mpm/dboard_manager/lmk_mg.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/mpm/python/usrp_mpm/dboard_manager/lmk_mg.py b/mpm/python/usrp_mpm/dboard_manager/lmk_mg.py
index e7327ee83..2f4d6a192 100644
--- a/mpm/python/usrp_mpm/dboard_manager/lmk_mg.py
+++ b/mpm/python/usrp_mpm/dboard_manager/lmk_mg.py
@@ -17,8 +17,8 @@ class LMK04828Mg(LMK04828):
"""
def __init__(self, regs_iface, spi_lock, ref_clock_freq, master_clock_freq, log=None):
LMK04828.__init__(self, regs_iface, log)
- self.log.trace("Using reference clock frequency: {} MHz".format(ref_clock_freq/1e6))
- self.log.trace("Using master clock frequency: {} MHz".format(master_clock_freq/1e6))
+ self.log.debug("Using reference clock frequency: {} MHz".format(ref_clock_freq/1e6))
+ self.log.debug("Using master clock frequency: {} MHz".format(master_clock_freq/1e6))
self.spi_lock = spi_lock
assert hasattr(self.spi_lock, 'lock')
assert hasattr(self.spi_lock, 'unlock')