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authorMartin Braun <martin.braun@ettus.com>2017-07-12 16:32:05 -0700
committerMartin Braun <martin.braun@ettus.com>2017-12-22 15:04:00 -0800
commit7cd675833655829655176fb17c9c592aefb63c55 (patch)
tree29d757f6c551cd591b6ca3d8c82915eddc007b44 /mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py
parente5a7be445377621ab68740487ed2e0baba5347bc (diff)
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n310/eiscat: Removed 20 MHz as a valid ref clock frequency
Diffstat (limited to 'mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py')
-rw-r--r--mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py6
1 files changed, 5 insertions, 1 deletions
diff --git a/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py b/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py
index 3affdc3e9..4bd9594d4 100644
--- a/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py
+++ b/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py
@@ -28,7 +28,11 @@ class LMK04828EISCAT(LMK04828):
def __init__(self, regs_iface, ref_clock_freq, slot=None):
LMK04828.__init__(self, regs_iface, slot)
self.log.trace("Using reference clock frequency {} MHz".format(ref_clock_freq/1e6))
- assert ref_clock_freq in (10e6, 20e6)
+ if ref_clock_freq != 10e6:
+ error_msg = "Invalid reference clock frequency: {} MHz. " \
+ "Must be 10 MHz.".format(ref_clock_freq)
+ self.log.error(error_msg)
+ raise RuntimeError(error_msg)
self.ref_clock_freq = ref_clock_freq
self.init()
self.config()