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| author | djepson1 <daniel.jepson@ni.com> | 2017-10-12 10:14:13 -0500 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2017-12-22 15:04:02 -0800 |
| commit | 5eb49364cea736d358ca005035ba50e772fae9fd (patch) | |
| tree | f36e529f17aec8affdf4391a27a890b8fe43e9cf /mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py | |
| parent | e212936218481b99a3f2e6283501ee6beaaa4d5a (diff) | |
| download | uhd-5eb49364cea736d358ca005035ba50e772fae9fd.tar.gz uhd-5eb49364cea736d358ca005035ba50e772fae9fd.tar.bz2 uhd-5eb49364cea736d358ca005035ba50e772fae9fd.zip | |
lmk: change holdover settings to reduce lock time
- Register 0x150 bit [1] to '0'
- Change lock detect to poll operation
Diffstat (limited to 'mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py')
| -rw-r--r-- | mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py b/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py index 4bd9594d4..774c10277 100644 --- a/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py +++ b/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py @@ -139,7 +139,7 @@ class LMK04828EISCAT(LMK04828): (0x14D, 0x00), # DAC Settings (defaults) (0x14E, 0x00), # DAC Settings (defaults) (0x14F, 0x7F), # DAC Settings (defaults) - (0x150, 0x03), # Holdover Settings (defaults) + (0x150, 0x00), # Holdover Settings; bits 0/1 = '0' per long PLL1 lock time debug (0x151, 0x02), # Holdover Settings (defaults) (0x152, 0x00), # Holdover Settings (defaults) (0x153, 0x00), # CLKin0_R divider [13:8], default = 0 @@ -175,6 +175,7 @@ class LMK04828EISCAT(LMK04828): (0x16D, 0x00), # PLL2 loop filter c = 10 pF (0x173, 0x00), # Do not power down PLL2 or prescaler )) + # TODO: change to Polling. time.sleep(1.0) # Increased time to wait for DAC and VCXO to settle. self.pokes8(( (0x182, 0x1), # Clear Lock Detect Sticky |