uhd: mpm: apply clang-format to all files

Applying formatting changes to all .cpp and .hpp files in the following
directories:
```
find host/examples/ -iname *.hpp -o -iname *.cpp | \
    xargs clang-format -i -style=file
find host/tests/ -iname *.hpp -o -iname *.cpp | \
    xargs clang-format -i -style=file
find host/lib/usrp/dboard/neon/ -iname *.hpp -o -iname *.cpp | \
    xargs clang-format -i -style=file
find host/lib/usrp/dboard/magnesium/ -iname *.hpp -o -iname *.cpp | \
    xargs clang-format -i -style=file
find host/lib/usrp/device3/ -iname *.hpp -o -iname *.cpp | \
    xargs clang-format -i -style=file
find host/lib/usrp/mpmd/ -iname *.hpp -o -iname *.cpp | \
    xargs clang-format -i -style=file
find host/lib/usrp/x300/ -iname *.hpp -o -iname *.cpp | \
    xargs clang-format -i -style=file
find host/utils/ -iname *.hpp -o -iname *.cpp | \
    xargs clang-format -i -style=file
find mpm/ -iname *.hpp -o -iname *.cpp | \
    xargs clang-format -i -style=file
```

Also formatted host/include/, except Cpp03 was used as a the language
standard instead of Cpp11.
```
sed -i 's/ Cpp11/ Cpp03/g' .clang-format
find host/include/ -iname *.hpp -o -iname *.cpp | \
    xargs clang-format -i -style=file
```

Formatting style was designated by the .clang-format file.

7 files changed, 932 insertions, 540 deletions

diff --git a/mpm/lib/mykonos/config/ad937x_config_t.cpp b/mpm/lib/mykonos/config/ad937x_config_t.cpp
index 9bebeafad..97651b0b4 100644
--- a/mpm/lib/mykonos/config/ad937x_config_t.cpp
+++ b/mpm/lib/mykonos/config/ad937x_config_t.cpp
@@ -7,87 +7,421 @@
 #include "ad937x_config_t.hpp"
 #include "ad937x_default_config.hpp"
 
-const int16_t ad937x_config_t::DEFAULT_TX_FIR[DEFAULT_TX_FIR_SIZE] =
-    {   -94,  -26,  282,  177, -438, -368,  756,  732,-1170,-1337, 1758, 2479,-2648,-5088, 4064,16760,
-      16759, 4110,-4881,-2247, 2888, 1917,-1440,-1296,  745,  828, -358, -474,  164,  298,  -16,  -94 };
-
-const int16_t ad937x_config_t::DEFAULT_TX_FIR_15366[DEFAULT_TX_FIR_SIZE] =
-    {     4,  -16,   -5,   75,  -13, -229,   85,  547, -293,-1158,  738, 2290,-1640,-4805, 3687,17108,
-      17108, 3687,-4805,-1640, 2290,  738,-1158, -293,  547,   85, -229,  -13,   75,   -5,  -16,    4 };
-
-const int16_t ad937x_config_t::DEFAULT_RX_FIR[DEFAULT_RX_FIR_SIZE] =
-    {   -20,    6,   66,   22, -128,  -54,  240,  126, -402, -248,  634,  444, -956, -756, 1400, 1244,
-      -2028,-2050, 2978, 3538,-4646,-7046, 9536,30880,30880, 9536,-7046,-4646, 3538, 2978,-2050,-2028,
-       1244, 1400, -756, -956,  444,  634, -248, -402,  126,  240,  -54, -128,   22,   66,    6,  -20 };
-
-const int16_t ad937x_config_t::DEFAULT_RX_FIR_15366[DEFAULT_RX_FIR_SIZE] =
-    {   -16,  -22,   18,   74,   24, -132, -152,  132,  372,   38, -598, -474,  638, 1178, -206,-1952,
-       -984, 2362, 3152,-1612,-6544,-2164,12806,26836,26836,12806,-2164,-6544,-1612, 3152, 2362, -984,
-      -1952, -206, 1178,  638, -474, -598,   38,  372,  132, -152, -132,   24,   74,   18,  -22,  -16 };
-
-const int16_t ad937x_config_t::DEFAULT_OBSRX_FIR[DEFAULT_RX_FIR_SIZE] =
-    {   -14,  -19,   44,   41,  -89,  -95,  175,  178, -303, -317,  499,  527, -779, -843, 1184, 1317,
-      -1781,-2059, 2760, 3350,-4962,-7433, 9822,32154,32154, 9822,-7433,-4962, 3350, 2760,-2059,-1781,
-       1317, 1184, -843, -779,  527,  499, -317, -303,  178,  175,  -95,  -89,   41,   44,  -19,  -14 };
-
-const int16_t ad937x_config_t::DEFAULT_OBSRX_FIR_15366[DEFAULT_RX_FIR_SIZE] =
-    {    -2,    3,   12,  -19,  -28,   44,   74,  -92, -169,  150,  353, -203, -671,  203, 1179,  -66,
-      -1952, -347, 3153, 1307,-5595,-4820,11323,29525,29525,11323,-4820,-5595, 1307, 3153, -347,-1952,
-        -66, 1179,  203, -671, -203,  353,  150, -169,  -92,   74,   44,  -28,  -19,   12,    3,   -2 };
-
-const int16_t ad937x_config_t::DEFAULT_SNIFFER_FIR[DEFAULT_RX_FIR_SIZE] =
-    {    -1,   -5,  -14,  -23,  -16,   24,   92,  137,   80, -120, -378, -471, -174,  507, 1174, 1183,
-         98,-1771,-3216,-2641,  942, 7027,13533,17738,17738,13533, 7027,  942,-2641,-3216,-1771,   98,
-       1183, 1174,  507, -174, -471, -378, -120,   80,  137,   92,   24,  -16,  -23,  -14,   -5,   -1 };
-
-const int16_t ad937x_config_t::DEFAULT_SNIFFER_FIR_15366[DEFAULT_RX_FIR_SIZE] =
-    {   10,    31,   59,   71,   30,  -92, -283, -456, -466, -175,  440, 1192, 1683, 1444,  198,-1871,
-     -3988, -4942,-3512,  958, 8118,16519,23993,28395,28395,23993,16519, 8118,  958,-3512,-4942,-3988,
-     -1871,   198, 1444, 1683, 1192,  440, -175, -466, -456, -283,  -92,   30,   71,   59,   31,   10 };
-
-ad937x_config_t::ad937x_config_t(spiSettings_t* sps, const size_t deserializer_lane_xbar) :
-    _rx(DEFAULT_RX_SETTINGS),
-    _rxProfile(DEFAULT_RX_PROFILE),
-    _framer(DEFAULT_FRAMER),
-    _rxGainCtrl(DEFAULT_RX_GAIN),
-    _rxPeakAgc(DEFAULT_RX_PEAK_AGC),
-    _rxPowerAgc(DEFAULT_RX_POWER_AGC),
-    _rxAgcCtrl(DEFAULT_RX_AGC_CTRL),
-
-    _tx(DEFAULT_TX_SETTINGS),
-    _txProfile(DEFAULT_TX_PROFILE),
-    _deframer(DEFAULT_DEFRAMER),
+const int16_t ad937x_config_t::DEFAULT_TX_FIR[DEFAULT_TX_FIR_SIZE] = {-94,
+    -26,
+    282,
+    177,
+    -438,
+    -368,
+    756,
+    732,
+    -1170,
+    -1337,
+    1758,
+    2479,
+    -2648,
+    -5088,
+    4064,
+    16760,
+    16759,
+    4110,
+    -4881,
+    -2247,
+    2888,
+    1917,
+    -1440,
+    -1296,
+    745,
+    828,
+    -358,
+    -474,
+    164,
+    298,
+    -16,
+    -94};
+
+const int16_t ad937x_config_t::DEFAULT_TX_FIR_15366[DEFAULT_TX_FIR_SIZE] = {4,
+    -16,
+    -5,
+    75,
+    -13,
+    -229,
+    85,
+    547,
+    -293,
+    -1158,
+    738,
+    2290,
+    -1640,
+    -4805,
+    3687,
+    17108,
+    17108,
+    3687,
+    -4805,
+    -1640,
+    2290,
+    738,
+    -1158,
+    -293,
+    547,
+    85,
+    -229,
+    -13,
+    75,
+    -5,
+    -16,
+    4};
+
+const int16_t ad937x_config_t::DEFAULT_RX_FIR[DEFAULT_RX_FIR_SIZE] = {-20,
+    6,
+    66,
+    22,
+    -128,
+    -54,
+    240,
+    126,
+    -402,
+    -248,
+    634,
+    444,
+    -956,
+    -756,
+    1400,
+    1244,
+    -2028,
+    -2050,
+    2978,
+    3538,
+    -4646,
+    -7046,
+    9536,
+    30880,
+    30880,
+    9536,
+    -7046,
+    -4646,
+    3538,
+    2978,
+    -2050,
+    -2028,
+    1244,
+    1400,
+    -756,
+    -956,
+    444,
+    634,
+    -248,
+    -402,
+    126,
+    240,
+    -54,
+    -128,
+    22,
+    66,
+    6,
+    -20};
+
+const int16_t ad937x_config_t::DEFAULT_RX_FIR_15366[DEFAULT_RX_FIR_SIZE] = {-16,
+    -22,
+    18,
+    74,
+    24,
+    -132,
+    -152,
+    132,
+    372,
+    38,
+    -598,
+    -474,
+    638,
+    1178,
+    -206,
+    -1952,
+    -984,
+    2362,
+    3152,
+    -1612,
+    -6544,
+    -2164,
+    12806,
+    26836,
+    26836,
+    12806,
+    -2164,
+    -6544,
+    -1612,
+    3152,
+    2362,
+    -984,
+    -1952,
+    -206,
+    1178,
+    638,
+    -474,
+    -598,
+    38,
+    372,
+    132,
+    -152,
+    -132,
+    24,
+    74,
+    18,
+    -22,
+    -16};
+
+const int16_t ad937x_config_t::DEFAULT_OBSRX_FIR[DEFAULT_RX_FIR_SIZE] = {-14,
+    -19,
+    44,
+    41,
+    -89,
+    -95,
+    175,
+    178,
+    -303,
+    -317,
+    499,
+    527,
+    -779,
+    -843,
+    1184,
+    1317,
+    -1781,
+    -2059,
+    2760,
+    3350,
+    -4962,
+    -7433,
+    9822,
+    32154,
+    32154,
+    9822,
+    -7433,
+    -4962,
+    3350,
+    2760,
+    -2059,
+    -1781,
+    1317,
+    1184,
+    -843,
+    -779,
+    527,
+    499,
+    -317,
+    -303,
+    178,
+    175,
+    -95,
+    -89,
+    41,
+    44,
+    -19,
+    -14};
+
+const int16_t ad937x_config_t::DEFAULT_OBSRX_FIR_15366[DEFAULT_RX_FIR_SIZE] = {-2,
+    3,
+    12,
+    -19,
+    -28,
+    44,
+    74,
+    -92,
+    -169,
+    150,
+    353,
+    -203,
+    -671,
+    203,
+    1179,
+    -66,
+    -1952,
+    -347,
+    3153,
+    1307,
+    -5595,
+    -4820,
+    11323,
+    29525,
+    29525,
+    11323,
+    -4820,
+    -5595,
+    1307,
+    3153,
+    -347,
+    -1952,
+    -66,
+    1179,
+    203,
+    -671,
+    -203,
+    353,
+    150,
+    -169,
+    -92,
+    74,
+    44,
+    -28,
+    -19,
+    12,
+    3,
+    -2};
+
+const int16_t ad937x_config_t::DEFAULT_SNIFFER_FIR[DEFAULT_RX_FIR_SIZE] = {-1,
+    -5,
+    -14,
+    -23,
+    -16,
+    24,
+    92,
+    137,
+    80,
+    -120,
+    -378,
+    -471,
+    -174,
+    507,
+    1174,
+    1183,
+    98,
+    -1771,
+    -3216,
+    -2641,
+    942,
+    7027,
+    13533,
+    17738,
+    17738,
+    13533,
+    7027,
+    942,
+    -2641,
+    -3216,
+    -1771,
+    98,
+    1183,
+    1174,
+    507,
+    -174,
+    -471,
+    -378,
+    -120,
+    80,
+    137,
+    92,
+    24,
+    -16,
+    -23,
+    -14,
+    -5,
+    -1};
+
+const int16_t ad937x_config_t::DEFAULT_SNIFFER_FIR_15366[DEFAULT_RX_FIR_SIZE] = {10,
+    31,
+    59,
+    71,
+    30,
+    -92,
+    -283,
+    -456,
+    -466,
+    -175,
+    440,
+    1192,
+    1683,
+    1444,
+    198,
+    -1871,
+    -3988,
+    -4942,
+    -3512,
+    958,
+    8118,
+    16519,
+    23993,
+    28395,
+    28395,
+    23993,
+    16519,
+    8118,
+    958,
+    -3512,
+    -4942,
+    -3988,
+    -1871,
+    198,
+    1444,
+    1683,
+    1192,
+    440,
+    -175,
+    -466,
+    -456,
+    -283,
+    -92,
+    30,
+    71,
+    59,
+    31,
+    10};
+
+ad937x_config_t::ad937x_config_t(spiSettings_t* sps, const size_t deserializer_lane_xbar)
+    : _rx(DEFAULT_RX_SETTINGS)
+    , _rxProfile(DEFAULT_RX_PROFILE)
+    , _framer(DEFAULT_FRAMER)
+    , _rxGainCtrl(DEFAULT_RX_GAIN)
+    , _rxPeakAgc(DEFAULT_RX_PEAK_AGC)
+    , _rxPowerAgc(DEFAULT_RX_POWER_AGC)
+    , _rxAgcCtrl(DEFAULT_RX_AGC_CTRL)
+    ,
+
+    _tx(DEFAULT_TX_SETTINGS)
+    , _txProfile(DEFAULT_TX_PROFILE)
+    , _deframer(DEFAULT_DEFRAMER)
+    ,
     // TODO: Remove if ADI ever fixes this
     // The TX bring up requires a valid ORX profile
     // https://github.com/EttusResearch/uhddev/blob/f0f8f58471c3fed94279c32f00e9f8da7db40efd/mpm/lib/mykonos/adi/mykonos.c#L16590
 
-    _obsRx(DEFAULT_ORX_SETTINGS),
-    _orxFramer(DEFAULT_ORX_FRAMER),
-    _orxProfile(DEFAULT_ORX_PROFILE),
-    _orxGainCtrl(DEFAULT_ORX_GAIN),
-    _orxPeakAgc(DEFAULT_ORX_PEAK_AGC),
-    _orxPowerAgc(DEFAULT_ORX_POWER_AGC),
-    _orxAgcCtrl(DEFAULT_ORX_AGC_CTRL),
+    _obsRx(DEFAULT_ORX_SETTINGS)
+    , _orxFramer(DEFAULT_ORX_FRAMER)
+    , _orxProfile(DEFAULT_ORX_PROFILE)
+    , _orxGainCtrl(DEFAULT_ORX_GAIN)
+    , _orxPeakAgc(DEFAULT_ORX_PEAK_AGC)
+    , _orxPowerAgc(DEFAULT_ORX_POWER_AGC)
+    , _orxAgcCtrl(DEFAULT_ORX_AGC_CTRL)
+    ,
 
     // TODO: Remove if ADI ever fixes this
     // ORX bring up requires a valid sniffer gain control struct
     // https://github.com/EttusResearch/uhddev/blob/f0f8f58471c3fed94279c32f00e9f8da7db40efd/mpm/lib/mykonos/adi/mykonos.c#L5752
 
-    _snifferGainCtrl(DEFAULT_SNIFFER_GAIN),
+    _snifferGainCtrl(DEFAULT_SNIFFER_GAIN)
+    ,
 
-    _armGpio(DEFAULT_ARM_GPIO),
-    _gpio3v3(DEFAULT_GPIO_3V3),
-    _gpio(DEFAULT_GPIO),
+    _armGpio(DEFAULT_ARM_GPIO)
+    , _gpio3v3(DEFAULT_GPIO_3V3)
+    , _gpio(DEFAULT_GPIO)
+    ,
 
-    _auxIo(DEFAULT_AUX_IO),
-    _clocks(DEFAULT_CLOCKS),
+    _auxIo(DEFAULT_AUX_IO)
+    , _clocks(DEFAULT_CLOCKS)
+    ,
 
-    tx_fir_config(DEFAULT_TX_FIR_GAIN, std::vector<int16_t>(DEFAULT_TX_FIR, DEFAULT_TX_FIR + DEFAULT_TX_FIR_SIZE)),
-    rx_fir_config(DEFAULT_RX_FIR_GAIN, std::vector<int16_t>(DEFAULT_RX_FIR, DEFAULT_RX_FIR + DEFAULT_RX_FIR_SIZE)),
-    _orx_fir_config(DEFAULT_RX_FIR_GAIN, std::vector<int16_t>(DEFAULT_OBSRX_FIR, DEFAULT_OBSRX_FIR + DEFAULT_RX_FIR_SIZE)),
-    _sniffer_rx_fir_config(DEFAULT_RX_FIR_GAIN, std::vector<int16_t>(DEFAULT_SNIFFER_FIR, DEFAULT_SNIFFER_FIR + DEFAULT_RX_FIR_SIZE))
+    tx_fir_config(DEFAULT_TX_FIR_GAIN,
+        std::vector<int16_t>(DEFAULT_TX_FIR, DEFAULT_TX_FIR + DEFAULT_TX_FIR_SIZE))
+    , rx_fir_config(DEFAULT_RX_FIR_GAIN,
+          std::vector<int16_t>(DEFAULT_RX_FIR, DEFAULT_RX_FIR + DEFAULT_RX_FIR_SIZE))
+    , _orx_fir_config(DEFAULT_RX_FIR_GAIN,
+          std::vector<int16_t>(
+              DEFAULT_OBSRX_FIR, DEFAULT_OBSRX_FIR + DEFAULT_RX_FIR_SIZE))
+    , _sniffer_rx_fir_config(DEFAULT_RX_FIR_GAIN,
+          std::vector<int16_t>(
+              DEFAULT_SNIFFER_FIR, DEFAULT_SNIFFER_FIR + DEFAULT_RX_FIR_SIZE))
 {
-    _device.spiSettings = sps;
+    _device.spiSettings                = sps;
     _deframer.deserializerLaneCrossbar = deserializer_lane_xbar;
 
     _init_pointers();
@@ -95,52 +429,51 @@ ad937x_config_t::ad937x_config_t(spiSettings_t* sps, const size_t deserializer_l
     device = &_device;
 }
 
-// This function sets up all the pointers in all of our local members that represent the device struct
-// This function should only be called during construction.
+// This function sets up all the pointers in all of our local members that represent the
+// device struct This function should only be called during construction.
 void ad937x_config_t::_init_pointers()
 {
-    _device.rx = &_rx;
-    _device.tx = &_tx;
-    _device.obsRx = &_obsRx;
-    _device.auxIo = &_auxIo;
+    _device.rx     = &_rx;
+    _device.tx     = &_tx;
+    _device.obsRx  = &_obsRx;
+    _device.auxIo  = &_auxIo;
     _device.clocks = &_clocks;
 
-    _rx.rxProfile = &_rxProfile;
-    _rx.framer = &_framer;
-    _rx.rxGainCtrl = &_rxGainCtrl;
-    _rx.rxAgcCtrl = &_rxAgcCtrl;
-    _rxProfile.rxFir = rx_fir_config.fir;
+    _rx.rxProfile               = &_rxProfile;
+    _rx.framer                  = &_framer;
+    _rx.rxGainCtrl              = &_rxGainCtrl;
+    _rx.rxAgcCtrl               = &_rxAgcCtrl;
+    _rxProfile.rxFir            = rx_fir_config.fir;
     _rxProfile.customAdcProfile = nullptr;
-    _rxAgcCtrl.peakAgc = &_rxPeakAgc;
-    _rxAgcCtrl.powerAgc = &_rxPowerAgc;
+    _rxAgcCtrl.peakAgc          = &_rxPeakAgc;
+    _rxAgcCtrl.powerAgc         = &_rxPowerAgc;
 
-    _tx.txProfile = &_txProfile;
+    _tx.txProfile    = &_txProfile;
     _txProfile.txFir = tx_fir_config.fir;
-    _tx.deframer = &_deframer;
+    _tx.deframer     = &_deframer;
 
     // AD9373
-    _tx.dpdConfig = nullptr;
+    _tx.dpdConfig  = nullptr;
     _tx.clgcConfig = nullptr;
     _tx.vswrConfig = nullptr;
 
     // TODO: ideally we set none of this information and leave the profile as nullptr
     // Check that the API supports this
-    _obsRx.orxProfile = &_orxProfile;
-    _obsRx.orxGainCtrl = &_orxGainCtrl;
-    _obsRx.orxAgcCtrl = &_orxAgcCtrl;
-    _orxProfile.rxFir = _orx_fir_config.fir;
+    _obsRx.orxProfile            = &_orxProfile;
+    _obsRx.orxGainCtrl           = &_orxGainCtrl;
+    _obsRx.orxAgcCtrl            = &_orxAgcCtrl;
+    _orxProfile.rxFir            = _orx_fir_config.fir;
     _orxProfile.customAdcProfile = nullptr;
-    _orxAgcCtrl.peakAgc = &_orxPeakAgc;
-    _orxAgcCtrl.powerAgc = &_orxPowerAgc;
+    _orxAgcCtrl.peakAgc          = &_orxPeakAgc;
+    _orxAgcCtrl.powerAgc         = &_orxPowerAgc;
 
-    _obsRx.snifferProfile = &_snifferProfile;
-    _snifferProfile.rxFir = _sniffer_rx_fir_config.fir;
+    _obsRx.snifferProfile  = &_snifferProfile;
+    _snifferProfile.rxFir  = _sniffer_rx_fir_config.fir;
     _obsRx.snifferGainCtrl = &_snifferGainCtrl;
     // sniffer has no AGC ctrl, so leave as null
     _obsRx.framer = &_orxFramer;
 
     _auxIo.gpio3v3 = &_gpio3v3;
-    _auxIo.gpio = &_gpio;
+    _auxIo.gpio    = &_gpio;
     _auxIo.armGpio = &_armGpio;
 }
-
diff --git a/mpm/lib/mykonos/config/ad937x_config_t.hpp b/mpm/lib/mykonos/config/ad937x_config_t.hpp
index 7cbabb9b5..ab5ddb894 100644
--- a/mpm/lib/mykonos/config/ad937x_config_t.hpp
+++ b/mpm/lib/mykonos/config/ad937x_config_t.hpp
@@ -10,11 +10,11 @@
 #include "ad937x_fir.hpp"
 #include <boost/noncopyable.hpp>
 // Allocates and links the entire mykonos config struct in a single class
-class ad937x_config_t  : public boost::noncopyable
+class ad937x_config_t : public boost::noncopyable
 {
 public:
     ad937x_config_t(spiSettings_t* sps, const size_t deserializer_lane_xbar);
-    mykonosDevice_t * device;
+    mykonosDevice_t* device;
 
     ad937x_fir rx_fir_config;
     ad937x_fir tx_fir_config;
@@ -35,8 +35,9 @@ public:
     static const int16_t DEFAULT_SNIFFER_FIR_15366[DEFAULT_RX_FIR_SIZE];
 
 private:
-    // The top level device struct is non-const and contains all other structs, so everything is "public"
-    // a user could technically modify the pointers in the structs, but we have no way of preventing that
+    // The top level device struct is non-const and contains all other structs, so
+    // everything is "public" a user could technically modify the pointers in the structs,
+    // but we have no way of preventing that
     mykonosDevice_t _device;
 
     ad937x_fir _orx_fir_config;
diff --git a/mpm/lib/mykonos/config/ad937x_default_config.hpp b/mpm/lib/mykonos/config/ad937x_default_config.hpp
index e01c0c6d3..72fbd6cf5 100644
--- a/mpm/lib/mykonos/config/ad937x_default_config.hpp
+++ b/mpm/lib/mykonos/config/ad937x_default_config.hpp
@@ -9,368 +9,396 @@
 // This file is more or less the static config provided by a run of the eval software
 // except all pointers have been changed to nullptr
 // Hopefully this helps the compiler use these as purely constants
-// The pointers should be filled in if these data structures are to be actually used with the API
+// The pointers should be filled in if these data structures are to be actually used with
+// the API
 
-static const mykonosRxSettings_t DEFAULT_RX_SETTINGS =
-{
-    nullptr,        // Rx datapath profile, 3dB corner frequencies, and digital filter enables
-    nullptr,        // Rx JESD204b framer configuration structure
-    nullptr,        // Rx Gain control settings structure
-    nullptr,        // Rx AGC control settings structure
-    RX1_RX2,        // The desired Rx Channels to enable during initialization
-    0,              // Internal LO = 0, external LO*2 = 1
-    3500000000U,    // Rx PLL LO Frequency (internal or external LO)
-    0               // Flag to choose if complex baseband or real IF data are selected for Rx and ObsRx paths. Where, if > 0 = real IF data, '0' = zero IF (IQ) data
+static const mykonosRxSettings_t DEFAULT_RX_SETTINGS = {
+    nullptr, // Rx datapath profile, 3dB corner frequencies, and digital filter enables
+    nullptr, // Rx JESD204b framer configuration structure
+    nullptr, // Rx Gain control settings structure
+    nullptr, // Rx AGC control settings structure
+    RX1_RX2, // The desired Rx Channels to enable during initialization
+    0, // Internal LO = 0, external LO*2 = 1
+    3500000000U, // Rx PLL LO Frequency (internal or external LO)
+    0 // Flag to choose if complex baseband or real IF data are selected for Rx and ObsRx
+      // paths. Where, if > 0 = real IF data, '0' = zero IF (IQ) data
 };
 
-static const mykonosRxProfile_t DEFAULT_RX_PROFILE =
-{                   // Rx 100MHz, IQrate 125MSPS, Dec5
-    1,              // The divider used to generate the ADC clock
-    nullptr,        // Pointer to Rx FIR filter structure
-    2,              // Rx FIR decimation (1,2,4)
-    5,              // Decimation of Dec5 or Dec4 filter (5,4)
-    1,              // If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter (1=Enabled, 0=Disabled)
-    1,              // RX Half band 1 decimation (1 or 2)
-    125000,         // Rx IQ data rate in kHz
-    100000000,      // The Rx RF passband bandwidth for the profile
-    102000,         // Rx BBF 3dB corner in kHz
-    NULL            // pointer to custom ADC profile
+static const mykonosRxProfile_t DEFAULT_RX_PROFILE = {
+    // Rx 100MHz, IQrate 125MSPS, Dec5
+    1, // The divider used to generate the ADC clock
+    nullptr, // Pointer to Rx FIR filter structure
+    2, // Rx FIR decimation (1,2,4)
+    5, // Decimation of Dec5 or Dec4 filter (5,4)
+    1, // If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter
+    // (1=Enabled, 0=Disabled)
+    1, // RX Half band 1 decimation (1 or 2)
+    125000, // Rx IQ data rate in kHz
+    100000000, // The Rx RF passband bandwidth for the profile
+    102000, // Rx BBF 3dB corner in kHz
+    NULL // pointer to custom ADC profile
 };
 
-static const mykonosJesd204bFramerConfig_t DEFAULT_FRAMER =
-{
-    0,              // JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15)
-    0,              // JESD204B Configuration Device ID - link identification number. (Valid 0..255)
-    0,              // JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31)
-    4,              // number of ADCs (0, 2, or 4) - 2 ADCs per receive chain
-    20,             // number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes)
-    1,              // scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled.
-    1,              // 0=use internal SYSREF, 1= use external SYSREF
-    0x0F,           // serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled
-    0x4B,           // serializerLaneCrossbar
-    26,             // serializerAmplitude - default 22 (valid (0-31)
-    0,              // preEmphasis - < default 4 (valid 0 - 7)
-    0,              // invertLanePolarity - default 0 ([0] will invert lane [0], bit1 will invert lane1)
-    0,              // lmfcOffset - LMFC offset value for deterministic latency setting
-    0,              // Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, 0 = not set
-    0,              // Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set
-    0,              // Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 = use OBSRX_SYNCB for this framer
-    1,              // Flag for determining if CMOS mode for RX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS
-    0,              // Selects framer bit repeat or oversampling mode for lane rate matching. Where, 0 = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same lane rate between ObsRx framer and Rx framer and oversamples the ADC samples)
-    1               // Flag for determining if API will calculate the appropriate settings for framer lane outputs to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in serializerLaneCrossbar will be used
+static const mykonosJesd204bFramerConfig_t DEFAULT_FRAMER = {
+    0, // JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15)
+    0, // JESD204B Configuration Device ID - link identification number. (Valid 0..255)
+    0, // JESD204B Configuration starting Lane ID.  If more than one lane used, each lane
+       // will increment from the Lane0 ID. (Valid 0..31)
+    4, // number of ADCs (0, 2, or 4) - 2 ADCs per receive chain
+    20, // number of frames in a multiframe (default=32), F*K must be a multiple of 4.
+        // (F=2*M/numberOfLanes)
+    1, // scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled.
+    1, // 0=use internal SYSREF, 1= use external SYSREF
+    0x0F, // serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1
+          // enabled
+    0x4B, // serializerLaneCrossbar
+    26, // serializerAmplitude - default 22 (valid (0-31)
+    0, // preEmphasis - < default 4 (valid 0 - 7)
+    0, // invertLanePolarity - default 0 ([0] will invert lane [0], bit1 will invert
+       // lane1)
+    0, // lmfcOffset - LMFC offset value for deterministic latency setting
+    0, // Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, 0 =
+       // not set
+    0, // Flag for determining if auto channel select for the xbar should be set. Where,
+       // if > 0 = set, '0' = not set
+    0, // Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 = use
+       // OBSRX_SYNCB for this framer
+    1, // Flag for determining if CMOS mode for RX Sync signal is used. Where, if > 0 =
+       // CMOS, '0' = LVDS
+    0, // Selects framer bit repeat or oversampling mode for lane rate matching. Where, 0
+       // = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same
+       // lane rate between ObsRx framer and Rx framer and oversamples the ADC samples)
+    1 // Flag for determining if API will calculate the appropriate settings for framer
+      // lane outputs to physical lanes. Where, if '0' = API will set automatic lane
+      // crossbar, '1' = set to manual mode and the value in serializerLaneCrossbar will
+      // be used
 };
 
-static const mykonosRxGainControl_t DEFAULT_RX_GAIN =
-{
-    MGC,            // Current Rx gain control mode setting
-    255,            // Rx1 Gain Index, can be used in different ways for manual and AGC gain control
-    255,            // Rx2 Gain Index, can be used in different ways for manual and AGC gain control
-    255,            // Max gain index for the currently loaded Rx1 Gain table
-    195,            // Min gain index for the currently loaded Rx1 Gain table
-    255,            // Max gain index for the currently loaded Rx2 Gain table
-    195,            // Min gain index for the currently loaded Rx2 Gain table
-    0,              // Stores Rx1 RSSI value read back from the Mykonos
-    0               // Stores Rx2 RSSI value read back from the Mykonos
+static const mykonosRxGainControl_t DEFAULT_RX_GAIN = {
+    MGC, // Current Rx gain control mode setting
+    255, // Rx1 Gain Index, can be used in different ways for manual and AGC gain control
+    255, // Rx2 Gain Index, can be used in different ways for manual and AGC gain control
+    255, // Max gain index for the currently loaded Rx1 Gain table
+    195, // Min gain index for the currently loaded Rx1 Gain table
+    255, // Max gain index for the currently loaded Rx2 Gain table
+    195, // Min gain index for the currently loaded Rx2 Gain table
+    0, // Stores Rx1 RSSI value read back from the Mykonos
+    0 // Stores Rx2 RSSI value read back from the Mykonos
 };
 
-static const mykonosPeakDetAgcCfg_t DEFAULT_RX_PEAK_AGC =
-{
-    0x1F,   // apdHighThresh:
-    0x16,   // apdLowThresh
-    0xB5,   // hb2HighThresh
-    0x80,   // hb2LowThresh
-    0x40,   // hb2VeryLowThresh
-    0x06,   // apdHighThreshExceededCnt
-    0x04,   // apdLowThreshExceededCnt
-    0x06,   // hb2HighThreshExceededCnt
-    0x04,   // hb2LowThreshExceededCnt
-    0x04,   // hb2VeryLowThreshExceededCnt
-    0x4,    // apdHighGainStepAttack
-    0x2,    // apdLowGainStepRecovery
-    0x4,    // hb2HighGainStepAttack
-    0x2,    // hb2LowGainStepRecovery
-    0x4,    // hb2VeryLowGainStepRecovery
-    0x1,    // apdFastAttack
-    0x1,    // hb2FastAttack
-    0x1,    // hb2OverloadDetectEnable
-    0x1,    // hb2OverloadDurationCnt
-    0x1     // hb2OverloadThreshCnt
+static const mykonosPeakDetAgcCfg_t DEFAULT_RX_PEAK_AGC = {
+    0x1F, // apdHighThresh:
+    0x16, // apdLowThresh
+    0xB5, // hb2HighThresh
+    0x80, // hb2LowThresh
+    0x40, // hb2VeryLowThresh
+    0x06, // apdHighThreshExceededCnt
+    0x04, // apdLowThreshExceededCnt
+    0x06, // hb2HighThreshExceededCnt
+    0x04, // hb2LowThreshExceededCnt
+    0x04, // hb2VeryLowThreshExceededCnt
+    0x4, // apdHighGainStepAttack
+    0x2, // apdLowGainStepRecovery
+    0x4, // hb2HighGainStepAttack
+    0x2, // hb2LowGainStepRecovery
+    0x4, // hb2VeryLowGainStepRecovery
+    0x1, // apdFastAttack
+    0x1, // hb2FastAttack
+    0x1, // hb2OverloadDetectEnable
+    0x1, // hb2OverloadDurationCnt
+    0x1 // hb2OverloadThreshCnt
 };
 
-static const mykonosPowerMeasAgcCfg_t DEFAULT_RX_POWER_AGC =
-{
-    0x01,   // pmdUpperHighThresh
-    0x03,   // pmdUpperLowThresh
-    0x0C,   // pmdLowerHighThresh
-    0x04,   // pmdLowerLowThresh
-    0x4,    // pmdUpperHighGainStepAttack
-    0x2,    // pmdUpperLowGainStepAttack
-    0x2,    // pmdLowerHighGainStepRecovery
-    0x4,    // pmdLowerLowGainStepRecovery
-    0x08,   // pmdMeasDuration
-    0x02    // pmdMeasConfig
+static const mykonosPowerMeasAgcCfg_t DEFAULT_RX_POWER_AGC = {
+    0x01, // pmdUpperHighThresh
+    0x03, // pmdUpperLowThresh
+    0x0C, // pmdLowerHighThresh
+    0x04, // pmdLowerLowThresh
+    0x4, // pmdUpperHighGainStepAttack
+    0x2, // pmdUpperLowGainStepAttack
+    0x2, // pmdLowerHighGainStepRecovery
+    0x4, // pmdLowerLowGainStepRecovery
+    0x08, // pmdMeasDuration
+    0x02 // pmdMeasConfig
 };
 
-static const mykonosAgcCfg_t DEFAULT_RX_AGC_CTRL =
-{
-    255,    // AGC peak wait time
-    195,    // agcRx1MinGainIndex
-    255,    // agcRx2MaxGainIndex
-    195,    // agcRx2MinGainIndex:
-    255,    // agcObsRxMaxGainIndex
-    203,    // agcObsRxMinGainIndex
-    1,      // agcObsRxSelect
-    1,      // agcPeakThresholdMode
-    1,      // agcLowThsPreventGainIncrease
-    30720,  // agcGainUpdateCounter
-    3,      // agcSlowLoopSettlingDelay
-    2,      // agcPeakWaitTime
-    0,      // agcResetOnRxEnable
-    0,      // agcEnableSyncPulseForGainCounter
-    nullptr,// *peakAgc
+static const mykonosAgcCfg_t DEFAULT_RX_AGC_CTRL = {
+    255, // AGC peak wait time
+    195, // agcRx1MinGainIndex
+    255, // agcRx2MaxGainIndex
+    195, // agcRx2MinGainIndex:
+    255, // agcObsRxMaxGainIndex
+    203, // agcObsRxMinGainIndex
+    1, // agcObsRxSelect
+    1, // agcPeakThresholdMode
+    1, // agcLowThsPreventGainIncrease
+    30720, // agcGainUpdateCounter
+    3, // agcSlowLoopSettlingDelay
+    2, // agcPeakWaitTime
+    0, // agcResetOnRxEnable
+    0, // agcEnableSyncPulseForGainCounter
+    nullptr, // *peakAgc
     nullptr // *powerAgc
 };
 
-static const mykonosTxSettings_t DEFAULT_TX_SETTINGS =
-{
-    nullptr,        // Tx datapath profile, 3dB corner frequencies, and digital filter enables
-    nullptr,        // Mykonos JESD204b deframer config for the Tx data path
-    TX1_TX2,        // The desired Tx channels to enable during initialization
-    0,              // Internal LO=0, external LO*2 if =1
-    3500000000U,    // Tx PLL LO frequency (internal or external LO)
-    TXATTEN_0P05_DB,// Initial and current Tx1 Attenuation
-    10000,          // Initial and current Tx1 Attenuation mdB
-    10000,          // Initial and current Tx2 Attenuation mdB
-    nullptr,        // DPD,CLGC,VSWR settings. Only valid for AD9373 device, set pointer to NULL otherwise
-    nullptr,        // CLGC Config Structure. Only valid for AD9373 device, set pointer to NULL otherwise
-    nullptr         // VSWR Config Structure. Only valid for AD9373 device, set pointer to NULL otherwise
+static const mykonosTxSettings_t DEFAULT_TX_SETTINGS = {
+    nullptr, // Tx datapath profile, 3dB corner frequencies, and digital filter enables
+    nullptr, // Mykonos JESD204b deframer config for the Tx data path
+    TX1_TX2, // The desired Tx channels to enable during initialization
+    0, // Internal LO=0, external LO*2 if =1
+    3500000000U, // Tx PLL LO frequency (internal or external LO)
+    TXATTEN_0P05_DB, // Initial and current Tx1 Attenuation
+    10000, // Initial and current Tx1 Attenuation mdB
+    10000, // Initial and current Tx2 Attenuation mdB
+    nullptr, // DPD,CLGC,VSWR settings. Only valid for AD9373 device, set pointer to NULL
+             // otherwise
+    nullptr, // CLGC Config Structure. Only valid for AD9373 device, set pointer to NULL
+             // otherwise
+    nullptr // VSWR Config Structure. Only valid for AD9373 device, set pointer to NULL
+            // otherwise
 };
 
-static const mykonosTxProfile_t DEFAULT_TX_PROFILE =
-{                   // Tx 20/100MHz, IQrate 122.88MHz, Dec5
-    DACDIV_2p5,     // The divider used to generate the DAC clock
-    nullptr,        // Pointer to Tx FIR filter structure
-    2,              // The Tx digital FIR filter interpolation (1,2,4)
-    2,              // Tx Halfband1 filter interpolation (1,2)
-    1,              // Tx Halfband2 filter interpolation (1,2)
-    1,              // TxInputHbInterpolation (1,2)
-    125000,         // Tx IQ data rate in kHz
-    20000000,       // Primary Signal BW
-    102000000,      // The Tx RF passband bandwidth for the profile
-    722000,         // The DAC filter 3dB corner in kHz
-    51000,          // Tx BBF 3dB corner in kHz
-    0               // Enable DPD, only valid for AD9373
+static const mykonosTxProfile_t DEFAULT_TX_PROFILE = {
+    // Tx 20/100MHz, IQrate 122.88MHz, Dec5
+    DACDIV_2p5, // The divider used to generate the DAC clock
+    nullptr, // Pointer to Tx FIR filter structure
+    2, // The Tx digital FIR filter interpolation (1,2,4)
+    2, // Tx Halfband1 filter interpolation (1,2)
+    1, // Tx Halfband2 filter interpolation (1,2)
+    1, // TxInputHbInterpolation (1,2)
+    125000, // Tx IQ data rate in kHz
+    20000000, // Primary Signal BW
+    102000000, // The Tx RF passband bandwidth for the profile
+    722000, // The DAC filter 3dB corner in kHz
+    51000, // Tx BBF 3dB corner in kHz
+    0 // Enable DPD, only valid for AD9373
 };
 
-static const mykonosJesd204bDeframerConfig_t DEFAULT_DEFRAMER =
-{
-    0,              // bankId extension to Device ID (Valid 0..15)
-    0,              // deviceId  link identification number. (Valid 0..255)
-    0,              // lane0Id Lane0 ID. (Valid 0..31)
-    4,              // M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain
-    20,             // K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes)
-    0,              // Scrambling off if scramble = 0, if framerScramble > 0 scrambling is enabled
-    1,              // External SYSREF select. 0 = use internal SYSREF, 1 = external SYSREF
-    0x0F,           // Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc
-    0xD2,           // Lane crossbar to map physical lanes to deframer lane inputs [1:0] = Deframer Input 0 Lane section, [3:2] = Deframer Input 1 lane select, etc
-    1,              // Equalizer setting. Applied to all deserializer lanes. Range is 0..4
-    0,              // PN inversion per each lane.  bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc).
-    0,              // LMFC offset value to adjust deterministic latency. Range is 0..31
-    0,              // Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, '0' = not set
-    0,              // Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set
-    1,              // Flag for determining if CMOS mode for TX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS
-    1,              // Flag for determining if API will calculate the appropriate settings for deframer lane in to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in deserializerLaneCrossbar will be used
+static const mykonosJesd204bDeframerConfig_t DEFAULT_DEFRAMER = {
+    0, // bankId extension to Device ID (Valid 0..15)
+    0, // deviceId  link identification number. (Valid 0..255)
+    0, // lane0Id Lane0 ID. (Valid 0..31)
+    4, // M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain
+    20, // K  #frames in a multiframe (default=32), F*K=multiple of 4.
+        // (F=2*M/numberOfLanes)
+    0, // Scrambling off if scramble = 0, if framerScramble > 0 scrambling is enabled
+    1, // External SYSREF select. 0 = use internal SYSREF, 1 = external SYSREF
+    0x0F, // Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1
+          // enabled, etc
+    0xD2, // Lane crossbar to map physical lanes to deframer lane inputs [1:0] = Deframer
+          // Input 0 Lane section, [3:2] = Deframer Input 1 lane select, etc
+    1, // Equalizer setting. Applied to all deserializer lanes. Range is 0..4
+    0, // PN inversion per each lane.  bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN
+       // of Lane 1, etc).
+    0, // LMFC offset value to adjust deterministic latency. Range is 0..31
+    0, // Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, '0'
+       // = not set
+    0, // Flag for determining if auto channel select for the xbar should be set. Where,
+       // if > 0 = set, '0' = not set
+    1, // Flag for determining if CMOS mode for TX Sync signal is used. Where, if > 0 =
+       // CMOS, '0' = LVDS
+    1, // Flag for determining if API will calculate the appropriate settings for deframer
+       // lane in to physical lanes. Where, if '0' = API will set automatic lane crossbar,
+       // '1' = set to manual mode and the value in deserializerLaneCrossbar will be used
 };
 
-static const mykonosObsRxSettings_t DEFAULT_ORX_SETTINGS =
-{
-    nullptr,        // ORx datapath profile, 3dB corner frequencies, and digital filter enables
-    nullptr,        // ObsRx gain control settings structure
-    nullptr,        // ORx AGC control settings structure
-    nullptr,        // Sniffer datapath profile, 3dB corner frequencies, and digital filter enables
-    nullptr,        // SnRx gain control settings structure
-    nullptr,        // ObsRx JESD204b framer configuration structure
-    MYK_ORX1,       // obsRxChannel  TODO: fix this garbage please
-    OBSLO_TX_PLL,   // (obsRxLoSource) The Obs Rx mixer can use the Tx Synth(TX_PLL) or Sniffer Synth (SNIFFER_PLL)
-    2600000000U,    // SnRx PLL LO frequency in Hz
-    0,              // Flag to choose if complex baseband or real IF data are selected for Rx and ObsRx paths. Where if > 0 = real IF data, '0' = complex data
-    nullptr,        // Custom Loopback ADC profile to set the bandwidth of the ADC response
-    OBS_RXOFF       // Default ObsRx channel to enter when radioOn called
+static const mykonosObsRxSettings_t DEFAULT_ORX_SETTINGS = {
+    nullptr, // ORx datapath profile, 3dB corner frequencies, and digital filter enables
+    nullptr, // ObsRx gain control settings structure
+    nullptr, // ORx AGC control settings structure
+    nullptr, // Sniffer datapath profile, 3dB corner frequencies, and digital filter
+             // enables
+    nullptr, // SnRx gain control settings structure
+    nullptr, // ObsRx JESD204b framer configuration structure
+    MYK_ORX1, // obsRxChannel  TODO: fix this garbage please
+    OBSLO_TX_PLL, // (obsRxLoSource) The Obs Rx mixer can use the Tx Synth(TX_PLL) or
+                  // Sniffer Synth (SNIFFER_PLL)
+    2600000000U, // SnRx PLL LO frequency in Hz
+    0, // Flag to choose if complex baseband or real IF data are selected for Rx and ObsRx
+       // paths. Where if > 0 = real IF data, '0' = complex data
+    nullptr, // Custom Loopback ADC profile to set the bandwidth of the ADC response
+    OBS_RXOFF // Default ObsRx channel to enter when radioOn called
 };
 
-static const mykonosJesd204bFramerConfig_t DEFAULT_ORX_FRAMER =
-{
-    0,              // JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15)
-    0,              // JESD204B Configuration Device ID - link identification number. (Valid 0..255)
-    0,              // JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31)
-    2,              // number of ADCs (0, 2, or 4) - 2 ADCs per receive chain
-    32,             // number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes)
-    1,              // scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled.
-    1,              // 0=use internal SYSREF, 1= use external SYSREF
-    0x00,           // serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled
-    0xE4,           // Lane crossbar to map framer lane outputs to physical lanes
-    22,             // serializerAmplitude - default 22 (valid (0-31)
-    4,              // preEmphasis - < default 4 (valid 0 - 7)
-    0,              // invertLanePolarity - default 0 ([0] will invert lane [0], bit1 will invert lane1)
-    0,              // lmfcOffset - LMFC_Offset offset value for deterministic latency setting
-    0,              // Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, 0 = not set
-    0,              // Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set
-    1,              // Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 = use OBSRX_SYNCB for this framer
-    0,              // Flag for determining if CMOS mode for RX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS
-    1,              // Selects framer bit repeat or oversampling mode for lane rate matching. Where, 0 = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same lane rate between ObsRx framer and Rx framer and oversamples the ADC samples)
-    1               // Flag for determining if API will calculate the appropriate settings for framer lane outputs to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in serializerLaneCrossbar will be used
+static const mykonosJesd204bFramerConfig_t DEFAULT_ORX_FRAMER = {
+    0, // JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15)
+    0, // JESD204B Configuration Device ID - link identification number. (Valid 0..255)
+    0, // JESD204B Configuration starting Lane ID.  If more than one lane used, each lane
+       // will increment from the Lane0 ID. (Valid 0..31)
+    2, // number of ADCs (0, 2, or 4) - 2 ADCs per receive chain
+    32, // number of frames in a multiframe (default=32), F*K must be a multiple of 4.
+        // (F=2*M/numberOfLanes)
+    1, // scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled.
+    1, // 0=use internal SYSREF, 1= use external SYSREF
+    0x00, // serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1
+          // enabled
+    0xE4, // Lane crossbar to map framer lane outputs to physical lanes
+    22, // serializerAmplitude - default 22 (valid (0-31)
+    4, // preEmphasis - < default 4 (valid 0 - 7)
+    0, // invertLanePolarity - default 0 ([0] will invert lane [0], bit1 will invert
+       // lane1)
+    0, // lmfcOffset - LMFC_Offset offset value for deterministic latency setting
+    0, // Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, 0 =
+       // not set
+    0, // Flag for determining if auto channel select for the xbar should be set. Where,
+       // if > 0 = set, '0' = not set
+    1, // Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 = use
+       // OBSRX_SYNCB for this framer
+    0, // Flag for determining if CMOS mode for RX Sync signal is used. Where, if > 0 =
+       // CMOS, '0' = LVDS
+    1, // Selects framer bit repeat or oversampling mode for lane rate matching. Where, 0
+       // = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same
+       // lane rate between ObsRx framer and Rx framer and oversamples the ADC samples)
+    1 // Flag for determining if API will calculate the appropriate settings for framer
+      // lane outputs to physical lanes. Where, if '0' = API will set automatic lane
+      // crossbar, '1' = set to manual mode and the value in serializerLaneCrossbar will
+      // be used
 };
 
-static const mykonosORxGainControl_t DEFAULT_ORX_GAIN =
-{
-    MGC,            // Current ORx gain control mode setting
-    255,            // ORx1 Gain Index, can be used in different ways for manual and AGC gain control
-    255,            // ORx2 Gain Index, can be used in different ways for manual and AGC gain control
-    255,            // Max gain index for the currently loaded ORx Gain table
-    237             // Min gain index for the currently loaded ORx Gain table
+static const mykonosORxGainControl_t DEFAULT_ORX_GAIN = {
+    MGC, // Current ORx gain control mode setting
+    255, // ORx1 Gain Index, can be used in different ways for manual and AGC gain control
+    255, // ORx2 Gain Index, can be used in different ways for manual and AGC gain control
+    255, // Max gain index for the currently loaded ORx Gain table
+    237 // Min gain index for the currently loaded ORx Gain table
 };
 
-static const mykonosAgcCfg_t DEFAULT_ORX_AGC_CTRL =
-{
-    255,    // agcRx1MaxGainIndex
-    195,    // agcRx1MinGainIndex
-    255,    // agcRx2MaxGainIndex
-    195,    // agcRx2MinGainIndex:
-    255,    // agcObsRxMaxGainIndex
-    203,    // agcObsRxMinGainIndex
-    1,      // agcObsRxSelect
-    1,      // agcPeakThresholdMode
-    1,      // agcLowThsPreventGainIncrease
-    30720,  // agcGainUpdateCounter
-    3,      // agcSlowLoopSettlingDelay
-    4,      // agcPeakWaitTime
-    0,      // agcResetOnRxEnable
-    0,      // agcEnableSyncPulseForGainCounter
-    nullptr,// *peakAgc
+static const mykonosAgcCfg_t DEFAULT_ORX_AGC_CTRL = {
+    255, // agcRx1MaxGainIndex
+    195, // agcRx1MinGainIndex
+    255, // agcRx2MaxGainIndex
+    195, // agcRx2MinGainIndex:
+    255, // agcObsRxMaxGainIndex
+    203, // agcObsRxMinGainIndex
+    1, // agcObsRxSelect
+    1, // agcPeakThresholdMode
+    1, // agcLowThsPreventGainIncrease
+    30720, // agcGainUpdateCounter
+    3, // agcSlowLoopSettlingDelay
+    4, // agcPeakWaitTime
+    0, // agcResetOnRxEnable
+    0, // agcEnableSyncPulseForGainCounter
+    nullptr, // *peakAgc
     nullptr // *powerAgc
 };
 
-static const mykonosPeakDetAgcCfg_t DEFAULT_ORX_PEAK_AGC =
-{
-    0x2A,   // apdHighThresh:
-    0x16,   // apdLowThresh
-    0xB5,   // hb2HighThresh
-    0x72,   // hb2LowThresh
-    0x40,   // hb2VeryLowThresh
-    0x03,   // apdHighThreshExceededCnt
-    0x03,   // apdLowThreshExceededCnt
-    0x03,   // hb2HighThreshExceededCnt
-    0x03,   // hb2LowThreshExceededCnt
-    0x03,   // hb2VeryLowThreshExceededCnt
-    0x4,    // apdHighGainStepAttack
-    0x2,    // apdLowGainStepRecovery
-    0x4,    // hb2HighGainStepAttack
-    0x2,    // hb2LowGainStepRecovery
-    0x4,    // hb2VeryLowGainStepRecovery
-    0x0,    // apdFastAttack
-    0x0,    // hb2FastAttack
-    0x1,    // hb2OverloadDetectEnable
-    0x1,    // hb2OverloadDurationCnt
-    0x1     // hb2OverloadThreshCnt
+static const mykonosPeakDetAgcCfg_t DEFAULT_ORX_PEAK_AGC = {
+    0x2A, // apdHighThresh:
+    0x16, // apdLowThresh
+    0xB5, // hb2HighThresh
+    0x72, // hb2LowThresh
+    0x40, // hb2VeryLowThresh
+    0x03, // apdHighThreshExceededCnt
+    0x03, // apdLowThreshExceededCnt
+    0x03, // hb2HighThreshExceededCnt
+    0x03, // hb2LowThreshExceededCnt
+    0x03, // hb2VeryLowThreshExceededCnt
+    0x4, // apdHighGainStepAttack
+    0x2, // apdLowGainStepRecovery
+    0x4, // hb2HighGainStepAttack
+    0x2, // hb2LowGainStepRecovery
+    0x4, // hb2VeryLowGainStepRecovery
+    0x0, // apdFastAttack
+    0x0, // hb2FastAttack
+    0x1, // hb2OverloadDetectEnable
+    0x1, // hb2OverloadDurationCnt
+    0x1 // hb2OverloadThreshCnt
 };
 
-static const mykonosPowerMeasAgcCfg_t DEFAULT_ORX_POWER_AGC =
-{
-    0x01,   // pmdUpperHighThresh
-    0x03,   // pmdUpperLowThresh
-    0x0C,   // pmdLowerHighThresh
-    0x04,   // pmdLowerLowThresh
-    0x0,    // pmdUpperHighGainStepAttack
-    0x0,    // pmdUpperLowGainStepAttack
-    0x0,    // pmdLowerHighGainStepRecovery
-    0x0,    // pmdLowerLowGainStepRecovery
-    0x08,   // pmdMeasDuration
-    0x02    // pmdMeasConfig
+static const mykonosPowerMeasAgcCfg_t DEFAULT_ORX_POWER_AGC = {
+    0x01, // pmdUpperHighThresh
+    0x03, // pmdUpperLowThresh
+    0x0C, // pmdLowerHighThresh
+    0x04, // pmdLowerLowThresh
+    0x0, // pmdUpperHighGainStepAttack
+    0x0, // pmdUpperLowGainStepAttack
+    0x0, // pmdLowerHighGainStepRecovery
+    0x0, // pmdLowerLowGainStepRecovery
+    0x08, // pmdMeasDuration
+    0x02 // pmdMeasConfig
 };
 
-static const mykonosSnifferGainControl_t DEFAULT_SNIFFER_GAIN =
-{
-    MGC,    // Current Sniffer gain control mode setting
-    255,    // Current Sniffer gain index. Can be used differently for Manual Gain control/AGC
-    255,    // Max gain index for the currently loaded Sniffer Gain table
-    203     // Min gain index for the currently loaded Sniffer Gain table
+static const mykonosSnifferGainControl_t DEFAULT_SNIFFER_GAIN = {
+    MGC, // Current Sniffer gain control mode setting
+    255, // Current Sniffer gain index. Can be used differently for Manual Gain
+         // control/AGC
+    255, // Max gain index for the currently loaded Sniffer Gain table
+    203 // Min gain index for the currently loaded Sniffer Gain table
 };
 
-static const mykonosRxProfile_t DEFAULT_ORX_PROFILE =
-{// ORX 100MHz, IQrate 125MSPS, Dec5
-    1,              // The divider used to generate the ADC clock
-    nullptr,        // Pointer to Rx FIR filter structure or NULL
-    2,              // Rx FIR decimation (1,2,4)
-    5,              // Decimation of Dec5 or Dec4 filter (5,4)
-    0,              // If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter (1=Enabled, 0=Disabled)
-    1,              // RX Half band 1 decimation (1 or 2)
-    125000,         // Rx IQ data rate in kHz
-    100000000,      // The Rx RF passband bandwidth for the profile
-    102000,         // Rx BBF 3dB corner in kHz
-    nullptr         // pointer to custom ADC profile
+static const mykonosRxProfile_t DEFAULT_ORX_PROFILE = {
+    // ORX 100MHz, IQrate 125MSPS, Dec5
+    1, // The divider used to generate the ADC clock
+    nullptr, // Pointer to Rx FIR filter structure or NULL
+    2, // Rx FIR decimation (1,2,4)
+    5, // Decimation of Dec5 or Dec4 filter (5,4)
+    0, // If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter
+    // (1=Enabled, 0=Disabled)
+    1, // RX Half band 1 decimation (1 or 2)
+    125000, // Rx IQ data rate in kHz
+    100000000, // The Rx RF passband bandwidth for the profile
+    102000, // Rx BBF 3dB corner in kHz
+    nullptr // pointer to custom ADC profile
 };
 
-static const mykonosArmGpioConfig_t DEFAULT_ARM_GPIO =
-{
-    1,  // useRx2EnablePin; //!< 0= RX1_ENABLE controls RX1 and RX2, 1 = separate RX1_ENABLE/RX2_ENABLE pins
-    1,  // useTx2EnablePin; //!< 0= TX1_ENABLE controls TX1 and TX2, 1 = separate TX1_ENABLE/TX2_ENABLE pins
-    0,  // txRxPinMode;     //!< 0= ARM command mode, 1 = Pin mode to power up Tx/Rx chains
-    0,  // orxPinMode;      //!< 0= ARM command mode, 1 = Pin mode to power up ObsRx receiver
+static const mykonosArmGpioConfig_t DEFAULT_ARM_GPIO = {
+    1, // useRx2EnablePin; //!< 0= RX1_ENABLE controls RX1 and RX2, 1 = separate
+       // RX1_ENABLE/RX2_ENABLE pins
+    1, // useTx2EnablePin; //!< 0= TX1_ENABLE controls TX1 and TX2, 1 = separate
+       // TX1_ENABLE/TX2_ENABLE pins
+    0, // txRxPinMode;     //!< 0= ARM command mode, 1 = Pin mode to power up Tx/Rx chains
+    0, // orxPinMode;      //!< 0= ARM command mode, 1 = Pin mode to power up ObsRx
+       // receiver
 
-    //Mykonos ARM input GPIO pins -- Only valid if orxPinMode = 1
-    0,  // orxTriggerPin; //!< Select desired GPIO pin (valid 4-15)
-    0,  // orxMode2Pin;   //!< Select desired GPIO pin (valid 0-18)
-    0,  // orxMode1Pin;   //!< Select desired GPIO pin (valid 0-18)
-    0,  // orxMode0Pin;   //!< Select desired GPIO pin (valid 0-18)
+    // Mykonos ARM input GPIO pins -- Only valid if orxPinMode = 1
+    0, // orxTriggerPin; //!< Select desired GPIO pin (valid 4-15)
+    0, // orxMode2Pin;   //!< Select desired GPIO pin (valid 0-18)
+    0, // orxMode1Pin;   //!< Select desired GPIO pin (valid 0-18)
+    0, // orxMode0Pin;   //!< Select desired GPIO pin (valid 0-18)
 
     // Mykonos ARM output GPIO pins  --  always available, even when pin mode not enabled
-    0,  // rx1EnableAck;  //!< Select desired GPIO pin (0-15), [4] = Output Enable
-    0,  // rx2EnableAck;  //!< Select desired GPIO pin (0-15), [4] = Output Enable
-    0,  // tx1EnableAck;  //!< Select desired GPIO pin (0-15), [4] = Output Enable
-    0,  // tx2EnableAck;  //!< Select desired GPIO pin (0-15), [4] = Output Enable
-    0,  // orx1EnableAck;  //!< Select desired GPIO pin (0-15), [4] = Output Enable
-    0,  // orx2EnableAck;  //!< Select desired GPIO pin (0-15), [4] = Output Enable
-    0,  // srxEnableAck;  //!< Select desired GPIO pin (0-15), [4] = Output Enable
-    0   // txObsSelect;   //!< Select desired GPIO pin (0-15), [4] = Output Enable
-        // When 2Tx are used with only 1 ORx input, this GPIO tells the BBIC which Tx channel is
-        // active for calibrations, so BBIC can route correct RF Tx path into the single ORx input
+    0, // rx1EnableAck;  //!< Select desired GPIO pin (0-15), [4] = Output Enable
+    0, // rx2EnableAck;  //!< Select desired GPIO pin (0-15), [4] = Output Enable
+    0, // tx1EnableAck;  //!< Select desired GPIO pin (0-15), [4] = Output Enable
+    0, // tx2EnableAck;  //!< Select desired GPIO pin (0-15), [4] = Output Enable
+    0, // orx1EnableAck;  //!< Select desired GPIO pin (0-15), [4] = Output Enable
+    0, // orx2EnableAck;  //!< Select desired GPIO pin (0-15), [4] = Output Enable
+    0, // srxEnableAck;  //!< Select desired GPIO pin (0-15), [4] = Output Enable
+    0 // txObsSelect;   //!< Select desired GPIO pin (0-15), [4] = Output Enable
+      // When 2Tx are used with only 1 ORx input, this GPIO tells the BBIC which Tx
+      // channel is active for calibrations, so BBIC can route correct RF Tx path into the
+      // single ORx input
 };
 
-static const mykonosGpio3v3_t DEFAULT_GPIO_3V3 =
-{
-    0,                      //!< Oe per pin, 1=output, 0 = input
-    GPIO3V3_BITBANG_MODE,   //!< Mode for GPIO3V3[3:0]
-    GPIO3V3_BITBANG_MODE,   //!< Mode for GPIO3V3[7:4]
-    GPIO3V3_BITBANG_MODE,   //!< Mode for GPIO3V3[11:8]
+static const mykonosGpio3v3_t DEFAULT_GPIO_3V3 = {
+    0, //!< Oe per pin, 1=output, 0 = input
+    GPIO3V3_BITBANG_MODE, //!< Mode for GPIO3V3[3:0]
+    GPIO3V3_BITBANG_MODE, //!< Mode for GPIO3V3[7:4]
+    GPIO3V3_BITBANG_MODE, //!< Mode for GPIO3V3[11:8]
 };
 
-static const mykonosGpioLowVoltage_t DEFAULT_GPIO =
-{
-    0,                      // Oe per pin, 1=output, 0 = input
-    GPIO_MONITOR_MODE,      // Mode for GPIO[3:0]
-    GPIO_MONITOR_MODE,      // Mode for GPIO[7:4]
-    GPIO_MONITOR_MODE,      // Mode for GPIO[11:8]
-    GPIO_MONITOR_MODE,      // Mode for GPIO[15:12]
-    GPIO_MONITOR_MODE,      // Mode for GPIO[18:16]
+static const mykonosGpioLowVoltage_t DEFAULT_GPIO = {
+    0, // Oe per pin, 1=output, 0 = input
+    GPIO_MONITOR_MODE, // Mode for GPIO[3:0]
+    GPIO_MONITOR_MODE, // Mode for GPIO[7:4]
+    GPIO_MONITOR_MODE, // Mode for GPIO[11:8]
+    GPIO_MONITOR_MODE, // Mode for GPIO[15:12]
+    GPIO_MONITOR_MODE, // Mode for GPIO[18:16]
 };
 
-static const mykonosAuxIo_t DEFAULT_AUX_IO =
-{
-    0,                          // auxDacEnable uint16_t
-    { 0,0,0,0,0,0,0,0,0,0 },    // auxDacValue uint16[10]
-    { 0,0,0,0,0,0,0,0,0,0 },    // auxDacSlope uint8[10]
-    { 0,0,0,0,0,0,0,0,0,0 },    // auxDacVref uint8[10]
-    nullptr,                    // *mykonosGpio3v3_t
-    nullptr,                    // *mykonosGpioLowVoltage_t
-    nullptr                     // *mykonosArmGpioConfig_t
+static const mykonosAuxIo_t DEFAULT_AUX_IO = {
+    0, // auxDacEnable uint16_t
+    {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // auxDacValue uint16[10]
+    {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // auxDacSlope uint8[10]
+    {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // auxDacVref uint8[10]
+    nullptr, // *mykonosGpio3v3_t
+    nullptr, // *mykonosGpioLowVoltage_t
+    nullptr // *mykonosArmGpioConfig_t
 };
 
-static const mykonosDigClocks_t DEFAULT_CLOCKS =
-{
-    125000,         // CLKPLL and device reference clock frequency in kHz
-    10000000,       // CLKPLL VCO frequency in kHz
-    VCODIV_2,       // CLKPLL VCO divider
-    4               // CLKPLL high speed clock divider
+static const mykonosDigClocks_t DEFAULT_CLOCKS = {
+    125000, // CLKPLL and device reference clock frequency in kHz
+    10000000, // CLKPLL VCO frequency in kHz
+    VCODIV_2, // CLKPLL VCO divider
+    4 // CLKPLL high speed clock divider
 };
-
-
diff --git a/mpm/lib/mykonos/config/ad937x_fir.cpp b/mpm/lib/mykonos/config/ad937x_fir.cpp
index 01c8772eb..6803f5369 100644
--- a/mpm/lib/mykonos/config/ad937x_fir.cpp
+++ b/mpm/lib/mykonos/config/ad937x_fir.cpp
@@ -6,21 +6,16 @@
 
 #include "ad937x_fir.hpp"
 
-ad937x_fir::ad937x_fir() :
-    ad937x_fir(0, { 1, 0 })
+ad937x_fir::ad937x_fir() : ad937x_fir(0, {1, 0}) {}
+
+ad937x_fir::ad937x_fir(int8_t gain, const std::vector<int16_t>& coefficients)
+    : // These two constructors will be run in the order they are declared in the class
+      // definition see C++ standard 12.6.2 section 13.3
+    _fir_coefficients(coefficients)
+    , _fir({gain,
+          static_cast<uint8_t>(_fir_coefficients.size()),
+          _fir_coefficients.data()})
 {
-
-}
-
-ad937x_fir::ad937x_fir(int8_t gain, const std::vector<int16_t>& coefficients) :
-    // These two constructors will be run in the order they are declared in the class definition
-    // see C++ standard 12.6.2 section 13.3
-    _fir_coefficients(coefficients),
-    _fir({gain,
-        static_cast<uint8_t>(_fir_coefficients.size()),
-        _fir_coefficients.data()})
-{
-
 }
 
 // ad937x_fir.fir should not be accessed during this operation
@@ -29,11 +24,11 @@ void ad937x_fir::set_fir(int8_t gain, const std::vector<int16_t>& coefficients)
     _fir.gain_dB = gain;
 
     _fir_coefficients = coefficients;
-    _fir.coefs = _fir_coefficients.data();
-    _fir.numFirCoefs = static_cast<uint8_t>(_fir_coefficients.size());
+    _fir.coefs        = _fir_coefficients.data();
+    _fir.numFirCoefs  = static_cast<uint8_t>(_fir_coefficients.size());
 }
 
-std::vector<int16_t> ad937x_fir::get_fir(int8_t &gain) const
+std::vector<int16_t> ad937x_fir::get_fir(int8_t& gain) const
 {
     gain = _fir.gain_dB;
     return _fir_coefficients;
diff --git a/mpm/lib/mykonos/config/ad937x_fir.hpp b/mpm/lib/mykonos/config/ad937x_fir.hpp
index c3fda6fb7..df122701d 100644
--- a/mpm/lib/mykonos/config/ad937x_fir.hpp
+++ b/mpm/lib/mykonos/config/ad937x_fir.hpp
@@ -15,11 +15,12 @@ class ad937x_fir
 {
     std::vector<int16_t> _fir_coefficients;
     mykonosFir_t _fir;
+
 public:
     mykonosFir_t* const fir = &_fir;
     ad937x_fir();
     ad937x_fir(int8_t gain, const std::vector<int16_t>& coefficients);
 
     void set_fir(int8_t gain, const std::vector<int16_t>& coefficients);
-    std::vector<int16_t> get_fir(int8_t &gain) const;
+    std::vector<int16_t> get_fir(int8_t& gain) const;
 };
diff --git a/mpm/lib/mykonos/config/ad937x_gain_ctrl_config.cpp b/mpm/lib/mykonos/config/ad937x_gain_ctrl_config.cpp
index d4fbef0ad..bc8dcb21a 100644
--- a/mpm/lib/mykonos/config/ad937x_gain_ctrl_config.cpp
+++ b/mpm/lib/mykonos/config/ad937x_gain_ctrl_config.cpp
@@ -11,121 +11,158 @@ using namespace mpm::ad937x::device;
 using namespace uhd;
 
 const uint8_t ad937x_gain_ctrl_channel_t::DEFAULT_GAIN_STEP = 1;
-const bool ad937x_gain_ctrl_channel_t::DEFAULT_ENABLE = 0;
+const bool ad937x_gain_ctrl_channel_t::DEFAULT_ENABLE       = 0;
 
 // rx uses gain, tx uses attenuation
-enum class pin_direction_t
-{
+enum class pin_direction_t {
     INCREASE,
     DECREASE,
 };
 
 mykonosGpioSelect_t _convert_gain_pin(gain_pin_t pin)
 {
-    switch (pin)
-    {
-    case gain_pin_t::PIN0:  return MYKGPIO0;
-    case gain_pin_t::PIN1:  return MYKGPIO1;
-    case gain_pin_t::PIN2:  return MYKGPIO2;
-    case gain_pin_t::PIN3:  return MYKGPIO3;
-    case gain_pin_t::PIN4:  return MYKGPIO4;
-    case gain_pin_t::PIN5:  return MYKGPIO5;
-    case gain_pin_t::PIN6:  return MYKGPIO6;
-    case gain_pin_t::PIN7:  return MYKGPIO7;
-    case gain_pin_t::PIN8:  return MYKGPIO8;
-    case gain_pin_t::PIN9:  return MYKGPIO9;
-    case gain_pin_t::PIN10: return MYKGPIO10;
-    case gain_pin_t::PIN11: return MYKGPIO11;
-    case gain_pin_t::PIN12: return MYKGPIO12;
-    case gain_pin_t::PIN13: return MYKGPIO13;
-    case gain_pin_t::PIN14: return MYKGPIO14;
-    case gain_pin_t::PIN15: return MYKGPIO15;
-    case gain_pin_t::PIN16: return MYKGPIO16;
-    case gain_pin_t::PIN17: return MYKGPIO17;
-    case gain_pin_t::PIN18: return MYKGPIO18;
-    default: return MYKGPIONAN;
+    switch (pin) {
+        case gain_pin_t::PIN0:
+            return MYKGPIO0;
+        case gain_pin_t::PIN1:
+            return MYKGPIO1;
+        case gain_pin_t::PIN2:
+            return MYKGPIO2;
+        case gain_pin_t::PIN3:
+            return MYKGPIO3;
+        case gain_pin_t::PIN4:
+            return MYKGPIO4;
+        case gain_pin_t::PIN5:
+            return MYKGPIO5;
+        case gain_pin_t::PIN6:
+            return MYKGPIO6;
+        case gain_pin_t::PIN7:
+            return MYKGPIO7;
+        case gain_pin_t::PIN8:
+            return MYKGPIO8;
+        case gain_pin_t::PIN9:
+            return MYKGPIO9;
+        case gain_pin_t::PIN10:
+            return MYKGPIO10;
+        case gain_pin_t::PIN11:
+            return MYKGPIO11;
+        case gain_pin_t::PIN12:
+            return MYKGPIO12;
+        case gain_pin_t::PIN13:
+            return MYKGPIO13;
+        case gain_pin_t::PIN14:
+            return MYKGPIO14;
+        case gain_pin_t::PIN15:
+            return MYKGPIO15;
+        case gain_pin_t::PIN16:
+            return MYKGPIO16;
+        case gain_pin_t::PIN17:
+            return MYKGPIO17;
+        case gain_pin_t::PIN18:
+            return MYKGPIO18;
+        default:
+            return MYKGPIONAN;
     }
 }
 
-ad937x_gain_ctrl_channel_t::ad937x_gain_ctrl_channel_t(mykonosGpioSelect_t inc_pin, mykonosGpioSelect_t dec_pin) :
-    enable(DEFAULT_ENABLE),
-    inc_step(DEFAULT_GAIN_STEP),
-    dec_step(DEFAULT_GAIN_STEP),
-    inc_pin(inc_pin),
-    dec_pin(dec_pin)
+ad937x_gain_ctrl_channel_t::ad937x_gain_ctrl_channel_t(
+    mykonosGpioSelect_t inc_pin, mykonosGpioSelect_t dec_pin)
+    : enable(DEFAULT_ENABLE)
+    , inc_step(DEFAULT_GAIN_STEP)
+    , dec_step(DEFAULT_GAIN_STEP)
+    , inc_pin(inc_pin)
+    , dec_pin(dec_pin)
 {
-
 }
 
-mykonosGpioSelect_t _get_gain_pin(
-    direction_t direction,
+mykonosGpioSelect_t _get_gain_pin(direction_t direction,
     chain_t chain,
     pin_direction_t pin_direction,
-    const gain_pins_t & gain_pins)
+    const gain_pins_t& gain_pins)
 {
-    switch (direction)
-    {
-    case RX_DIRECTION:
-        switch (chain)
-        {
-        case chain_t::ONE:
-            switch (pin_direction)
-            {
-            case pin_direction_t::INCREASE: return _convert_gain_pin(gain_pins.rx1_inc_gain_pin);
-            case pin_direction_t::DECREASE: return _convert_gain_pin(gain_pins.rx1_dec_gain_pin);
-            }
-        case chain_t::TWO:
-            switch (pin_direction)
-            {
-            case pin_direction_t::INCREASE: return _convert_gain_pin(gain_pins.rx2_inc_gain_pin);
-            case pin_direction_t::DECREASE: return _convert_gain_pin(gain_pins.rx2_dec_gain_pin);
+    switch (direction) {
+        case RX_DIRECTION:
+            switch (chain) {
+                case chain_t::ONE:
+                    switch (pin_direction) {
+                        case pin_direction_t::INCREASE:
+                            return _convert_gain_pin(gain_pins.rx1_inc_gain_pin);
+                        case pin_direction_t::DECREASE:
+                            return _convert_gain_pin(gain_pins.rx1_dec_gain_pin);
+                    }
+                case chain_t::TWO:
+                    switch (pin_direction) {
+                        case pin_direction_t::INCREASE:
+                            return _convert_gain_pin(gain_pins.rx2_inc_gain_pin);
+                        case pin_direction_t::DECREASE:
+                            return _convert_gain_pin(gain_pins.rx2_dec_gain_pin);
+                    }
             }
-        }
 
-        // !!! TX is attenuation direction, so the pins are flipped !!!
-    case TX_DIRECTION:
-        switch (chain)
-        {
-        case chain_t::ONE:
-            switch (pin_direction)
-            {
-            case pin_direction_t::INCREASE: return _convert_gain_pin(gain_pins.tx1_dec_gain_pin);
-            case pin_direction_t::DECREASE: return _convert_gain_pin(gain_pins.tx1_inc_gain_pin);
+            // !!! TX is attenuation direction, so the pins are flipped !!!
+        case TX_DIRECTION:
+            switch (chain) {
+                case chain_t::ONE:
+                    switch (pin_direction) {
+                        case pin_direction_t::INCREASE:
+                            return _convert_gain_pin(gain_pins.tx1_dec_gain_pin);
+                        case pin_direction_t::DECREASE:
+                            return _convert_gain_pin(gain_pins.tx1_inc_gain_pin);
+                    }
+                case chain_t::TWO:
+                    switch (pin_direction) {
+                        case pin_direction_t::INCREASE:
+                            return _convert_gain_pin(gain_pins.tx2_dec_gain_pin);
+                        case pin_direction_t::DECREASE:
+                            return _convert_gain_pin(gain_pins.tx2_inc_gain_pin);
+                    }
             }
-        case chain_t::TWO:
-            switch (pin_direction)
-            {
-            case pin_direction_t::INCREASE: return _convert_gain_pin(gain_pins.tx2_dec_gain_pin);
-            case pin_direction_t::DECREASE: return _convert_gain_pin(gain_pins.tx2_inc_gain_pin);
-            }
-        }
 
-    default:
-        return MYKGPIONAN;
+        default:
+            return MYKGPIONAN;
     }
 }
 
 ad937x_gain_ctrl_config_t::ad937x_gain_ctrl_config_t(gain_pins_t gain_pins)
 {
-    config.emplace(std::piecewise_construct, std::forward_as_tuple(RX_DIRECTION), std::forward_as_tuple());
-    config.emplace(std::piecewise_construct, std::forward_as_tuple(TX_DIRECTION), std::forward_as_tuple());
+    config.emplace(std::piecewise_construct,
+        std::forward_as_tuple(RX_DIRECTION),
+        std::forward_as_tuple());
+    config.emplace(std::piecewise_construct,
+        std::forward_as_tuple(TX_DIRECTION),
+        std::forward_as_tuple());
 
-    config.at(RX_DIRECTION).emplace(std::piecewise_construct, std::forward_as_tuple(chain_t::ONE),
-        std::forward_as_tuple(
-        _get_gain_pin(RX_DIRECTION, chain_t::ONE, pin_direction_t::INCREASE, gain_pins),
-        _get_gain_pin(RX_DIRECTION, chain_t::ONE, pin_direction_t::DECREASE, gain_pins)));
-    config.at(RX_DIRECTION).emplace(std::piecewise_construct, std::forward_as_tuple(chain_t::TWO),
-        std::forward_as_tuple(
-        _get_gain_pin(RX_DIRECTION, chain_t::TWO, pin_direction_t::INCREASE, gain_pins),
-        _get_gain_pin(RX_DIRECTION, chain_t::TWO, pin_direction_t::DECREASE, gain_pins)));
+    config.at(RX_DIRECTION)
+        .emplace(std::piecewise_construct,
+            std::forward_as_tuple(chain_t::ONE),
+            std::forward_as_tuple(
+                _get_gain_pin(
+                    RX_DIRECTION, chain_t::ONE, pin_direction_t::INCREASE, gain_pins),
+                _get_gain_pin(
+                    RX_DIRECTION, chain_t::ONE, pin_direction_t::DECREASE, gain_pins)));
+    config.at(RX_DIRECTION)
+        .emplace(std::piecewise_construct,
+            std::forward_as_tuple(chain_t::TWO),
+            std::forward_as_tuple(
+                _get_gain_pin(
+                    RX_DIRECTION, chain_t::TWO, pin_direction_t::INCREASE, gain_pins),
+                _get_gain_pin(
+                    RX_DIRECTION, chain_t::TWO, pin_direction_t::DECREASE, gain_pins)));
 
-    config.at(TX_DIRECTION).emplace(std::piecewise_construct, std::forward_as_tuple(chain_t::ONE),
-        std::forward_as_tuple(
-        _get_gain_pin(TX_DIRECTION, chain_t::ONE, pin_direction_t::INCREASE, gain_pins),
-        _get_gain_pin(TX_DIRECTION, chain_t::ONE, pin_direction_t::DECREASE, gain_pins)));
-    config.at(TX_DIRECTION).emplace(std::piecewise_construct, std::forward_as_tuple(chain_t::TWO),
-        std::forward_as_tuple(
-        _get_gain_pin(TX_DIRECTION, chain_t::TWO, pin_direction_t::INCREASE, gain_pins),
-        _get_gain_pin(TX_DIRECTION, chain_t::TWO, pin_direction_t::DECREASE, gain_pins)));
+    config.at(TX_DIRECTION)
+        .emplace(std::piecewise_construct,
+            std::forward_as_tuple(chain_t::ONE),
+            std::forward_as_tuple(
+                _get_gain_pin(
+                    TX_DIRECTION, chain_t::ONE, pin_direction_t::INCREASE, gain_pins),
+                _get_gain_pin(
+                    TX_DIRECTION, chain_t::ONE, pin_direction_t::DECREASE, gain_pins)));
+    config.at(TX_DIRECTION)
+        .emplace(std::piecewise_construct,
+            std::forward_as_tuple(chain_t::TWO),
+            std::forward_as_tuple(
+                _get_gain_pin(
+                    TX_DIRECTION, chain_t::TWO, pin_direction_t::INCREASE, gain_pins),
+                _get_gain_pin(
+                    TX_DIRECTION, chain_t::TWO, pin_direction_t::DECREASE, gain_pins)));
 }
-
diff --git a/mpm/lib/mykonos/config/ad937x_gain_ctrl_config.hpp b/mpm/lib/mykonos/config/ad937x_gain_ctrl_config.hpp
index 380efb0de..12851af92 100644
--- a/mpm/lib/mykonos/config/ad937x_gain_ctrl_config.hpp
+++ b/mpm/lib/mykonos/config/ad937x_gain_ctrl_config.hpp
@@ -8,31 +8,29 @@
 
 #include "../ad937x_device_types.hpp"
 #include "../adi/t_mykonos.h"
-
 #include "mpm/ad937x/ad937x_ctrl_types.hpp"
-
-#include <vector>
 #include <unordered_map>
+#include <vector>
 
-// C++14 requires std::hash includes a specialization for enums, but gcc doesn't do that yet
-// Remove this when that happens
+// C++14 requires std::hash includes a specialization for enums, but gcc doesn't do that
+// yet Remove this when that happens
 namespace std {
-    template <> struct hash<uhd::direction_t>
+template <> struct hash<uhd::direction_t>
+{
+    size_t operator()(const uhd::direction_t& x) const
     {
-        size_t operator()(const uhd::direction_t & x) const
-        {
-            return static_cast<std::size_t>(x);
-        }
-    };
+        return static_cast<std::size_t>(x);
+    }
+};
 
-    template <> struct hash<mpm::ad937x::device::chain_t>
+template <> struct hash<mpm::ad937x::device::chain_t>
+{
+    size_t operator()(const mpm::ad937x::device::chain_t& x) const
     {
-        size_t operator()(const mpm::ad937x::device::chain_t & x) const
-        {
-            return static_cast<std::size_t>(x);
-        }
-    };
-}
+        return static_cast<std::size_t>(x);
+    }
+};
+} // namespace std
 
 // collection of the 5 attributes that define the gain pins for a channel in Mykonos
 struct ad937x_gain_ctrl_channel_t
@@ -54,9 +52,8 @@ private:
 struct ad937x_gain_ctrl_config_t
 {
     std::unordered_map<uhd::direction_t,
-        std::unordered_map<mpm::ad937x::device::chain_t, ad937x_gain_ctrl_channel_t>> config;
+        std::unordered_map<mpm::ad937x::device::chain_t, ad937x_gain_ctrl_channel_t>>
+        config;
 
     ad937x_gain_ctrl_config_t(mpm::ad937x::gpio::gain_pins_t gain_pins);
 };
-
-