mpm: Implement 32 bit register interface with SPI

Implement SPI transfers which are 12 bytes in length to support
access for 32 bit register interfaces. 12 byte transactions are
necessary for Titanium MB PS CPLD SPI transactions. This implementation
supports 48 bits of TX data per transfer and offsets all flags and
data shifts from the end of the TX data portion of the transfer buffer
rather than the end of the entire transfer buffer.

1 files changed, 12 insertions, 0 deletions

diff --git a/mpm/lib/i2c/i2c_regs_iface.cpp b/mpm/lib/i2c/i2c_regs_iface.cpp
index 575e19d26..0fd5e716c 100644
--- a/mpm/lib/i2c/i2c_regs_iface.cpp
+++ b/mpm/lib/i2c/i2c_regs_iface.cpp
@@ -93,6 +93,18 @@ public:
         }
     }
 
+    uint32_t peek32(const uint64_t addr)
+    {
+        throw mpm::not_implemented_error(
+            "I2C regs iface does not implement 32 bit transactions.");
+    }
+
+    void poke32(const uint64_t addr, const uint32_t data)
+    {
+        throw mpm::not_implemented_error(
+            "I2C regs iface does not implement 32 bit transactions.");
+    }
+
 private:
     mpm::i2c::i2c_iface::sptr _i2c_iface;