uhd: Add support for the USRP X410

Co-authored-by: Lars Amsel <lars.amsel@ni.com>
Co-authored-by: Michael Auchter <michael.auchter@ni.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Cristina Fuentes <cristina.fuentes-curiel@ni.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Virendra Kakade <virendra.kakade@ni.com>
Co-authored-by: Lane Kolbly <lane.kolbly@ni.com>
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Andrew Lynch <andrew.lynch@ni.com>
Co-authored-by: Grant Meyerhoff <grant.meyerhoff@ni.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Thomas Vogel <thomas.vogel@ni.com>

9 files changed, 5461 insertions, 6 deletions

diff --git a/mpm/include/mpm/CMakeLists.txt b/mpm/include/mpm/CMakeLists.txt
index d4caff1c4..4a5a3acc2 100644
--- a/mpm/include/mpm/CMakeLists.txt
+++ b/mpm/include/mpm/CMakeLists.txt
@@ -18,3 +18,7 @@ add_subdirectory(chips)
 add_subdirectory(dboards)
 add_subdirectory(spi)
 add_subdirectory(types)
+
+if(ENABLE_X400)
+  add_subdirectory(rfdc)
+endif(ENABLE_X400)
diff --git a/mpm/include/mpm/i2c/i2c_iface.hpp b/mpm/include/mpm/i2c/i2c_iface.hpp
index c49a70b48..02dc23acf 100644
--- a/mpm/include/mpm/i2c/i2c_iface.hpp
+++ b/mpm/include/mpm/i2c/i2c_iface.hpp
@@ -43,16 +43,17 @@ public:
 
     /*!
      * \param tx Buffer of data to send
-     * \param rx Buffer to hold read data
+     * \param rx_num_bytes Number of bytes to read into rx return buffer
      * \param do_close If true, close file descriptor at end of function
+     * \return Buffer of rx data
      *
      * All data in tx will be transmitted.
-     * The amount of data read will be determined by the number of elements
-     * in the rx vector. Those elements will be overwritten with the data.
-     * Use the resize() function for a new rx vector.
+     * The amount of data read will be determined by num_rx_bytes and written
+     * into the return buffer.
      */
-    virtual int transfer(
-        std::vector<uint8_t>* tx, std::vector<uint8_t>* rx, bool do_close = true) = 0;
+    virtual std::vector<uint8_t> transfer(
+        std::vector<uint8_t>& tx, size_t num_rx_bytes, bool do_close = true) = 0;
+
 };
 
 }}; /* namespace mpm::i2c */
diff --git a/mpm/include/mpm/i2c/i2c_python.hpp b/mpm/include/mpm/i2c/i2c_python.hpp
index ebc9cb0a1..18209adf2 100644
--- a/mpm/include/mpm/i2c/i2c_python.hpp
+++ b/mpm/include/mpm/i2c/i2c_python.hpp
@@ -14,5 +14,9 @@ void export_i2c(py::module& top_module)
 {
     auto m = top_module.def_submodule("i2c");
 
+    m.def("make_i2cdev", &mpm::i2c::i2c_iface::make_i2cdev);
     m.def("make_i2cdev_regs_iface", &mpm::i2c::make_i2cdev_regs_iface);
+
+    py::class_<mpm::i2c::i2c_iface, std::shared_ptr<mpm::i2c::i2c_iface>>(m, "i2c_iface")
+        .def("transfer", (std::vector<uint8_t> (mpm::i2c::i2c_iface::*)(std::vector<uint8_t>&, size_t, bool)) &mpm::i2c::i2c_iface::transfer, "Transfer i2c data");
 }
diff --git a/mpm/include/mpm/rfdc/CMakeLists.txt b/mpm/include/mpm/rfdc/CMakeLists.txt
new file mode 100644
index 000000000..cbd1ce5bc
--- /dev/null
+++ b/mpm/include/mpm/rfdc/CMakeLists.txt
@@ -0,0 +1,13 @@
+#
+# Copyright 2019 Ettus Research, National Instruments Brand
+#
+# SPDX-License-Identifier: GPL-3.0
+#
+install(FILES
+    rfdc_ctrl.hpp
+    rfdc_throw.h
+    xrfdc_hw.h
+    xrfdc_mts.h
+    xrfdc.h
+    DESTINATION ${INCLUDE_DIR}/mpm/rfdc
+)
diff --git a/mpm/include/mpm/rfdc/rfdc_ctrl.hpp b/mpm/include/mpm/rfdc/rfdc_ctrl.hpp
new file mode 100644
index 000000000..411b70c90
--- /dev/null
+++ b/mpm/include/mpm/rfdc/rfdc_ctrl.hpp
@@ -0,0 +1,755 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Brand
+//
+// SPDX-License-Identifier: GPL-3.0-or-later
+//
+
+#pragma once
+
+#include "xrfdc.h"
+#include "xrfdc_mts.h"
+#include <boost/noncopyable.hpp>
+#include <vector>
+
+#ifdef LIBMPM_PYTHON
+#    include <pybind11/stl.h>
+#endif
+
+#define THRESHOLDS_PER_BLOCK 2
+
+namespace mpm { namespace rfdc {
+
+/**
+ * A class to control the Xilinx RFdc driver.
+ * This will be imported into a MPM shared library.
+ */
+class rfdc_ctrl : public boost::noncopyable
+{
+    XRFdc rfdc_inst;
+    XRFdc* rfdc_inst_ptr;
+    XRFdc_MultiConverter_Sync_Config rfdc_dac_sync_config;
+    XRFdc_MultiConverter_Sync_Config rfdc_adc_sync_config;
+    uint16_t rfdc_device_id;
+
+public:
+    /**
+     * These macros are placed within enums so they can be imported to Python.
+     * They are originally defined in xrfdc.h
+     */
+    enum threshold_id_options {
+        THRESHOLD_0    = XRFDC_UPDATE_THRESHOLD_0,
+        THRESHOLD_1    = XRFDC_UPDATE_THRESHOLD_1,
+        THRESHOLD_BOTH = XRFDC_UPDATE_THRESHOLD_BOTH
+    };
+    enum threshold_mode_options {
+        TRSHD_OFF          = XRFDC_TRSHD_OFF,
+        TRSHD_STICKY_OVER  = XRFDC_TRSHD_STICKY_OVER,
+        TRSHD_STICKY_UNDER = XRFDC_TRSHD_STICKY_UNDER,
+        TRSHD_HYSTERESIS   = XRFDC_TRSHD_HYSTERISIS
+    };
+    enum threshold_clr_mode_options {
+        THRESHOLD_CLRMD_MANUAL = XRFDC_THRESHOLD_CLRMD_MANUAL_CLR,
+        THRESHOLD_CLRMD_AUTO   = XRFDC_THRESHOLD_CLRMD_AUTO_CLR,
+        // The XRFdc Threshold clear modes currently only go up to 2
+        // This assumes there will never be a clear mode of value 99
+        THRESHOLD_CLRMD_UNKNOWN = 99
+    };
+    enum decoder_mode_options {
+        DECODER_MAX_SNR_MODE = XRFDC_DECODER_MAX_SNR_MODE, // for non-randomized decoder
+        DECODER_MAX_LINEARITY_MODE =
+            XRFDC_DECODER_MAX_LINEARITY_MODE // for randomized decoder
+    };
+    enum nyquist_zone_options {
+        ODD_NYQUIST_ZONE  = XRFDC_ODD_NYQUIST_ZONE,
+        EVEN_NYQUIST_ZONE = XRFDC_EVEN_NYQUIST_ZONE
+    };
+    enum mixer_mode_options {
+        MIXER_MODE_OFF = XRFDC_MIXER_MODE_OFF,
+        MIXER_MODE_C2C = XRFDC_MIXER_MODE_C2C, // Complex to complex
+        MIXER_MODE_C2R = XRFDC_MIXER_MODE_C2R, // Complex to real
+        MIXER_MODE_R2C = XRFDC_MIXER_MODE_R2C, // Real to complex
+        MIXER_MODE_R2R = XRFDC_MIXER_MODE_R2R // Real to real
+    };
+    /**
+     * See section "RF-ADC Settings" of the Xilinx
+     * "RF Data Converter Interface User Guide" to learn
+     * more about the calibration modes.
+     */
+    enum calibration_mode_options {
+        CALIB_MODE1 = XRFDC_CALIB_MODE1,
+        CALIB_MODE2 = XRFDC_CALIB_MODE2
+    };
+    enum event_type_options {
+        MIXER_EVENT = XRFDC_EVENT_MIXER,
+        CRSE_DLY_EVENT = XRFDC_EVENT_CRSE_DLY,
+        QMC_EVENT = XRFDC_EVENT_QMC,
+    };
+    enum interp_decim_options {
+        INTERP_DECIM_OFF = XRFDC_INTERP_DECIM_OFF,
+        INTERP_DECIM_1X  = XRFDC_INTERP_DECIM_1X,
+        INTERP_DECIM_2X  = XRFDC_INTERP_DECIM_2X,
+        INTERP_DECIM_4X  = XRFDC_INTERP_DECIM_4X,
+        INTERP_DECIM_8X  = XRFDC_INTERP_DECIM_8X,
+    };
+    enum fabric_clk_div_options {
+        DIV_1  = XRFDC_FAB_CLK_DIV1,
+        DIV_2  = XRFDC_FAB_CLK_DIV2,
+        DIV_4  = XRFDC_FAB_CLK_DIV4,
+        DIV_8  = XRFDC_FAB_CLK_DIV8,
+        DIV_16 = XRFDC_FAB_CLK_DIV16,
+    };
+
+    /**
+     * Assignes the rfdc_inst_ptr to an instance of the Xilinx RFdc driver
+     */
+    rfdc_ctrl();
+
+    /**
+     * Closes the libmetal device
+     */
+    ~rfdc_ctrl();
+
+    /**
+     * Initializes the driver by reading configuration settings
+     * from the device found in the device tree and applying them to
+     * the driver instance.
+     * Throws an exception if init fails.
+     *
+     * @param    rfdc_device_id the device ID of the rfdc device
+     */
+    void init(uint16_t rfdc_device_id);
+
+    /**
+     * Starts up the requested tile while retaining register values.
+     *
+     * @param    tile_id the ID of the tile to start.
+     *           Pass -1 to select all tiles.
+     * @param    is_dac whether the tile is a DAC (true) or ADC (false)
+     *
+     * @return   true if the operation was successful
+     */
+    bool startup_tile(int tile_id, bool is_dac);
+
+    /**
+     * Shuts down the requested tile while retaining register values.
+     *
+     * @param    tile_id the ID of the tile to stop.
+     *           Pass -1 to select all tiles.
+     * @param    is_dac whether the tile is a DAC (true) or ADC (false)
+     *
+     * @return   true if the operation was successful
+     */
+    bool shutdown_tile(int tile_id, bool is_dac);
+
+    /**
+     * Restarts the requested tile while resetting registers to default values.
+     *
+     * @param    tile_id the ID of the tile to restart.
+     *           Pass -1 to select all tiles.
+     * @param    is_dac whether the tile is a DAC (true) or ADC (false)
+     *
+     * @return   true if the operation was successful
+     */
+    bool reset_tile(int tile_id, bool is_dac);
+
+    /**
+     * Triggers an update event for a given component.
+     *
+     * @param    tile_id the tile ID of the block to trigger
+     * @param    block_id the block ID of the block to trigger
+     * @param    is_dac whether the block is a DAC (true) or ADC (false)
+     * @param    event_type which component of block to update
+     *           See event_type_options for valid values.
+     *
+     * @return   true if the operation was successful
+     */
+    bool trigger_update_event(uint32_t tile_id, uint32_t block_id,
+       bool is_dac, event_type_options event_type);
+
+    /**
+     * Enable/Disable gain correction for a given block.
+     *
+     * @param    tile_id the tile ID of the block to set
+     * @param    block_id the block ID of the block to set
+     * @param    is_dac whether the block is a DAC (true) or ADC (false)
+     * @param    enable whether to enable or disable gain correction
+     *
+     * @return   true if the operation was successful
+     */
+    bool set_gain_enable(uint32_t tile_id, uint32_t block_id, bool is_dac, bool enable);
+
+    /**
+     * Set gain correction on a given ADC or DAC block
+     *
+     * @param    tile_id the tile ID of the block to set
+     * @param    block_id the block ID of the block to set
+     * @param    is_dac whether the block is a DAC (true) or ADC (false)
+     * @param    gain the gain correction to set.
+     *           Valid values are 0.0-2.0
+     *
+     * @return   true if the operation was successful
+     */
+    bool set_gain(uint32_t tile_id, uint32_t block_id, bool is_dac, double gain);
+
+    /**
+     * Set the threshold settings for a given ADC
+     *
+     * @param    tile_id the tile ID of the block to set
+     * @param    block_id the block ID of the block to set
+     * @param    threshold_id the ID of the threshold to modify.
+     *           See threshold_id_options for valid values.
+     * @param    mode the threshold mode to set.
+     *           See threshold_mode_options for valid values.
+     * @param    average_val the average threshold value
+     * @param    under_val the under threshold value
+     * @param    over_val the over threshold value
+     *
+     * @return   true if the operation was successful
+     */
+    bool set_threshold_settings(uint32_t tile_id,
+        uint32_t block_id,
+        threshold_id_options threshold_id,
+        threshold_mode_options mode,
+        uint32_t average_val,
+        uint32_t under_val,
+        uint32_t over_val);
+
+    /**
+     * Clears the sticky line which indicates a threshold has been breached.
+     * This will also set the sticky clear mode to be manual.
+     *
+     * @param    tile_id the tile ID of the block to set
+     * @param    block_id the block ID of the block to set
+     * @param    threshold_id the ID of the threshold to modify.
+     *           See threshold_id_options for valid values.
+     *
+     * @return   true if the operation was successful
+     */
+    bool clear_threshold_sticky(
+        uint32_t tile_id, uint32_t block_id, threshold_id_options threshold_id);
+
+    /**
+     * Sets whether the threshold breach sticky is cleared manually
+     * or automatically (when QMC gain is changed).
+     *
+     * @param    tile_id the tile ID of the block to set
+     * @param    block_id the block ID of the block to set
+     * @param    threshold_id the ID of the threshold to modify.
+     *           See threshold_id_options for valid values.
+     * @param    mode What mode to set for the threshold sticky clear mode.
+     *           See threshold_clr_mode_options for valid values.
+     *
+     * @return   true if the operation was successful
+     */
+    bool set_threshold_clr_mode(uint32_t tile_id,
+        uint32_t block_id,
+        threshold_id_options threshold_id,
+        threshold_clr_mode_options clear_mode);
+
+    /**
+     * Gets the threshold sticky clear mode
+     *
+     * @param    tile_id the tile ID of the block to set
+     * @param    block_id the block ID of the block to set
+     * @param    threshold_id the ID of the threshold to modify.
+     *           See threshold_id_options for valid values.
+     *           Note: THRESHOLD_BOTH is not a valid threshold_id for this
+     *           method and will result in THRESHOLD_CLRMD_UNKNOWN.
+     * @param    mode What mode to set for the threshold sticky clear mode.
+     *           See threshold_clr_mode_options for valid values.
+     *
+     * @return   threshold_clr_mode_options which is currently set.
+     *           A value of THRESHOLD_CLRMD_UNKNOWN indicates that the hardware
+     *           setting is currently unknown or an invalid ID was given.
+     */
+    threshold_clr_mode_options get_threshold_clr_mode(
+        uint32_t tile_id, uint32_t block_id, threshold_id_options threshold_id);
+
+    /**
+     * Sets the decoder mode of a given DAC
+     * An auto-clear takes place when the gain setting is changed.
+     *
+     * @param    tile_id the tile ID of the block to set
+     * @param    block_id the block ID of the block to set
+     * @param    decoder_mode the desired decoder mode for the DAC.
+     *           See decoder_mode_options for valid values.
+     *
+     * @return   true if the operation was successful
+     */
+    bool set_decoder_mode(
+        uint32_t tile_id, uint32_t block_id, decoder_mode_options decoder_mode);
+
+    /**
+     * Resets the NCO phase of the current block phase accumulator.
+     *
+     * @param    tile_id the tile ID of the block to set
+     * @param    block_id the block ID of the block to set
+     * @param    is_dac whether the block is a DAC (true) or ADC (false)
+     *
+     * @return   true if the operation was successful
+     */
+    bool reset_nco_phase(uint32_t tile_id, uint32_t block_id, bool is_dac);
+
+    /**
+     * Sets the NCO event source for a given DAC or ADC
+     *
+     * @param    tile_id the tile ID of the block to set
+     * @param    block_id the block ID of the block to set
+     * @param    is_dac whether the block is a DAC (true) or ADC (false)
+     *
+     * @return   true if the operation was successful
+     */
+    bool set_nco_event_src(uint32_t tile_id, uint32_t block_id, bool is_dac);
+
+    /**
+     * Sets the NCO frequency for a given DAC or ADC
+     *
+     * @param    tile_id the tile ID of the block to set
+     * @param    block_id the block ID of the block to set
+     * @param    is_dac whether the block is a DAC (true) or ADC (false)
+     * @param    freq the NCO frequency to set
+     *           Frequencies are specified in Hz.
+     *
+     * @return   true if the operation was successful
+     */
+    bool set_nco_freq(uint32_t tile_id, uint32_t block_id, bool is_dac, double freq);
+
+    /**
+     * Gets the NCO frequency for a given DAC or ADC
+     *
+     * @param    tile_id the tile ID of the block
+     * @param    block_id the block ID of the block
+     * @param    is_dac whether the block is a DAC (true) or ADC (false)
+     *
+     * @return   freq of the NCO in Hz
+     */
+    double get_nco_freq(uint32_t tile_id, uint32_t block_id, bool is_dac);
+
+    /**
+     * Sets the mixer mode of the given block
+     *
+     * @param    tile_id the tile ID of the block to set
+     * @param    block_id the block ID of the block to set
+     * @param    is_dac whether the block is a DAC (true) or ADC (false)
+     * @param    mixer_mode the mixer mode to set.
+     *           See mixer_mode_options for valid values
+     *
+     * @return   true if the operation was successful
+     */
+    bool set_mixer_mode(
+        uint32_t tile_id, uint32_t block_id, bool is_dac, mixer_mode_options mixer_mode);
+
+    /**
+     * Sets the Nyquist Zone of a give block
+     *
+     * @param    tile_id the tile ID of the block to set
+     * @param    block_id the block ID of the block to set
+     * @param    is_dac whether the block is a DAC (true) or ADC (false)
+     * @param    nyquist_zone the nyquist zone to set
+     *           See nyquist_zone_options for valid values.
+     *
+     * @return   true if the operation was successful
+     */
+    bool set_nyquist_zone(uint32_t tile_id,
+        uint32_t block_id,
+        bool is_dac,
+        nyquist_zone_options nyquist_zone);
+
+    /**
+     * Sets the calibration mode of a given ADC
+     *
+     * @param    tile_id the tile ID of the block to set
+     * @param    block_id the block ID of the block to set
+     * @param    calibration_mode the calibration mode to set.
+     *           See calibration_mode_options for valid values.
+     *           See section "RF-ADC Settings" of the Xilinx
+     *           "RF Data Converter Interface User Guide" to learn
+     *           more about the modes.
+     *
+     * @return   true if the operation was successful
+     */
+    bool set_calibration_mode(
+        uint32_t tile_id, uint32_t block_id, calibration_mode_options calibration_mode);
+
+    /**
+     * Enables/Disables the Inverse-Sinc filter on a DAC block.
+     *
+     * @param    tile_id the tile ID of the block to set
+     * @param    block_id the block ID of the block to set
+     * @param    enable enables the filter if true, disables if false
+     *
+     * @return   true if the operation was successful
+     */
+    bool enable_inverse_sinc_filter(uint32_t tile_id, uint32_t block_id, bool enable);
+
+    /**
+     * Sets the sample rate for a given tile.
+     *
+     * @param    tile_id the ID of the tile to set
+     * @param    is_dac whether the tile is a DAC (true) or ADC (false)
+     * @param    sample_rate the rate in Hz to sample at
+     *
+     * @return   true if the operation was successful
+     */
+    bool set_sample_rate(uint32_t tile_id, bool is_dac, double sample_rate);
+
+    /**
+     * Gets the sample rate for a given block.
+     *
+     * @param    tile_id the ID of the tile to set
+     * @param    block_id the ID of the block to set
+     * @param    is_dac whether the tile is a DAC (true) or ADC (false)
+     *
+     * @return   sample rate of the block in Hz
+     */
+    double get_sample_rate(uint32_t tile_id, uint32_t block_id, bool is_dac);
+
+    /**
+     * Specifies the IF for the given ADC or DAC.
+     * Setting this will determine the Nyquist zone, mixer mode,
+     * Inverse Sinc filter, and mixer NCO frequency.
+     *
+     * @param    tile_id the tile ID of the block to set
+     * @param    block_id the block ID of the block to set
+     * @param    is_dac whether the block is a DAC (true) or ADC (false)
+     * @param    if_freq the IF frequency expected for the block.
+     *           Frequencies are specified in Hz.
+     *
+     * @return   true all resulting settings were successfully changed
+     */
+    bool set_if(uint32_t tile_id, uint32_t block_id, bool is_dac, double if_freq);
+
+    /**
+     * Sets the decimation factor for a given ADC block
+     *
+     * @param    tile_id the ID of the tile to set
+     * @param    block_id the block ID of the block to set
+     * @param    decimation_factor the desired factor
+     *           See interp_decim_options for valid values
+     *
+     * @return   true if the operation was successful
+     */
+    bool set_decimation_factor(
+        uint32_t tile_id, uint32_t block_id, interp_decim_options decimation_factor);
+
+    /**
+     * Gets the decimation factor for a given ADC block
+     *
+     * @param    tile_id the ID of the tile to get
+     * @param    block_id the block ID of the block to get
+     *
+     * @return   the actual decimation factor
+     *           See interp_decim_options for valid values
+     */
+    interp_decim_options get_decimation_factor(uint32_t tile_id, uint32_t block_id);
+
+    /**
+     * Sets the interpolation factor for a given DAC block
+     *
+     * @param    tile_id the ID of the tile to set
+     * @param    block_id the block ID of the block to set
+     * @param    interpolation_factor the desired factor
+     *           See interp_decim_options for valid values.
+     *
+     * @return   true if the operation was successful
+     */
+    bool set_interpolation_factor(
+        uint32_t tile_id, uint32_t block_id, interp_decim_options interpolation_factor);
+
+    /**
+     * Gets the interpolation factor for a given DAC block
+     *
+     * @param    tile_id the ID of the tile to get
+     * @param    block_id the block ID of the block to get
+     *
+     * @return   the actual interpolation factor
+     *           See interp_decim_options for valid values
+     */
+    interp_decim_options get_interpolation_factor(uint32_t tile_id, uint32_t block_id);
+
+    /**
+     * Sets the number of valid read words for a given ADC block
+     *
+     * @param    tile_id the ID of the tile to set
+     * @param    block_id the block ID of the block to set
+     * @param    valid_read_words the number of valid read words
+     *
+     * @return   true if the operation was successful
+     */
+    bool set_data_read_rate(
+        uint32_t tile_id, uint32_t block_id, uint32_t valid_read_words);
+
+    /**
+     * Gets the number of valid read words for a given ADC/DAC block
+     *
+     * @param    tile_id the ID of the tile to get
+     * @param    block_id the block ID of the block to get
+     * @param    is_dac whether the tile is a DAC (true) or ADC (false)
+     *
+     * @return   the valid read words
+     */
+    uint32_t get_data_read_rate(uint32_t tile_id, uint32_t block_id, bool is_dac);
+
+    /**
+     * Sets the number of valid write words for a given DAC block
+     *
+     * @param    tile_id the ID of the tile to set
+     * @param    block_id the block ID of the block to set
+     * @param    valid_write_words the number of valid write words
+     *
+     * @return   true if the operation was successful
+     */
+    bool set_data_write_rate(
+        uint32_t tile_id, uint32_t block_id, uint32_t valid_write_words);
+
+    /**
+     * Gets the number of valid write words for a given ADC/DAC block
+     *
+     * @param    tile_id the ID of the tile to get
+     * @param    block_id the block ID of the block to get
+     * @param    is_dac whether the tile is a DAC (true) or ADC (false)
+
+     *
+     * @return   the valid write words
+     */
+    uint32_t get_data_write_rate(uint32_t tile_id, uint32_t block_id, bool is_dac);
+
+    /**
+     * Sets the clock fabric output divider of a given tile
+     *
+     * @param    tile_id the ID of the tile to set
+     * @param    is_dac whether the tile is a DAC (true) or ADC (false)
+     * @param    divider the divider to set
+     *           See fabric_clk_div_options for valid values
+     *
+     * @return   true if the operation was successful
+     */
+    bool set_fabric_clk_div(
+        uint32_t tile_id, bool is_dac, fabric_clk_div_options divider);
+
+    /**
+     * Gets the fabric clock divider rate of a Tile
+     *
+     * @param    tile_id the ID of the tile to get
+     * @param    is_dac whether the tile is a DAC (true) or ADC (false)
+     *
+     * @return   the fabric clock divider
+     *           See fabric_clk_div_options for valid values
+     */
+    fabric_clk_div_options get_fabric_clk_div(uint32_t tile_id, bool is_dac);
+
+    /**
+     * Sets the FIFO for an ADC/DAC
+     *
+     * @param    tile_id the ID of the tile to get
+     * @param    is_dac whether the tile is a DAC (true) or ADC (false)
+     * @param    enable enables (true) or disables (false) the FIFO
+
+     *
+     * @return   true if the operation was successful
+     */
+    bool set_data_fifo_state(uint32_t tile_id, bool is_dac, bool enable);
+
+    /**
+     * Gets the FIFO for an ADC/DAC
+     *
+     * @param    tile_id the ID of the tile to get
+     * @param    is_dac whether the tile is a DAC (true) or ADC (false)
+
+     *
+     * @return   true if FIFO is enabled, false if it is disabled
+     */
+    bool get_data_fifo_state(uint32_t tile_id, bool is_dac);
+
+    /**
+     * Clears the interrupts for the data FIFO (FIFOUSRDAT)
+     *
+     * @param    tile_id the ID of the tile to get
+     * @param    block_id specify ADC/DAC block
+     * @param    is_dac whether the tile is a DAC (true) or ADC (false)
+     */
+    void clear_data_fifo_interrupts(
+        const uint32_t tile_id, const uint32_t block_id, const bool is_dac);
+
+    /**
+     * Perform Multi-tile Synchronization on ADC or DAC tiles
+     *
+     * @param    tiles tiles vector to specify which DAC/ADC tiles to synchronize
+     * @param    is_dac whether the tile is a DAC (true) or ADC (false)
+     *
+     * @return   true if synchronization completed successfully
+     */
+    bool sync_tiles(const std::vector<uint32_t>& tiles, bool is_dac, uint32_t latency);
+
+    /**
+     * Get post-sync latency between ADC or DAC tiles
+     *
+     * @param    tile_index specify ADC or DAC target tile
+     * @param    is_dac whether the tile is a DAC (true) or ADC (false)
+     *
+     * @return   the measured relative latency value of each tile
+     */
+    uint32_t get_tile_latency(uint32_t tile_index, bool is_dac);
+
+    /**
+     * Get post-sync offset between ADC or DAC tile and reference tile
+     *
+     * @param    tile_index specify ADC or DAC target tile
+     * @param    is_dac whether the tile is a DAC (true) or ADC (false)
+     *
+     * @return   value the interface data was delayed to achieve alignment
+     */
+    uint32_t get_tile_offset(uint32_t tile_index, bool is_dac);
+
+    /**
+     * Sets whether or not the ADC calibration blocks are frozen
+     *
+     * @param    tile_id specify ADC target tile
+     * @param    block_id specify ADC block
+     * @param    frozen specify whether or not the ADC calibration blocks should be frozen
+     */
+    void set_cal_frozen(uint32_t tile_id, uint32_t block_id, bool frozen);
+
+    /**
+     * Sets whether or not the ADC calibration blocks are frozen
+     *
+     * @param    tile_id specify ADC target tile
+     * @param    block_id specify ADC block
+     *
+     * @return   true if the cal blocks are frozen, false if not
+     */
+    bool get_cal_frozen(uint32_t tile_id, uint32_t block_id);
+
+    void set_adc_cal_coefficients(uint32_t tile_id, uint32_t block_id, uint32_t cal_block, std::vector<uint32_t> coefs);
+    std::vector<uint32_t> get_adc_cal_coefficients(uint32_t tile_id, uint32_t block_id, uint32_t cal_block);
+
+    /**
+     * Resets an internal mixer with known valid settings.
+     */
+    bool reset_mixer_settings( uint32_t tile_id, uint32_t block_id, bool is_dac);
+
+private:
+    /* Indicates whether libmetal was initialized successfully and can
+     * be safely deinitialized.
+     */
+    bool metal_init_complete = false;
+
+    // Stores the current threshold clear mode according to
+    // [Tile ID][Block ID][Threshold ID]
+    threshold_clr_mode_options threshold_clr_modes[XRFDC_TILE_ID_MAX + 1]
+                                                  [XRFDC_BLOCK_ID_MAX + 1]
+                                                  [THRESHOLDS_PER_BLOCK];
+};
+}}; /* namespace mpm::rfdc */
+
+#ifdef LIBMPM_PYTHON
+void export_rfdc(py::module& top_module)
+{
+    using namespace mpm::rfdc;
+    auto m = top_module.def_submodule("rfdc");
+
+    py::class_<rfdc_ctrl, std::shared_ptr<rfdc_ctrl>>(m, "rfdc_ctrl")
+        .def(py::init())
+        .def("init", &rfdc_ctrl::init)
+        .def("startup_tile", &rfdc_ctrl::startup_tile)
+        .def("shutdown_tile", &rfdc_ctrl::shutdown_tile)
+        .def("reset_tile", &rfdc_ctrl::reset_tile)
+        .def("trigger_update_event", &rfdc_ctrl::trigger_update_event)
+        .def("set_gain_enable", &rfdc_ctrl::set_gain_enable)
+        .def("set_gain", &rfdc_ctrl::set_gain)
+        .def("set_threshold_settings", &rfdc_ctrl::set_threshold_settings)
+        .def("clear_threshold_sticky", &rfdc_ctrl::clear_threshold_sticky)
+        .def("set_threshold_clr_mode", &rfdc_ctrl::set_threshold_clr_mode)
+        .def("get_threshold_clr_mode", &rfdc_ctrl::get_threshold_clr_mode)
+        .def("set_decoder_mode", &rfdc_ctrl::set_decoder_mode)
+        .def("reset_nco_phase", &rfdc_ctrl::reset_nco_phase)
+        .def("set_nco_event_src", &rfdc_ctrl::set_nco_event_src)
+        .def("set_nco_freq", &rfdc_ctrl::set_nco_freq)
+        .def("get_nco_freq", &rfdc_ctrl::get_nco_freq)
+        .def("reset_mixer_settings", &rfdc_ctrl::reset_mixer_settings)
+        .def("set_mixer_mode", &rfdc_ctrl::set_mixer_mode)
+        .def("set_nyquist_zone", &rfdc_ctrl::set_nyquist_zone)
+        .def("set_calibration_mode", &rfdc_ctrl::set_calibration_mode)
+        .def("enable_inverse_sinc_filter", &rfdc_ctrl::enable_inverse_sinc_filter)
+        .def("set_sample_rate", &rfdc_ctrl::set_sample_rate)
+        .def("get_sample_rate", &rfdc_ctrl::get_sample_rate)
+        .def("set_if", &rfdc_ctrl::set_if)
+        .def("set_decimation_factor", &rfdc_ctrl::set_decimation_factor)
+        .def("get_decimation_factor", &rfdc_ctrl::get_decimation_factor)
+        .def("set_interpolation_factor", &rfdc_ctrl::set_interpolation_factor)
+        .def("get_interpolation_factor", &rfdc_ctrl::get_interpolation_factor)
+        .def("set_data_read_rate", &rfdc_ctrl::set_data_read_rate)
+        .def("get_data_read_rate", &rfdc_ctrl::get_data_read_rate)
+        .def("set_data_write_rate", &rfdc_ctrl::set_data_write_rate)
+        .def("get_data_write_rate", &rfdc_ctrl::get_data_write_rate)
+        .def("set_fabric_clk_div", &rfdc_ctrl::set_fabric_clk_div)
+        .def("get_fabric_clk_div", &rfdc_ctrl::get_fabric_clk_div)
+        .def("set_data_fifo_state", &rfdc_ctrl::set_data_fifo_state)
+        .def("get_data_fifo_state", &rfdc_ctrl::get_data_fifo_state)
+        .def("clear_data_fifo_interrupts", &rfdc_ctrl::clear_data_fifo_interrupts)
+        .def("sync_tiles", &rfdc_ctrl::sync_tiles)
+        .def("get_tile_latency", &rfdc_ctrl::get_tile_latency)
+        .def("get_tile_offset", &rfdc_ctrl::get_tile_offset)
+        .def("set_cal_frozen", &rfdc_ctrl::set_cal_frozen)
+        .def("get_cal_frozen", &rfdc_ctrl::get_cal_frozen)
+        .def("set_adc_cal_coefficients", &rfdc_ctrl::set_adc_cal_coefficients)
+        .def("get_adc_cal_coefficients", &rfdc_ctrl::get_adc_cal_coefficients);
+
+    py::enum_<mpm::rfdc::rfdc_ctrl::threshold_id_options>(m, "threshold_id_options")
+        .value("THRESHOLD_0", mpm::rfdc::rfdc_ctrl::THRESHOLD_0)
+        .value("THRESHOLD_1", mpm::rfdc::rfdc_ctrl::THRESHOLD_1)
+        .value("THRESHOLD_BOTH", mpm::rfdc::rfdc_ctrl::THRESHOLD_BOTH);
+
+    py::enum_<mpm::rfdc::rfdc_ctrl::threshold_mode_options>(m, "threshold_mode_options")
+        .value("TRSHD_OFF", mpm::rfdc::rfdc_ctrl::TRSHD_OFF)
+        .value("TRSHD_STICKY_OVER", mpm::rfdc::rfdc_ctrl::TRSHD_STICKY_OVER)
+        .value("TRSHD_STICKY_UNDER", mpm::rfdc::rfdc_ctrl::TRSHD_STICKY_UNDER)
+        .value("TRSHD_HYSTERESIS", mpm::rfdc::rfdc_ctrl::TRSHD_HYSTERESIS);
+
+    py::enum_<mpm::rfdc::rfdc_ctrl::threshold_clr_mode_options>(
+        m, "threshold_clr_mode_options")
+        .value("THRESHOLD_CLRMD_MANUAL", mpm::rfdc::rfdc_ctrl::THRESHOLD_CLRMD_MANUAL)
+        .value("THRESHOLD_CLRMD_AUTO", mpm::rfdc::rfdc_ctrl::THRESHOLD_CLRMD_AUTO)
+        .value("THRESHOLD_CLRMD_UNKNOWN", mpm::rfdc::rfdc_ctrl::THRESHOLD_CLRMD_UNKNOWN);
+
+    py::enum_<mpm::rfdc::rfdc_ctrl::decoder_mode_options>(m, "decoder_mode_options")
+        .value("DECODER_MAX_SNR_MODE", mpm::rfdc::rfdc_ctrl::DECODER_MAX_SNR_MODE)
+        .value("DECODER_MAX_LINEARITY_MODE",
+            mpm::rfdc::rfdc_ctrl::DECODER_MAX_LINEARITY_MODE);
+
+    py::enum_<mpm::rfdc::rfdc_ctrl::nyquist_zone_options>(m, "nyquist_zone_options")
+        .value("ODD_NYQUIST_ZONE", mpm::rfdc::rfdc_ctrl::ODD_NYQUIST_ZONE)
+        .value("EVEN_NYQUIST_ZONE", mpm::rfdc::rfdc_ctrl::EVEN_NYQUIST_ZONE);
+
+    py::enum_<mpm::rfdc::rfdc_ctrl::mixer_mode_options>(m, "mixer_mode_options")
+        .value("MIXER_MODE_OFF", mpm::rfdc::rfdc_ctrl::MIXER_MODE_OFF)
+        .value("MIXER_MODE_C2C", mpm::rfdc::rfdc_ctrl::MIXER_MODE_C2C)
+        .value("MIXER_MODE_C2R", mpm::rfdc::rfdc_ctrl::MIXER_MODE_C2R)
+        .value("MIXER_MODE_R2C", mpm::rfdc::rfdc_ctrl::MIXER_MODE_R2C)
+        .value("MIXER_MODE_R2R", mpm::rfdc::rfdc_ctrl::MIXER_MODE_R2R);
+
+    py::enum_<mpm::rfdc::rfdc_ctrl::calibration_mode_options>(
+        m, "calibration_mode_options")
+        .value("CALIB_MODE1", mpm::rfdc::rfdc_ctrl::CALIB_MODE1)
+        .value("CALIB_MODE2", mpm::rfdc::rfdc_ctrl::CALIB_MODE2);
+
+    py::enum_<mpm::rfdc::rfdc_ctrl::event_type_options>(m, "event_type_options")
+        .value("MIXER_EVENT", mpm::rfdc::rfdc_ctrl::MIXER_EVENT)
+        .value("CRSE_DLY_EVENT", mpm::rfdc::rfdc_ctrl::CRSE_DLY_EVENT)
+        .value("QMC_EVENT", mpm::rfdc::rfdc_ctrl::QMC_EVENT);
+
+    py::enum_<mpm::rfdc::rfdc_ctrl::interp_decim_options>(m, "interp_decim_options")
+        .value("INTERP_DECIM_OFF", mpm::rfdc::rfdc_ctrl::INTERP_DECIM_OFF)
+        .value("INTERP_DECIM_1X", mpm::rfdc::rfdc_ctrl::INTERP_DECIM_1X)
+        .value("INTERP_DECIM_2X", mpm::rfdc::rfdc_ctrl::INTERP_DECIM_2X)
+        .value("INTERP_DECIM_4X", mpm::rfdc::rfdc_ctrl::INTERP_DECIM_4X)
+        .value("INTERP_DECIM_8X", mpm::rfdc::rfdc_ctrl::INTERP_DECIM_8X);
+
+    py::enum_<mpm::rfdc::rfdc_ctrl::fabric_clk_div_options>(m, "fabric_clk_div_options")
+        .value("DIV_1", mpm::rfdc::rfdc_ctrl::DIV_1)
+        .value("DIV_2", mpm::rfdc::rfdc_ctrl::DIV_2)
+        .value("DIV_4", mpm::rfdc::rfdc_ctrl::DIV_4)
+        .value("DIV_8", mpm::rfdc::rfdc_ctrl::DIV_8)
+        .value("DIV_16", mpm::rfdc::rfdc_ctrl::DIV_16);
+}
+#endif
diff --git a/mpm/include/mpm/rfdc/rfdc_throw.h b/mpm/include/mpm/rfdc/rfdc_throw.h
new file mode 100755
index 000000000..20a592696
--- /dev/null
+++ b/mpm/include/mpm/rfdc/rfdc_throw.h
@@ -0,0 +1,10 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Brand
+//
+// SPDX-License-Identifier: GPL-3.0-or-later
+//
+
+/**
+ * A function to throw MPM exceptions from within the Xilinx RFdc API
+ */
+void rfdc_throw(const char* msg);
diff --git a/mpm/include/mpm/rfdc/xrfdc.h b/mpm/include/mpm/rfdc/xrfdc.h
new file mode 100644
index 000000000..ad2c06fa8
--- /dev/null
+++ b/mpm/include/mpm/rfdc/xrfdc.h
@@ -0,0 +1,2092 @@
+/******************************************************************************
+*
+* Copyright (C) 2017-2019 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xrfdc.h
+* @addtogroup rfdc_v6_0
+* @{
+* @details
+*
+* The Xilinx� LogiCORE IP Zynq UltraScale+ RFSoC RF Data Converter IP core
+* provides a configurable wrapper to allow the RF DAC and RF ADC blocks to be
+* used in IP Integrator designs. Multiple tiles are available on each RFSoC
+* and each tile can have a number of data converters (analog-to-digital (ADC)
+* and digital-to-analog (DAC)). The RF ADCs can sample input frequencies up
+* to 4 GHz at 4 GSPS with excellent noise spectral density. The RF DACs
+* generate output carrier frequencies up to 4 GHz using the 2nd Nyquist zone
+* with excellent noise spectral density at an update rate of 6.4 GSPS.
+* The RF data converters also include power efficient digital down-converters
+* (DDCs) and digital up-converters (DUCs) that include programmable interpolation
+* and decimation, NCO and complex mixer. The DDCs and DUCs can also support
+* dual-band operation.
+* A maximum of 4 tiles are available on for DAC and ADC operations each. Each
+* tile can have a maximum of 4 blocks/slices.
+* This driver provides APIs to configure various functionalities. Similarly
+* the driver provides APIs to read back configurations.
+* Some of the features that the driver supports are:
+* 1) Setting up and reading back fine mixer settings
+* 2) Setting up and reading back coarse mixer settings
+* 3) Reading back interpolation or decimation factors
+* 4) Setting up and reading back QMC settings which include gain, phase etc
+* 5) Setting up and reading back decoder mode settings
+* 6) Setting up and reading back coarse delay settings
+* All the APIs implemented in the driver provide appropriate range checks.
+* An API has been provided for debug purpose which will dump all registers
+* for a requested tile.
+* Inline functions have also been provided to read back the parameters
+* initially configured through the GUI.
+*
+* There are plans to add more features, e.g. Support for multi band, PLL
+* configurations etc.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.0   sk     05/16/17 Initial release
+* 2.0   sk     08/09/17 Fixed coarse Mixer configuration settings
+*                       CR# 977266, 977872.
+*                       Return error for Slice Event on 4G ADC Block.
+*                       Corrected Interrupt Macro names and values.
+*              08/16/17 Add support for SYSREF and PL event sources.
+*              08/18/17 Add API to enable and disable FIFO.
+*              08/23/17 Add API to configure Nyquist zone.
+*              08/30/17 Add additional info to BlockStatus.
+*              08/30/17 Add support for Coarse Mixer BYPASS mode.
+*              08/31/17 Removed Tile Reset Assert and Deassert.
+*              09/07/17 Add support for negative NCO freq.
+*              09/15/17 Fixed NCO freq precision issue.
+*              09/15/17 Fixed Immediate Event source issue and also
+*                       updated the Immediate Macro value to 0.
+* 2.1   sk     09/15/17 Remove Libmetal library dependency for MB.
+*              09/18/17 Add API to clear the interrupts.
+*       sk     09/21/17 Add __BAREMETAL__ compiler flag option
+*                       for Baremetal.
+*       sk     09/21/17 Add support for Over voltage and Over
+*                       Range interrupts.
+*       sk     09/22/17 Add s64 typedef for Linux.
+*       sk     09/24/17 Fixed Get_Tile/BlockBaseAddr always
+*                       giving ADC related address.
+*       sk     09/25/17 Modified XRFdc_GetBlockStatus API to give
+*                       correct information and also updates the
+*                       description for Vector Param in intr handler
+*                       Add API to get Output current and removed
+*                       GetTermVoltage and GetOutputCurr inline functions.
+* 2.2   sk     10/05/17 Fixed XRFdc_GetNoOfADCBlocks API for 4GSPS.
+*                       Enable the decoder clock based on decoder mode.
+*                       Add API to get the current FIFO status.
+*                       Updated XRFdc_DumpRegs API for better readability
+*                       of output register dump.
+*                       Add support for 4GSPS CoarseMixer frequency.
+*              10/11/17 Modify float types to double to increase precision.
+*              10/12/17 Update BlockStatus API to give current status.
+*                       In BYPASS mode, input datatype can be Real or IQ
+*                       hence checked both while reading the mixer mode.
+*              10/17/17 Fixed Set Threshold API Issue.
+* 2.2   sk     10/18/17 Add support for FIFO and DATA overflow interrupt
+* 2.3   sk     11/06/17 Fixed PhaseOffset truncation issue.
+*                       Provide user configurability for FineMixerScale.
+*              11/08/17 Return error for DAC R2C mode and ADC C2R mode.
+*              11/10/17 Corrected FIFO and DATA Interrupt masks.
+*              11/20/17 Fixed StartUp, Shutdown and Reset API for Tile_Id -1.
+*              11/20/17 Remove unwanted ADC block checks in 4GSPS mode.
+* 3.0   sk     12/11/17 Added DDC and DUC support.
+*              12/13/17 Add CoarseMixMode field in Mixer_Settings structure.
+*              12/15/17 Add support to switch calibration modes.
+*              12/15/17 Add support for mixer frequencies > Fs/2 and < -Fs/2.
+*       sg     13/01/18 Added PLL and external clock switch support
+*                       Added API to get PLL lock status.
+*                       Added API to get clock source.
+*       sk     01/18/18 Add API to get driver version.
+* 3.1   jm     01/24/18 Add Multi-tile sync support.
+*       sk     01/25/18 Updated Set and Get Interpolation/Decimation factor
+*                       API's to consider the actual factor value.
+* 3.2   sk     02/02/18 Add API's to configure inverse-sinc.
+*       sk     02/27/18 Add API's to configure Multiband.
+*       sk     03/09/18 Update PLL structure in XRFdc_DynamicPLLConfig API.
+*       sk     03/09/18 Update ADC and DAC datatypes in Mixer API and use
+*                       input datatype for ADC in threshold and QMC APIs.
+*       sk     03/09/18 Removed FIFO disable check in DDC and DUC APIs.
+*       sk     03/09/18 Add support for Marker event source for DAC block.
+*       jm     03/12/18 Fixed DAC latency calculation in MTS.
+*       jm     03/12/18 Added support for reloading DTC scans.
+*       jm     03/12/18 Add option to configure sysref capture after MTS.
+*       sk     03/22/18 Updated PLL settings based on latest IP values.
+* 4.0   sk     04/09/18 Added API to enable/disable the sysref.
+*       sk     04/09/18 Updated max VCO to 13108MHz to support max DAC
+*                       sample rate of 6.554MHz.
+*       rk     04/17/18 Adjust calculated latency by sysref period, where doing
+*                       so results in closer alignment to the target latency.
+*       sk     04/17/18 Corrected Set/Get MixerSettings API description for
+*                       FineMixerScale parameter.
+*       sk     04/19/18 Enable VCO Auto selection while configuring the clock.
+*       sk     04/24/18 Add API to get PLL Configurations.
+*       sk     04/24/18 Add API to get the Link Coupling mode.
+*       sk     04/28/18 Implement timeouts for PLL Lock, Startup and shutdown.
+*       sk     05/30/18 Removed CalibrationMode check for DAC.
+*       sk     06/05/18 Updated minimum Ref clock value to 102.40625MHz.
+* 5.0   sk     06/25/18 Update DAC min sampling rate to 500MHz and also update
+*                       VCO Range, PLL_DIVIDER and PLL_FPDIV ranges.
+*                       Update PLL structure with calculated sampling rate.
+*       sk     06/25/18 Add XRFdc_GetFabClkOutDiv() API to read fabric clk div.
+*                       Add Inline APIs XRFdc_CheckBlockEnabled(),
+*                       XRFdc_CheckTileEnabled().
+*       sk     07/06/18 Add support to dump HSCOM regs in XRFdc_DumpRegs() API
+*       sk     07/12/18 Fixed Multiband crossbar settings in C2C mode.
+*       sk     07/19/18 Add MixerType member to MixerSettings structure and 
+*                       Update Mixer Settings APIs to consider the MixerType
+*                       variable.
+*       sk     07/19/18 Add XRFdc_GetMultibandConfig() API to read Multiband
+*                       configuration.
+*       sk     07/20/18 Update the APIs to check the corresponding section
+*                       (Digital/Analog)enable/disable.
+*       sk     07/26/18 Fixed Doxygen, coverity warnings.
+*       sk     08/03/18 Fixed MISRAC warnings.
+*       sk     08/24/18 Move mixer related APIs to xrfdc_mixer.c file.
+*                       Define asserts for Linux, Re-arranged XRFdc_RestartIPSM,
+*                       XRFdc_CfgInitialize() and XRFdc_MultiBand()  APIs.
+*                       Reorganize the code to improve readability and
+*                       optimization.
+*       mus    08/17/18 Removed structure paddings from XRFdc_Config structure.
+*                       It has been done to have 1:1 mapping between
+*                       XRFdc_Config structure and device tree property
+*                       "param-list", over linux platform.
+*       sk     09/24/18 Update powerup-state value based on PLL mode in
+*                       XRFdc_DynamicPLLConfig() API.
+*       sk     10/10/18 Check for DigitalPath enable in XRFdc_GetNyquistZone()
+*                       and XRFdc_GetCalibrationMode() APIs for Multiband.
+*       sk     10/13/18 Add support to read the REFCLKDIV param from design.
+*                       Update XRFdc_SetPLLConfig() API to support range of
+*                       REF_CLK_DIV values(1 to 4).
+*                       Add XRFDC_MIXER_MODE_R2R option to support BYPASS mode
+*                       for Real input.
+* 5.1   cog    01/29/19 Replace structure reference ADC checks with
+*                       function.
+*       cog    01/29/19 Added XRFdc_SetDither() and XRFdc_GetDither() APIs.
+*       cog    01/29/19 Rename DataType for mixer input to MixerInputDataType
+*                       for readability.
+*       cog    01/29/19 Refactoring of interpolation and decimation APIs and
+*                       changed fabric rate for decimation X8 for non-high speed ADCs.
+*       cog    01/29/19 New inline functions to determine max & min sampling rates.
+* 6.0   cog    02/17/19 Added Inverse-Sinc Second Nyquist Zone Support
+*       cog    02/17/19 Added new clock Distribution functionality.
+*       cog    02/17/19 Refactored to improve delay balancing in clock
+*                       distribution.
+*       cog    02/17/19 Added delay calculation & metal log messages.
+*       cog    02/17/19 Added Intratile clock settings.
+*       cog    02/17/19 XRFdc_GetPLLConfig() now uses register values to get the
+*                       PLL configuration for new IPs and is no longer static.
+*       cog    02/17/19 Refactoring of interpolation and decimation APIs and
+*                       changed fabric rate for decimation X8 for non-high speed ADCs.
+*       cog    02/17/19 Added XRFdc_SetIMRPassMode() and XRFdc_SetIMRPassMode() APIs
+*       cog    02/17/19 Added XRFdc_SetDACMode() and XRFdc_GetDACMode() APIs
+*       cog    02/17/19	Added XRFdc_SetSignalDetector() and XRFdc_GetSignalDetector() APIs
+*       cog    02/17/19 Added XRFdc_DisableCoefficientsOverride(), XRFdc_SetCalCoefficients
+*                       and XRFdc_GetCalCoefficients APIs.
+*       cog    02/19/19 New definitions for clock detection.
+* 6.0   cog    02/20/19	Added handling for new ADC common mode over/under
+*                       voltage interrupts.
+*       cog    02/20/19	XRFdc_GetIntrStatus now populates a pointer with the
+*                       status and returns an error code.
+*       cog	   02/20/19	XRFdc_IntrClr, XRFdc_IntrDisable and XRFdc_IntrEnable
+*                       now return error codes.
+*       cog    02/21/19 Added XRFdc_SetCalFreeze() and XRFdc_GetCalFreeze() APIs
+*       cog    04/15/19 Rename XRFdc_SetDACMode() and XRFdc_GetDACMode() APIs to
+*                       XRFdc_SetDataPathMode() and XRFdc_GetDataPathMode() respectively.
+*
+* </pre>
+*
+******************************************************************************/
+
+
+#ifndef RFDC_H_
+#define RFDC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "rfdc_throw.h"
+#include <stdlib.h>
+#include <stdint.h>
+
+#ifdef __BAREMETAL__
+#include "xil_assert.h"
+#include "xdebug.h"
+#include "sleep.h"
+#endif
+#include <metal/sys.h>
+#include <metal/device.h>
+#include <metal/irq.h>
+#include <metal/atomic.h>
+#include <metal/io.h>
+#include <metal/sleep.h>
+#include "metal/alloc.h"
+#include "xrfdc_hw.h"
+
+/**************************** Type Definitions *******************************/
+#define XRFdc_IsADC4GSPS(InstPtr) XRFdc_IsHighSpeedADC(InstPtr, 0)
+
+#ifndef __BAREMETAL__
+typedef __u32 u32;
+typedef __u16 u16;
+typedef __u8 u8;
+typedef __s32 s32;
+typedef __u64 u64;
+typedef __s64 s64;
+typedef __s8 s8;
+#endif
+
+/**
+* The handler data type allows the user to define a callback function to
+* respond to interrupt events in the system. This function is executed
+* in interrupt context, so amount of processing should be minimized.
+*
+* @param	CallBackRef is the callback reference passed in by the upper
+*		layer when setting the callback functions, and passed back to
+*		the upper layer when the callback is invoked. Its type is
+*		not important to the driver, so it is a void pointer.
+* @param	Type indicates ADC/DAC.
+* @param	Tile_Id indicates Tile number (0-3).
+* @param	Block_Id indicates Block number (0-3).
+* @param	StatusEvent indicates one or more interrupt occurred.
+*/
+typedef void (*XRFdc_StatusHandler) (void *CallBackRef, u32 Type, u32 Tile_Id,
+				u32 Block_Id, u32 StatusEvent);
+#ifndef __BAREMETAL__
+#pragma pack(1)
+#endif
+/**
+ * PLL settings.
+ */
+typedef struct {
+	u32 Enabled;	/* PLL Enables status (not a setter) */
+	double RefClkFreq;
+	double SampleRate;
+	u32 RefClkDivider;
+	u32 FeedbackDivider;
+	u32 OutputDivider;
+	u32 FractionalMode;	/* Fractional mode is currently not supported */
+	u64 FractionalData;	/* Fractional data is currently not supported */
+	u32 FractWidth;	/* Fractional width is currently not supported */
+} XRFdc_PLL_Settings;
+/**
+* ClkIntraTile Settings.
+*/
+typedef struct {
+	u8 SourceTile;
+	u8 PLLEnable;
+	XRFdc_PLL_Settings PLLSettings;
+	u8 DivisionFactor;
+	u8 Delay;
+	u8 DistributedClock;
+} XRFdc_Tile_Clock_Settings;
+/**
+* Clk Distribution.
+*/
+typedef struct {
+	u8 Enabled;
+	u8 DistributionSource;
+	u8 UpperBound;
+	u8 LowerBound;
+	u8 MaxDelay;
+	u8 MinDelay;
+	u8 IsDelayBalanced;
+} XRFdc_Distribution;
+/**
+* Clk Distribution Settings.
+*/
+typedef struct {
+	XRFdc_Tile_Clock_Settings DAC[4];
+	XRFdc_Tile_Clock_Settings ADC[4];
+	XRFdc_Distribution DistributionStatus[8];
+} XRFdc_Distribution_Settings;
+#ifndef __BAREMETAL__
+#pragma pack()
+#endif
+
+/**
+ * ADC Signal Detect Settings.
+ */
+typedef struct {
+	u8 Mode;
+	u8 TimeConstant;
+	u8 Flush;
+	u8 EnableIntegrator;
+	u16 HighThreshold;
+	u16 LowThreshold;
+	u8  HysteresisEnable;
+}XRFdc_Signal_Detector_Settings;
+/**
+ * QMC settings.
+ */
+typedef struct {
+	u32 EnablePhase;
+	u32 EnableGain;
+	double GainCorrectionFactor;
+	double PhaseCorrectionFactor;
+	s32 OffsetCorrectionFactor;
+	u32 EventSource;
+} XRFdc_QMC_Settings;
+
+/**
+ * Coarse delay settings.
+ */
+typedef struct {
+	u32 CoarseDelay;
+	u32 EventSource;
+} XRFdc_CoarseDelay_Settings;
+
+/**
+ * Mixer settings.
+ */
+typedef struct {
+	double Freq;
+	double PhaseOffset;
+	u32 EventSource;
+	u32 CoarseMixFreq;
+	u32 MixerMode;
+	u8 FineMixerScale;	/* NCO output scale, valid values 0,1 and 2 */
+	u8 MixerType;
+} XRFdc_Mixer_Settings;
+
+/**
+ * ADC block Threshold settings.
+ */
+typedef struct {
+	u32 UpdateThreshold; /* Selects which threshold to update */
+	u32 ThresholdMode[2]; /* Entry 0 for Threshold0 and 1 for Threshold1 */
+	u32 ThresholdAvgVal[2]; /* Entry 0 for Threshold0 and 1 for Threshold1 */
+	u32 ThresholdUnderVal[2]; /* Entry 0 for Threshold0 and 1 for Threshold1 */
+	u32 ThresholdOverVal[2]; /* Entry 0 is for Threshold0 and 1 for Threshold1 */
+} XRFdc_Threshold_Settings;
+
+/**
+ * RFSoC Calibration coefficients generic struct
+ */
+typedef struct {
+	u32 Coeff0;
+	u32 Coeff1;
+	u32 Coeff2;
+	u32 Coeff3;
+	u32 Coeff4;
+	u32 Coeff5;
+	u32 Coeff6;
+	u32 Coeff7;
+} XRFdc_Calibration_Coefficients;
+
+/**
+ * RFSoC Calibration freeze settings struct
+ */
+typedef struct {
+	u32 CalFrozen; /*Status indicates calibration freeze state*/
+	u32 DisableFreezePin; /*Disable the calibration freeze pin*/
+	u32 FreezeCalibration; /*Setter for freezing*/
+} XRFdc_Cal_Freeze_Settings;
+
+/**
+ * RFSoC Tile status.
+ */
+typedef struct {
+	u32 IsEnabled;	/* 1, if tile is enabled, 0 otherwise */
+	u32 TileState;	/* Indicates Tile Current State */
+	u8 BlockStatusMask; /* Bit mask for block status, 1 indicates block enable */
+	u32 PowerUpState;
+	u32 PLLState;
+} XRFdc_TileStatus;
+
+/**
+ * RFSoC Data converter IP status.
+ */
+typedef struct {
+	XRFdc_TileStatus DACTileStatus[4];
+	XRFdc_TileStatus ADCTileStatus[4];
+	u32 State;
+} XRFdc_IPStatus;
+
+/**
+ * status of DAC or ADC blocks in the RFSoC Data converter.
+ */
+typedef struct {
+	double SamplingFreq;
+	u32 AnalogDataPathStatus;
+	u32 DigitalDataPathStatus;
+	u8 DataPathClocksStatus;	/* Indicates all required datapath
+				clocks are enabled or not, 1 if all clocks enabled, 0 otherwise */
+	u8 IsFIFOFlagsEnabled;	/* Indicates FIFO flags enabled or not,
+				 1 if all flags enabled, 0 otherwise */
+	u8 IsFIFOFlagsAsserted;	/* Indicates FIFO flags asserted or not,
+				 1 if all flags asserted, 0 otherwise */
+} XRFdc_BlockStatus;
+
+#ifndef __BAREMETAL__
+#pragma pack(1)
+#endif
+/**
+ * DAC block Analog DataPath Config settings.
+ */
+typedef struct {
+	u32 BlockAvailable;
+	u32 InvSyncEnable;
+	u32 MixMode;
+	u32 DecoderMode;
+} XRFdc_DACBlock_AnalogDataPath_Config;
+
+/**
+ * DAC block Digital DataPath Config settings.
+ */
+typedef struct {
+	u32 MixerInputDataType;
+	u32 DataWidth;
+	u32 InterpolationMode;
+	u32 FifoEnable;
+	u32 AdderEnable;
+	u32 MixerType;
+} XRFdc_DACBlock_DigitalDataPath_Config;
+
+/**
+ * ADC block Analog DataPath Config settings.
+ */
+typedef struct {
+	u32 BlockAvailable;
+	u32 MixMode;
+} XRFdc_ADCBlock_AnalogDataPath_Config;
+
+/**
+ * DAC block Digital DataPath Config settings.
+ */
+typedef struct {
+	u32 MixerInputDataType;
+	u32 DataWidth;
+	u32 DecimationMode;
+	u32 FifoEnable;
+	u32 MixerType;
+} XRFdc_ADCBlock_DigitalDataPath_Config;
+
+/**
+ * DAC Tile Config structure.
+ */
+typedef struct {
+	u32 Enable;
+	u32 PLLEnable;
+	double SamplingRate;
+	double RefClkFreq;
+	double FabClkFreq;
+	u32 FeedbackDiv;
+	u32 OutputDiv;
+	u32 RefClkDiv;
+	u32 MultibandConfig;
+	double MaxSampleRate;
+	u32 NumSlices;
+	XRFdc_DACBlock_AnalogDataPath_Config DACBlock_Analog_Config[4];
+	XRFdc_DACBlock_DigitalDataPath_Config DACBlock_Digital_Config[4];
+} XRFdc_DACTile_Config;
+
+/**
+ * ADC Tile Config Structure.
+ */
+typedef struct {
+	u32 Enable;	/* Tile Enable status */
+	u32 PLLEnable;	/* PLL enable Status */
+	double SamplingRate;
+	double RefClkFreq;
+	double FabClkFreq;
+	u32 FeedbackDiv;
+	u32 OutputDiv;
+	u32 RefClkDiv;
+	u32 MultibandConfig;
+	double MaxSampleRate;
+	u32 NumSlices;
+	XRFdc_ADCBlock_AnalogDataPath_Config ADCBlock_Analog_Config[4];
+	XRFdc_ADCBlock_DigitalDataPath_Config ADCBlock_Digital_Config[4];
+} XRFdc_ADCTile_Config;
+
+/**
+ * RFdc Config Structure.
+ */
+typedef struct {
+	u32 DeviceId;
+	metal_phys_addr_t BaseAddr;
+	u32 ADCType;	/* ADC Type 4GSPS or 2GSPS*/
+	u32 MasterADCTile;	/* ADC master Tile */
+	u32 MasterDACTile;	/* DAC Master Tile */
+	u32 ADCSysRefSource;
+	u32 DACSysRefSource;
+	u32 IPType;
+	XRFdc_DACTile_Config DACTile_Config[4];
+	XRFdc_ADCTile_Config ADCTile_Config[4];
+} XRFdc_Config;
+#ifndef __BAREMETAL__
+#pragma pack()
+#endif
+/**
+ * DAC Block Analog DataPath Structure.
+ */
+typedef struct {
+	u32 Enabled;	/* DAC Analog Data Path Enable */
+	u32 MixedMode;
+	double TerminationVoltage;
+	double OutputCurrent;
+	u32 InverseSincFilterEnable;
+	u32 DecoderMode;
+	void *FuncHandler;
+	u32 NyquistZone;
+	u8 AnalogPathEnabled;
+	u8 AnalogPathAvailable;
+	XRFdc_QMC_Settings QMC_Settings;
+	XRFdc_CoarseDelay_Settings CoarseDelay_Settings;
+} XRFdc_DACBlock_AnalogDataPath;
+
+/**
+ * DAC Block Digital DataPath Structure.
+ */
+typedef struct {
+	u32 MixerInputDataType;
+	u32 DataWidth;
+	int ConnectedIData;
+	int ConnectedQData;
+	u32 InterpolationFactor;
+	u8 DigitalPathEnabled;
+	u8 DigitalPathAvailable;
+	XRFdc_Mixer_Settings Mixer_Settings;
+} XRFdc_DACBlock_DigitalDataPath;
+
+/**
+ * ADC Block Analog DataPath Structure.
+ */
+typedef struct {
+	u32 Enabled;	/* ADC Analog Data Path Enable */
+	XRFdc_QMC_Settings QMC_Settings;
+	XRFdc_CoarseDelay_Settings CoarseDelay_Settings;
+	XRFdc_Threshold_Settings Threshold_Settings;
+	u32 NyquistZone;
+	u8 CalibrationMode;
+	u8 AnalogPathEnabled;
+	u8 AnalogPathAvailable;
+} XRFdc_ADCBlock_AnalogDataPath;
+
+/**
+ * ADC Block Digital DataPath Structure.
+ */
+typedef struct {
+	u32 MixerInputDataType;
+	u32 DataWidth;
+	u32 DecimationFactor;
+	int ConnectedIData;
+	int ConnectedQData;
+	u8 DigitalPathEnabled;
+	u8 DigitalPathAvailable;
+	XRFdc_Mixer_Settings Mixer_Settings;
+} XRFdc_ADCBlock_DigitalDataPath;
+
+/**
+ * DAC Tile Structure.
+ */
+typedef struct {
+	u32 TileBaseAddr;	/* Tile  BaseAddress*/
+	u32 NumOfDACBlocks;	/* Number of DAC block enabled */
+	XRFdc_PLL_Settings PLL_Settings;
+	u8 MultibandConfig;
+	XRFdc_DACBlock_AnalogDataPath DACBlock_Analog_Datapath[4];
+	XRFdc_DACBlock_DigitalDataPath DACBlock_Digital_Datapath[4];
+} XRFdc_DAC_Tile;
+
+/**
+ * ADC Tile Structure.
+ */
+typedef struct {
+	u32 TileBaseAddr;
+	u32 NumOfADCBlocks;	/* Number of ADC block enabled */
+	XRFdc_PLL_Settings PLL_Settings;
+	u8 MultibandConfig;
+	XRFdc_ADCBlock_AnalogDataPath ADCBlock_Analog_Datapath[4];
+	XRFdc_ADCBlock_DigitalDataPath ADCBlock_Digital_Datapath[4];
+} XRFdc_ADC_Tile;
+
+/**
+ * RFdc Structure.
+ */
+typedef struct {
+	XRFdc_Config RFdc_Config;	/* Config Structure */
+	u32 IsReady;
+	u32 ADC4GSPS;
+	metal_phys_addr_t BaseAddr;	/* BaseAddress */
+	struct metal_io_region *io;	/* Libmetal IO structure */
+	struct metal_device *device;	/* Libmetal device structure */
+	XRFdc_DAC_Tile DAC_Tile[4];
+	XRFdc_ADC_Tile ADC_Tile[4];
+	XRFdc_StatusHandler StatusHandler;	/* Event handler function */
+	void *CallBackRef;			/* Callback reference for event handler */
+	u8 UpdateMixerScale;	/* Set to 1, if user overwrite mixer scale */
+} XRFdc;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#    ifndef __BAREMETAL__
+#        define Xil_AssertNonvoid(Expression) \
+            {                                 \
+                if (!(Expression)) {          \
+                    rfdc_throw(#Expression);  \
+                }                             \
+            }
+#        define Xil_AssertVoid(Expression)   \
+            {                                \
+                if (!(Expression)) {         \
+                    rfdc_throw(#Expression); \
+                }                            \
+            }
+#        define Xil_AssertVoidAlways()       \
+            {                                \
+                rfdc_throw("Assert false"); \
+            }
+#    endif
+
+#define MAX(x,y)						(x>y)?x:y
+#define MIN(x,y)						(x<y)?x:y
+#define XRFDC_SUCCESS                     0U
+#define XRFDC_FAILURE                     1U
+#define XRFDC_COMPONENT_IS_READY     	0x11111111U
+#define XRFDC_NUM_SLICES_HSADC			2
+#define XRFDC_NUM_SLICES_LSADC			4
+#ifndef __BAREMETAL__
+#define XRFDC_PLATFORM_DEVICE_DIR		"/sys/bus/platform/devices/"
+#define XRFDC_BUS_NAME					"platform"
+#define XRFDC_SIGNATURE	"usp_rf_data_converter" /* String in RFDC node name */
+#define XRFDC_CONFIG_DATA_PROPERTY		"param-list" /* device tree property */
+#define XRFDC_COMPATIBLE_PROPERTY		"compatible" /* device tree property */
+#define XRFDC_NUM_INSTANCES_PROPERTY	"num-insts" /* device tree property */
+#define XRFDC_COMPATIBLE_STRING			"xlnx,usp-rf-data-converter-"
+#define XRFDC_DEVICE_ID_SIZE			4U
+#define XRFDC_NUM_INST_SIZE				4U
+#define XRFDC_CONFIG_DATA_SIZE			sizeof(XRFdc_Config)
+#endif
+#define XRFDC_REGION_SIZE	0x40000U
+#define XRFDC_DRP_BASE(type, tile) ((type) == XRFDC_ADC_TILE ?		\
+			XRFDC_ADC_TILE_DRP_ADDR(tile) : XRFDC_DAC_TILE_DRP_ADDR(tile))
+
+#define XRFDC_CTRL_STS_BASE(Type, Tile) ((Type) == XRFDC_ADC_TILE ?	\
+	XRFDC_ADC_TILE_CTRL_STATS_ADDR(Tile) :		\
+	XRFDC_DAC_TILE_CTRL_STATS_ADDR(Tile))
+
+#define XRFDC_BLOCK_BASE(Type, Tile, Block) ((Type) == XRFDC_ADC_TILE ?	\
+	(XRFDC_ADC_TILE_DRP_ADDR(Tile) + XRFDC_BLOCK_ADDR_OFFSET(Block)) : \
+	(XRFDC_DAC_TILE_DRP_ADDR(Tile) + XRFDC_BLOCK_ADDR_OFFSET(Block)))
+
+#define XRFDC_ADC_TILE				0U
+#define XRFDC_DAC_TILE				1U
+#define XRFDC_TILE_ID_MAX			0x3U
+#define XRFDC_BLOCK_ID_MAX			0x3U
+#define XRFDC_EVNT_SRC_IMMEDIATE	0x00000000U
+#define XRFDC_EVNT_SRC_SLICE		0x00000001U
+#define XRFDC_EVNT_SRC_TILE			0x00000002U
+#define XRFDC_EVNT_SRC_SYSREF		0x00000003U
+#define XRFDC_EVNT_SRC_MARKER		0x00000004U
+#define XRFDC_EVNT_SRC_PL			0x00000005U
+#define XRFDC_EVENT_MIXER			0x00000001U
+#define XRFDC_EVENT_CRSE_DLY		0x00000002U
+#define XRFDC_EVENT_QMC				0x00000004U
+#define XRFDC_SELECT_ALL_TILES		-1
+#define XRFDC_ADC_4GSPS				1U
+
+#define XRFDC_CRSE_DLY_MAX		0x7U
+#define XRFDC_CRSE_DLY_MAX_EXT	0x28U
+#define XRFDC_NCO_FREQ_MULTIPLIER		((0x1LLU << 48U) - 2) /* 2^48 -2 */
+#define XRFDC_NCO_FREQ_MIN_MULTIPLIER	(0x1LLU << 48U) /* 2^48 */
+#define XRFDC_NCO_PHASE_MULTIPLIER		(1U << 17U) /* 2^17 */
+#define XRFDC_QMC_PHASE_MULT			(1U << 11U) /* 2^11 */
+#define XRFDC_QMC_GAIN_MULT				(1U << 14U) /* 2^14 */
+
+#define XRFDC_DATA_TYPE_IQ			0x00000001U
+#define XRFDC_DATA_TYPE_REAL		0x00000000U
+
+#define XRFDC_TRSHD_OFF				0x0U
+#define XRFDC_TRSHD_STICKY_OVER		0x00000001U
+#define XRFDC_TRSHD_STICKY_UNDER	0x00000002U
+#define XRFDC_TRSHD_HYSTERISIS		0x00000003U
+
+/* Mixer modes */
+#define XRFDC_MIXER_MODE_OFF				0x0U
+#define XRFDC_MIXER_MODE_C2C				0x1U
+#define XRFDC_MIXER_MODE_C2R				0x2U
+#define XRFDC_MIXER_MODE_R2C				0x3U
+#define XRFDC_MIXER_MODE_R2R				0x4U
+
+#define XRFDC_I_IQ_COS_MINSIN	0x00000C00U
+#define XRFDC_Q_IQ_SIN_COS		0x00001000U
+#define XRFDC_EN_I_IQ			0x00000001U
+#define XRFDC_EN_Q_IQ			0x00000004U
+
+#define XRFDC_MIXER_TYPE_COARSE		0x1U
+#define XRFDC_MIXER_TYPE_FINE		0x2U
+
+#define XRFDC_MIXER_TYPE_OFF	0x3U
+
+#define XRFDC_COARSE_MIX_OFF						0x0U
+#define XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_TWO			0x2U
+#define XRFDC_COARSE_MIX_SAMPLE_FREQ_BY_FOUR		0x4U
+#define XRFDC_COARSE_MIX_MIN_SAMPLE_FREQ_BY_FOUR	0x8U
+#define XRFDC_COARSE_MIX_BYPASS							0x10U
+
+#define XRFDC_COARSE_MIX_MODE_C2C_C2R	0x1U
+#define XRFDC_COARSE_MIX_MODE_R2C	0x2U
+
+#define XRFDC_CRSE_MIX_OFF					0x924U
+#define XRFDC_CRSE_MIX_BYPASS				0x0U
+#define XRFDC_CRSE_4GSPS_ODD_FSBYTWO		0x492U
+#define XRFDC_CRSE_MIX_I_ODD_FSBYFOUR		0x2CBU
+#define XRFDC_CRSE_MIX_Q_ODD_FSBYFOUR		0x659U
+#define XRFDC_CRSE_MIX_I_Q_FSBYTWO			0x410U
+#define XRFDC_CRSE_MIX_I_FSBYFOUR			0x298U
+#define XRFDC_CRSE_MIX_Q_FSBYFOUR			0x688U
+#define XRFDC_CRSE_MIX_I_MINFSBYFOUR		0x688U
+#define XRFDC_CRSE_MIX_Q_MINFSBYFOUR		0x298U
+#define XRFDC_CRSE_MIX_R_I_FSBYFOUR			0x8A0U
+#define XRFDC_CRSE_MIX_R_Q_FSBYFOUR			0x70CU
+#define XRFDC_CRSE_MIX_R_I_MINFSBYFOUR		0x8A0U
+#define XRFDC_CRSE_MIX_R_Q_MINFSBYFOUR		0x31CU
+
+#define XRFDC_MIXER_SCALE_AUTO				0x0U
+#define XRFDC_MIXER_SCALE_1P0				0x1U
+#define XRFDC_MIXER_SCALE_0P7				0x2U
+
+#define XRFDC_MIXER_PHASE_OFFSET_UP_LIMIT	180
+#define XRFDC_MIXER_PHASE_OFFSET_LOW_LIMIT	(-180)
+#define XRFDC_UPDATE_THRESHOLD_0			0x1U
+#define XRFDC_UPDATE_THRESHOLD_1			0x2U
+#define XRFDC_UPDATE_THRESHOLD_BOTH			0x4U
+#define XRFDC_THRESHOLD_CLRMD_MANUAL_CLR	0x1U
+#define XRFDC_THRESHOLD_CLRMD_AUTO_CLR		0x2U
+#define XRFDC_DECODER_MAX_SNR_MODE			0x1U
+#define XRFDC_DECODER_MAX_LINEARITY_MODE	0x2U
+#define XRFDC_OUTPUT_CURRENT_32MA			32U
+#define XRFDC_OUTPUT_CURRENT_20MA			20U
+
+#define XRFDC_ADC_MIXER_MODE_IQ		0x1U
+#define XRFDC_DAC_MIXER_MODE_REAL	0x2U
+
+#define XRFDC_ODD_NYQUIST_ZONE		0x1U
+#define XRFDC_EVEN_NYQUIST_ZONE		0x2U
+
+#define XRFDC_INTERP_DECIM_OFF		0x0U
+#define XRFDC_INTERP_DECIM_1X		0x1U
+#define XRFDC_INTERP_DECIM_2X		0x2U
+#define XRFDC_INTERP_DECIM_3X		0x3U
+#define XRFDC_INTERP_DECIM_4X		0x4U
+#define XRFDC_INTERP_DECIM_5X		0x5U
+#define XRFDC_INTERP_DECIM_6X		0x6U
+#define XRFDC_INTERP_DECIM_8X		0x8U
+#define XRFDC_INTERP_DECIM_10X		0xAU
+#define XRFDC_INTERP_DECIM_12X		0xCU
+#define XRFDC_INTERP_DECIM_16X		0x10U
+#define XRFDC_INTERP_DECIM_20X		0x14U
+#define XRFDC_INTERP_DECIM_24X		0x18U
+#define XRFDC_INTERP_DECIM_40X		0x28U
+
+#define XRFDC_FAB_CLK_DIV1		0x1U
+#define XRFDC_FAB_CLK_DIV2		0x2U
+#define XRFDC_FAB_CLK_DIV4		0x3U
+#define XRFDC_FAB_CLK_DIV8		0x4U
+#define XRFDC_FAB_CLK_DIV16		0x5U
+
+#define XRFDC_CALIB_MODE1		0x1U
+#define XRFDC_CALIB_MODE2		0x2U
+#define XRFDC_TI_DCB_MODE1_4GSPS		0x00007800U
+#define XRFDC_TI_DCB_MODE1_2GSPS		0x00005000U
+
+/* PLL Configuration */
+#define XRFDC_PLL_UNLOCKED		0x1U
+#define XRFDC_PLL_LOCKED		0x2U
+
+#define XRFDC_EXTERNAL_CLK		0x0U
+#define XRFDC_INTERNAL_PLL_CLK		0x1U
+
+#define PLL_FPDIV_MIN			13U
+#define PLL_FPDIV_MAX			128U
+#define PLL_DIVIDER_MIN			2U
+#define PLL_DIVIDER_MAX			28U
+#define VCO_RANGE_MIN			8500U
+#define VCO_RANGE_MAX			13200U
+#define XRFDC_PLL_LPF1_VAL		0x6U
+#define XRFDC_PLL_CRS2_VAL		0x7008U
+#define XRFDC_VCO_UPPER_BAND	0x0U
+#define XRFDC_VCO_LOWER_BAND	0x1U
+#define XRFDC_REF_CLK_DIV_1		0x1U
+#define XRFDC_REF_CLK_DIV_2		0x2U
+#define XRFDC_REF_CLK_DIV_3		0x3U
+#define XRFDC_REF_CLK_DIV_4		0x4U
+
+#define XRFDC_SINGLEBAND_MODE		0x1U
+#define XRFDC_MULTIBAND_MODE_2X		0x2U
+#define XRFDC_MULTIBAND_MODE_4X		0x4U
+
+#define XRFDC_MB_DATATYPE_C2C		0x1U
+#define XRFDC_MB_DATATYPE_R2C		0x2U
+#define XRFDC_MB_DATATYPE_C2R		0x4U
+
+#define XRFDC_SB_C2C_BLK0	0x82U
+#define XRFDC_SB_C2C_BLK1	0x64U
+#define XRFDC_SB_C2R		0x40U
+#define XRFDC_MB_C2C_BLK0	0x5EU
+#define XRFDC_MB_C2C_BLK1	0x5DU
+#define XRFDC_MB_C2R_BLK0	0x5CU
+#define XRFDC_MB_C2R_BLK1	0x0U
+
+#define XRFDC_MIXER_MODE_BYPASS		0x2U
+
+#define XRFDC_LINK_COUPLING_DC	0x0U
+#define XRFDC_LINK_COUPLING_AC	0x1U
+
+#define XRFDC_MB_MODE_SB				0x0U
+#define XRFDC_MB_MODE_2X_BLK01			0x1U
+#define XRFDC_MB_MODE_2X_BLK23			0x2U
+#define XRFDC_MB_MODE_2X_BLK01_BLK23	0x3U
+#define XRFDC_MB_MODE_4X				0x4U
+
+#define XRFDC_MILLI		1000U
+#define XRFDC_DAC_SAMPLING_MIN	500
+#define XRFDC_DAC_SAMPLING_MAX	6554
+#define XRFDC_ADC_4G_SAMPLING_MIN	1000
+#define XRFDC_ADC_4G_SAMPLING_MAX	4116
+#define XRFDC_ADC_2G_SAMPLING_MIN	500
+#define XRFDC_ADC_2G_SAMPLING_MAX	2058
+#define XRFDC_REFFREQ_MIN	102.40625
+#define XRFDC_REFFREQ_MAX	614
+
+#define XRFDC_DIGITALPATH_ENABLE	0x1U
+#define XRFDC_ANALOGPATH_ENABLE		0x1U
+
+#define XRFDC_BLK_ID0	0x0U
+#define XRFDC_BLK_ID1	0x1U
+#define XRFDC_BLK_ID2	0x2U
+#define XRFDC_BLK_ID3	0x3U
+#define XRFDC_BLK_ID4	0x4U
+
+#define XRFDC_TILE_ID0	0x0U
+#define XRFDC_TILE_ID1	0x1U
+#define XRFDC_TILE_ID2	0x2U
+#define XRFDC_TILE_ID3	0x3U
+#define XRFDC_TILE_ID4	0x4U
+
+#define XRFDC_NUM_OF_BLKS1		0x1U
+#define XRFDC_NUM_OF_BLKS2		0x2U
+#define XRFDC_NUM_OF_BLKS3		0x3U
+#define XRFDC_NUM_OF_BLKS4		0x4U
+
+#define XRFDC_NUM_OF_TILES1		0x1U
+#define XRFDC_NUM_OF_TILES2		0x2U
+#define XRFDC_NUM_OF_TILES3		0x3U
+#define XRFDC_NUM_OF_TILES4		0x4U
+
+#define XRFDC_SM_STATE0		0x0U
+#define XRFDC_SM_STATE1		0x1U
+#define XRFDC_SM_STATE15	0xFU
+
+#define XRFDC_DECIM_4G_DATA_TYPE		0x3U
+#define XRFDC_DECIM_2G_IQ_DATA_TYPE		0x2U
+
+#define XRFDC_DAC_MAX_WR_FAB_RATE	16U
+#define XRFDC_ADC_MAX_RD_FAB_RATE	8U
+
+#define XRFDC_MIN_PHASE_CORR_FACTOR		-26.5
+#define XRFDC_MAX_PHASE_CORR_FACTOR		26.5
+#define XRFDC_MAX_GAIN_CORR_FACTOR		2.0
+#define XRFDC_MIN_GAIN_CORR_FACTOR		0.0
+
+#define XRFDC_FAB_RATE_8	8
+#define XRFDC_FAB_RATE_4	4
+#define XRFDC_FAB_RATE_2	2
+#define XRFDC_FAB_RATE_1	1
+
+#define XRFDC_HSCOM_PWR_STATS_PLL		0xFFC0U
+#define XRFDC_HSCOM_PWR_STATS_EXTERNAL	0xF240U
+
+#define XRFDC_CLK_DST_DAC0 0
+#define XRFDC_CLK_DST_DAC1 1
+#define XRFDC_CLK_DST_DAC2 2
+#define XRFDC_CLK_DST_DAC3 3
+#define XRFDC_CLK_DST_ADC0 4
+#define XRFDC_CLK_DST_ADC1 5
+#define XRFDC_CLK_DST_ADC2 6
+#define XRFDC_CLK_DST_ADC3 7
+#define XRFDC_CLK_DST_INVALID 0xFFU
+
+#define XRFDC_CLK_DISTR_MUX4A_SRC_INT	0x0008U
+#define XRFDC_CLK_DISTR_MUX4A_SRC_STH	0x0000U
+#define XRFDC_CLK_DISTR_MUX6_SRC_OFF	0x0000U
+#define XRFDC_CLK_DISTR_MUX6_SRC_INT	0x0100U
+#define XRFDC_CLK_DISTR_MUX6_SRC_NTH	0x0080U
+#define XRFDC_CLK_DISTR_MUX7_SRC_OFF	0x0000U
+#define XRFDC_CLK_DISTR_MUX7_SRC_STH	0x0200U
+#define XRFDC_CLK_DISTR_MUX7_SRC_INT	0x0400U
+#define XRFDC_CLK_DISTR_MUX8_SRC_NTH	0x0000U
+#define XRFDC_CLK_DISTR_MUX8_SRC_INT	0x8000U
+#define XRFDC_CLK_DISTR_MUX9_SRC_NTH	0x4000U
+#define XRFDC_CLK_DISTR_MUX9_SRC_INT	0x0000U
+#define XRFDC_CLK_DISTR_MUX5A_SRC_PLL	0x0800U
+#define XRFDC_CLK_DISTR_MUX5A_SRC_RX	0x0040U
+#define XRFDC_CLK_DISTR_OFF		(XRFDC_CLK_DISTR_MUX4A_SRC_INT | \
+					XRFDC_CLK_DISTR_MUX6_SRC_OFF | \
+					XRFDC_CLK_DISTR_MUX7_SRC_OFF | \
+					XRFDC_CLK_DISTR_MUX8_SRC_NTH | \
+					XRFDC_CLK_DISTR_MUX9_SRC_INT)
+#define XRFDC_CLK_DISTR_LEFTMOST_TILE		0x0000U
+#define XRFDC_CLK_DISTR_CONT_LEFT_EVEN		0x8208U
+#define  XRFDC_CLK_DISTR_CONT_LEFT_ODD		0x8200U
+#define XRFDC_CLK_DISTR_RIGHTMOST_TILE		0x4008
+#define XRFDC_CLK_DISTR_CONT_RIGHT_EVEN		0x4080
+#define XRFDC_CLK_DISTR_CONT_RIGHT_HWL_ODD	0x4088
+
+#define XRFDC_CLK_DISTR_MUX4A_SRC_CLR	0x0008U
+#define XRFDC_CLK_DISTR_MUX6_SRC_CLR	0x0180U
+#define XRFDC_CLK_DISTR_MUX7_SRC_CLR	0x0600U
+#define XRFDC_CLK_DISTR_MUX8_SRC_CLR	0x8000U
+#define XRFDC_CLK_DISTR_MUX9_SRC_CLR	0x4000U
+
+#define XRFDC_DIST_MAX 8
+
+#define XRFDC_NET_CTRL_CLK_REC_PLL			0x1U
+#define XRFDC_NET_CTRL_CLK_REC_DIST_T1		0x2U
+#define XRFDC_NET_CTRL_CLK_T1_SRC_LOCAL		0x4U
+#define XRFDC_NET_CTRL_CLK_T1_SRC_DIST		0x8U
+#define XRFDC_NET_CTRL_CLK_INPUT_DIST		0x20U
+#define XRFDC_DIST_CTRL_TO_PLL_DIV		0x10U
+#define XRFDC_DIST_CTRL_TO_T1			0x20U
+#define XRFDC_DIST_CTRL_DIST_SRC_LOCAL		0x40U
+#define XRFDC_DIST_CTRL_DIST_SRC_PLL		0x800U
+#define XRFDC_DIST_CTRL_CLK_T1_SRC_LOCAL	0x1000U
+#define XRFDC_PLLREFDIV_INPUT_OFF		0x20U
+#define XRFDC_PLLREFDIV_INPUT_DIST		0x40U
+#define XRFDC_PLLREFDIV_INPUT_FABRIC	0x60U
+#define XRFDC_PLLOPDIV_INPUT_DIST_LOCAL		0x800U
+
+#define XRFDC_TILE_SOURCE_RX 0U
+#define XRFDC_TILE_SOURCE_DIST 1U
+#define XRFDC_TILE_SOURCE_FABRIC 2U
+
+#define XRFDC_DIST_OUT_NONE 0U
+#define XRFDC_DIST_OUT_RX 1U
+#define XRFDC_DIST_OUT_OUTDIV 2U
+
+#define XRFDC_PLL_SOURCE_NONE 0U
+#define XRFDC_PLL_SOURCE_RX 1U
+#define XRFDC_PLL_SOURCE_OUTDIV 2U
+
+#define XRFDC_PLL_OUTDIV_MODE_1 0x0U
+#define XRFDC_PLL_OUTDIV_MODE_2 0x1U
+#define XRFDC_PLL_OUTDIV_MODE_3 0x2U
+#define XRFDC_PLL_OUTDIV_MODE_N 0x3U
+
+#define XRFDC_PLL_OUTDIV_MODE_3_VAL 0x1U
+
+#define XRFDC_DIVISION_FACTOR_MIN 1
+
+#define XRFDC_DITH_ENABLE 1
+#define XRFDC_DITH_DISABLE 0
+
+#define XRFDC_SIGDET_MODE_AVG  	0
+#define XRFDC_SIGDET_MODE_RNDM 	1
+#define XRFDC_SIGDET_TC_2_0		0
+#define XRFDC_SIGDET_TC_2_2		1
+#define XRFDC_SIGDET_TC_2_4		2
+#define XRFDC_SIGDET_TC_2_8		3
+#define XRFDC_SIGDET_TC_2_12	4
+#define XRFDC_SIGDET_TC_2_14	5
+#define XRFDC_SIGDET_TC_2_16	6
+#define XRFDC_SIGDET_TC_2_18	7
+
+#define XRFDC_DISABLED 0
+#define XRFDC_ENABLED 1
+
+#define XRFDC_CAL_BLOCK_OCB1 	0
+#define XRFDC_CAL_BLOCK_OCB2	1
+#define XRFDC_CAL_BLOCK_GCB		2
+#define XRFDC_CAL_BLOCK_TSCB	3
+
+#define XRFDC_INV_SYNC_MODE_MAX 2
+
+#define XRFDC_INV_SYNC_EN_MAX 1
+
+
+#define XRFDC_CTRL_MASK				0x4800
+#define XRFDC_EXPORTCTRL_CLKDIST	0x4000
+#define XRFDC_PREMIUMCTRL_CLKDIST	0x0800
+
+#define XRFDC_DAC_MODE_7G_NQ1		0U
+#define XRFDC_DAC_MODE_7G_NQ2		1U
+#define XRFDC_DAC_MODE_10G_IMR		2U
+#define XRFDC_DAC_MODE_10G_BYPASS 	3U
+#define XRFDC_DAC_MODE_MAX 			XRFDC_DAC_MODE_10G_BYPASS
+
+#define XRFDC_DAC_IMR_MODE_LOWPASS	0U
+#define XRFDC_DAC_IMR_MODE_HIGHPASS	1U
+#define XRFDC_DAC_IMR_MODE_MAX		XRFDC_DAC_IMR_MODE_HIGHPASS
+
+#define XRFDC_CLOCK_DETECT_CLK		0x1U
+#define XRFDC_CLOCK_DETECT_DIST		0x2U
+#define XRFDC_CLOCK_DETECT_BOTH		0x3U
+
+#define XRFDC_CAL_UNFREEZE_CALIB	0U
+#define XRFDC_CAL_FREEZE_CALIB		1U
+#define XRFDC_CAL_FRZ_PIN_ENABLE	0U
+#define XRFDC_CAL_FRZ_PIN_DISABLE	1U
+/*****************************************************************************/
+/**
+*
+* Execute Read modify Write
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	BaseAddr is address of a block.
+* @param	RegAddr is register offset value.
+* @param	Mask contains bit mask value.
+* @param	Data contains value to be written to register.
+*
+* @return
+*		- None
+*
+******************************************************************************/
+static inline void XRFdc_ClrSetReg(XRFdc *InstancePtr, u32 BaseAddr,
+						u32 RegAddr, u16 Mask, u16 Data)
+{
+	u16 ReadReg;
+
+	ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, RegAddr);
+	ReadReg = (ReadReg & ~Mask) | (Data & Mask);
+	XRFdc_WriteReg16(InstancePtr, BaseAddr, RegAddr, ReadReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* Execute Read and clear
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	BaseAddr is address of a block.
+* @param	RegAddr is register offset value.
+* @param	Mask contains bit mask value.
+*
+* @return
+*		- None
+*
+******************************************************************************/
+static inline void XRFdc_ClrReg(XRFdc *InstancePtr, u32 BaseAddr,
+						u32 RegAddr, u16 Mask)
+{
+	u16 ReadReg;
+
+	ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, RegAddr);
+	ReadReg &= ~Mask;
+	XRFdc_WriteReg16(InstancePtr, BaseAddr, RegAddr, ReadReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* Execute Read and mask with the value
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	BaseAddr is address of a block.
+* @param	RegAddr is register offset value.
+* @param	Mask contains bit mask value.
+*
+* @return
+*		- None
+*
+******************************************************************************/
+static inline u16 XRFdc_RDReg(XRFdc *InstancePtr, u32 BaseAddr,
+						u32 RegAddr, u16 Mask)
+{
+	u16 ReadReg;
+
+	ReadReg = XRFdc_ReadReg16(InstancePtr, BaseAddr, RegAddr);
+	ReadReg &= Mask;
+
+	return ReadReg;
+}
+
+/*****************************************************************************/
+/**
+*
+* Checks whether DAC block is available or not.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	Tile_Id Valid values are 0-3.
+* @param	Block_Id is ADC/DAC block number inside the tile. Valid values
+*			are 0-3.
+*
+* @return
+*		- Return 1 if DAC block is available, otherwise 0.
+*
+******************************************************************************/
+static inline u32 XRFdc_IsDACBlockEnabled(XRFdc *InstancePtr, u32 Tile_Id,
+												u32 Block_Id)
+{
+	return InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].
+				DACBlock_Analog_Config[Block_Id].BlockAvailable;
+}
+
+/*****************************************************************************/
+/**
+*
+* Checks whether ADC block is available or not.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	Tile_Id Valid values are 0-3.
+* @param	Block_Id is ADC/DAC block number inside the tile. Valid values
+*			are 0-3 in DAC/ADC-2GSPS and 0-1 in ADC-4GSPS.
+*
+* @return
+*		- Return 1 if ADC block is available, otherwise 0.
+*
+******************************************************************************/
+static inline u32 XRFdc_IsADCBlockEnabled(XRFdc *InstancePtr, u32 Tile_Id,
+												u32 Block_Id)
+{
+	u32 IsBlockAvail;
+
+	if (InstancePtr->RFdc_Config.ADCType == XRFDC_ADC_4GSPS) {
+		if ((Block_Id == 2U) || (Block_Id == 3U)) {
+			IsBlockAvail = 0;
+			goto RETURN_PATH;
+		}
+		if (Block_Id == 1U) {
+			Block_Id = 2U;
+		}
+	}
+	IsBlockAvail = InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id].
+				ADCBlock_Analog_Config[Block_Id].BlockAvailable;
+RETURN_PATH:
+	return IsBlockAvail;
+}
+
+/*****************************************************************************/
+/**
+*
+* Checks whether DAC Digital path is enabled or not.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	Tile_Id Valid values are 0-3.
+* @param	Block_Id is ADC/DAC block number inside the tile. Valid values
+*			are 0-3.
+*
+* @return
+*		- Return 1 if DAC digital path is enabled, otherwise 0.
+*
+******************************************************************************/
+static inline u32 XRFdc_IsDACDigitalPathEnabled(XRFdc *InstancePtr,
+				u32 Tile_Id, u32 Block_Id)
+{
+	u32 Status;
+
+	if (InstancePtr->DAC_Tile[Tile_Id].DACBlock_Digital_Datapath[Block_Id].
+				Mixer_Settings.MixerType == XRFDC_MIXER_TYPE_OFF) {
+		Status = 0U;
+	} else {
+		Status = 1U;
+	}
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Checks whether ADC digital path is enabled or not.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	Tile_Id Valid values are 0-3.
+* @param	Block_Id is ADC/DAC block number inside the tile. Valid values
+*			are 0-3 in DAC/ADC-2GSPS and 0-1 in ADC-4GSPS.
+*
+* @return
+*		- Return 1 if ADC digital path is enabled, otherwise 0.
+*
+******************************************************************************/
+static inline u32 XRFdc_IsADCDigitalPathEnabled(XRFdc *InstancePtr,
+							u32 Tile_Id, u32 Block_Id)
+{
+	u32 IsBlockAvail;
+
+	if (InstancePtr->RFdc_Config.ADCType == XRFDC_ADC_4GSPS) {
+		if ((Block_Id == 2U) || (Block_Id == 3U)) {
+			IsBlockAvail = 0;
+			goto RETURN_PATH;
+		}
+		if (Block_Id == 1U) {
+			Block_Id = 2U;
+		}
+	}
+
+	if (InstancePtr->ADC_Tile[Tile_Id].ADCBlock_Digital_Datapath[Block_Id].
+				Mixer_Settings.MixerType == XRFDC_MIXER_TYPE_OFF) {
+		IsBlockAvail = 0;
+	} else {
+		IsBlockAvail = 1;
+	}
+
+RETURN_PATH:
+	return IsBlockAvail;
+}
+
+/*****************************************************************************/
+/**
+*
+* Checks whether ADC/DAC Digital path is enabled or not.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param    Type is ADC or DAC. 0 for ADC and 1 for DAC.
+* @param	Tile_Id Valid values are 0-3.
+* @param	Block_Id is ADC/DAC block number inside the tile. Valid values
+*			are 0-3.
+*
+* @return
+*		- XRFDC_SUCCESS if Digital path is enabled.
+*       - XRFDC_FAILURE if Digital path is not enabled.
+*
+******************************************************************************/
+static inline u32 XRFdc_CheckDigitalPathEnabled(XRFdc *InstancePtr, u32 Type,
+			u32 Tile_Id, u32 Block_Id)
+{
+	u32 IsBlockAvail;
+	u32 Status;
+
+	if ((Type != XRFDC_ADC_TILE) && (Type != XRFDC_DAC_TILE)) {
+		Status = XRFDC_FAILURE;
+		goto RETURN_PATH;
+	}
+	if ((Tile_Id > XRFDC_TILE_ID_MAX) || (Block_Id > XRFDC_BLOCK_ID_MAX)) {
+		Status = XRFDC_FAILURE;
+		goto RETURN_PATH;
+	}
+	if (Type == XRFDC_ADC_TILE) {
+		IsBlockAvail = XRFdc_IsADCDigitalPathEnabled(InstancePtr, Tile_Id,
+						Block_Id);
+	} else {
+		IsBlockAvail = XRFdc_IsDACDigitalPathEnabled(InstancePtr, Tile_Id,
+						Block_Id);
+	}
+	if (IsBlockAvail == 0U) {
+		Status = XRFDC_FAILURE;
+	} else {
+		Status = XRFDC_SUCCESS;
+	}
+RETURN_PATH:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get IP BaseAddress.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+*
+* @return
+*		- Return IP BaseAddress.
+*
+******************************************************************************/
+static inline u32 XRFdc_Get_IPBaseAddr(XRFdc *InstancePtr)
+{
+	return (u32)InstancePtr->BaseAddr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get Tile BaseAddress
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	Type is ADC or DAC. 0 for ADC and 1 for DAC
+* @param	Tile_Id Valid values are 0-3.
+*
+* @return
+*		- Return Tile BaseAddress.
+*
+******************************************************************************/
+static inline u32 XRFdc_Get_TileBaseAddr(XRFdc *InstancePtr, u32 Type,
+								u32 Tile_Id)
+{
+	u32 BaseAddr;
+
+	if (Type == XRFDC_ADC_TILE) {
+		BaseAddr = InstancePtr->BaseAddr + XRFDC_ADC_TILE_DRP_ADDR(Tile_Id);
+	} else {
+		BaseAddr = InstancePtr->BaseAddr + XRFDC_DAC_TILE_DRP_ADDR(Tile_Id);
+	}
+
+	return BaseAddr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get Block BaseAddress
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	Type is ADC or DAC. 0 for ADC and 1 for DAC
+* @param	Tile_Id Valid values are 0-3.
+* @param	Block_Id is ADC/DAC block number inside the tile. Valid values
+*			are 0-3 in DAC/ADC-2GSPS and 0-1 in ADC-4GSPS.
+*
+* @return
+*		- Return Block BaseAddress.
+*
+******************************************************************************/
+static inline u32 XRFdc_Get_BlockBaseAddr(XRFdc *InstancePtr, u32 Type,
+								u32 Tile_Id, u32 Block_Id)
+{
+	u32 BaseAddr;
+
+	if (Type == XRFDC_ADC_TILE) {
+		if (InstancePtr->RFdc_Config.ADCType == XRFDC_ADC_4GSPS) {
+			if (Block_Id == 1U) {
+				Block_Id = 2U;
+			}
+		}
+		BaseAddr = InstancePtr->BaseAddr + XRFDC_ADC_TILE_DRP_ADDR(Tile_Id) +
+								XRFDC_BLOCK_ADDR_OFFSET(Block_Id);
+	} else {
+		BaseAddr = InstancePtr->BaseAddr + XRFDC_DAC_TILE_DRP_ADDR(Tile_Id) +
+								XRFDC_BLOCK_ADDR_OFFSET(Block_Id);
+	}
+
+	return BaseAddr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get Number of DAC Blocks enabled.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	Tile_Id Valid values are 0-3.
+*
+* @return
+*		- Return number of DAC blocks enabled.
+*
+******************************************************************************/
+static inline u32 XRFdc_GetNoOfDACBlock(XRFdc *InstancePtr, u32 Tile_Id)
+{
+	return InstancePtr->DAC_Tile[Tile_Id].NumOfDACBlocks;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get Number of ADC Blocks enabled.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	Tile_Id Valid values are 0-3.
+*
+* @return
+*		- Return number of ADC blocks enabled.
+*
+******************************************************************************/
+static inline u32 XRFdc_GetNoOfADCBlocks(XRFdc *InstancePtr, u32 Tile_Id)
+{
+	return InstancePtr->ADC_Tile[Tile_Id].NumOfADCBlocks;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get ADC type is High Speed or Medium Speed.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+*
+* @return
+*		- Return 1 if ADC type is 4GSPS, otherwise 0.
+*
+******************************************************************************/
+
+static inline u32 XRFdc_IsHighSpeedADC(XRFdc *InstancePtr, int Tile)
+{
+	if (InstancePtr->RFdc_Config.ADCTile_Config[Tile].NumSlices == 0) {
+		return InstancePtr->ADC4GSPS;
+	} else {
+		return (InstancePtr->RFdc_Config.ADCTile_Config[Tile].NumSlices == XRFDC_NUM_SLICES_HSADC);
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Get Mixer Input Data Type for ADC/DAC block.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	Type is ADC or DAC. 0 for ADC and 1 for DAC
+* @param	Tile_Id Valid values are 0-3.
+* @param	Block_Id is ADC/DAC block number inside the tile. Valid values
+*			are 0-3.
+*
+* @return
+*		- Return MixerInputDataType of ADC/DAC block.
+*
+******************************************************************************/
+static inline u32 XRFdc_GetDataType(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
+								u32 Block_Id)
+{
+	u32 MixerInputDataType;
+
+	if (Type == XRFDC_ADC_TILE) {
+		MixerInputDataType = InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id].
+				ADCBlock_Digital_Config[Block_Id].MixerInputDataType;
+	} else {
+		MixerInputDataType = InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].
+				DACBlock_Digital_Config[Block_Id].MixerInputDataType;
+	}
+
+	return MixerInputDataType;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get Data Width for ADC/DAC block.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	Type is ADC or DAC. 0 for ADC and 1 for DAC
+* @param	Tile_Id Valid values are 0-3.
+* @param	Block_Id is ADC/DAC block number inside the tile. Valid values
+*			are 0-3.
+*
+* @return
+*		- Return DataWidth of ADC/DAC block.
+*
+******************************************************************************/
+static inline u32 XRFdc_GetDataWidth(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
+								u32 Block_Id)
+{
+	u32 DataWidth;
+
+	if (Type == XRFDC_ADC_TILE) {
+		DataWidth = InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id].
+				ADCBlock_Digital_Config[Block_Id].DataWidth;
+	} else {
+		DataWidth = InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].
+				DACBlock_Digital_Config[Block_Id].DataWidth;
+	}
+
+	return DataWidth;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get Inversesync filter for DAC block.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	Tile_Id Valid values are 0-3.
+* @param	Block_Id is ADC/DAC block number inside the tile. Valid values
+*			are 0-3.
+*
+* @return
+*		- Return Inversesync filter for DAC block
+*
+******************************************************************************/
+static inline u32 XRFdc_GetInverseSincFilter(XRFdc *InstancePtr, u32 Tile_Id,
+								u32 Block_Id)
+{
+	return InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].
+				DACBlock_Analog_Config[Block_Id].InvSyncEnable;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get Mixed mode for DAC block.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	Tile_Id Valid values are 0-3.
+* @param	Block_Id is ADC/DAC block number inside the tile. Valid values
+*			are 0-3.
+*
+* @return
+*		- Return mixed mode for DAC block
+*
+******************************************************************************/
+static inline u32 XRFdc_GetMixedMode(XRFdc *InstancePtr, u32 Tile_Id,
+								u32 Block_Id)
+{
+	return InstancePtr->DAC_Tile[Tile_Id].
+				DACBlock_Analog_Datapath[Block_Id].MixedMode;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get Master Tile for ADC/DAC tiles.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	Type is ADC or DAC. 0 for ADC and 1 for DAC
+*
+* @return
+*		- Return Master Tile for ADC/DAC tiles
+*
+******************************************************************************/
+static inline u32 XRFdc_GetMasterTile(XRFdc *InstancePtr, u32 Type)
+{
+	u32 MasterTile;
+
+	if (Type == XRFDC_ADC_TILE) {
+		MasterTile = InstancePtr->RFdc_Config.MasterADCTile;
+	} else {
+		MasterTile = InstancePtr->RFdc_Config.MasterDACTile;
+	}
+
+	return MasterTile;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get Sysref source for ADC/DAC tile.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	Type is ADC or DAC. 0 for ADC and 1 for DAC
+*
+* @return
+*		- Return Sysref source for ADC/DAC tile
+*
+******************************************************************************/
+static inline u32 XRFdc_GetSysRefSource(XRFdc *InstancePtr, u32 Type)
+{
+	u32 SysRefSource;
+
+	if (Type == XRFDC_ADC_TILE) {
+		SysRefSource = InstancePtr->RFdc_Config.ADCSysRefSource;
+	} else {
+		SysRefSource = InstancePtr->RFdc_Config.DACSysRefSource;
+	}
+
+	return SysRefSource;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get Fabric Clock frequency.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	Type is ADC or DAC. 0 for ADC and 1 for DAC
+* @param	Tile_Id Valid values are 0-3.
+*
+* @return
+*		- Return Fabric Clock frequency for ADC/DAC tile
+*
+******************************************************************************/
+static inline double XRFdc_GetFabClkFreq(XRFdc *InstancePtr, u32 Type,
+								u32 Tile_Id)
+{
+	double FabClkFreq;
+
+	if (Type == XRFDC_ADC_TILE) {
+		FabClkFreq = InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id].FabClkFreq;
+	} else {
+		FabClkFreq = InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].FabClkFreq;
+	}
+
+	return FabClkFreq;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get whether FIFO is enabled or not.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	Type is ADC or DAC. 0 for ADC and 1 for DAC
+* @param	Tile_Id Valid values are 0-3.
+* @param	Block_Id is ADC/DAC block number inside the tile. Valid values
+*			are 0-3.
+*
+* @return
+*		- Return 1 if FIFO is enabled, otherwise 0.
+*
+******************************************************************************/
+static inline u32 XRFdc_IsFifoEnabled(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
+								u32 Block_Id)
+{
+	u32 FifoEnable;
+
+	if (Type == XRFDC_ADC_TILE) {
+		FifoEnable = InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id].
+				ADCBlock_Digital_Config[Block_Id].FifoEnable;
+	} else {
+		FifoEnable = InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].
+				DACBlock_Digital_Config[Block_Id].FifoEnable;
+	}
+
+	return FifoEnable;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get Data Converter connected for digital data path I
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	Type is ADC or DAC. 0 for ADC and 1 for DAC
+* @param	Tile_Id Valid values are 0-3.
+* @param	Block_Id is Digital Data Path number.
+*
+* @return
+*		- Return Data converter Id.
+*
+******************************************************************************/
+static inline int XRFdc_GetConnectedIData(XRFdc *InstancePtr, u32 Type,
+				 u32 Tile_Id, u32 Block_Id)
+{
+	int ConnectedIData;
+
+	if (Type == XRFDC_ADC_TILE) {
+		ConnectedIData = InstancePtr->ADC_Tile[Tile_Id].
+				ADCBlock_Digital_Datapath[Block_Id].ConnectedIData;
+	} else {
+		ConnectedIData = InstancePtr->DAC_Tile[Tile_Id].
+				DACBlock_Digital_Datapath[Block_Id].ConnectedIData;
+	}
+
+	return ConnectedIData;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get Data Converter connected for digital data path Q
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	Type is ADC or DAC. 0 for ADC and 1 for DAC
+* @param	Tile_Id Valid values are 0-3.
+* @param	Block_Id is Digital Data Path number.
+*
+* @return
+*		- Return Data converter Id.
+*
+******************************************************************************/
+static inline int XRFdc_GetConnectedQData(XRFdc *InstancePtr, u32 Type,
+				 u32 Tile_Id, u32 Block_Id)
+{
+	int ConnectedQData;
+
+	if (Type == XRFDC_ADC_TILE) {
+		ConnectedQData = InstancePtr->ADC_Tile[Tile_Id].
+				ADCBlock_Digital_Datapath[Block_Id].ConnectedQData;
+	} else {
+		ConnectedQData = InstancePtr->DAC_Tile[Tile_Id].
+				DACBlock_Digital_Datapath[Block_Id].ConnectedQData;
+	}
+
+	return ConnectedQData;
+}
+
+/*****************************************************************************/
+/**
+*
+* Set Data Converter connected for digital data path I and Q
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	Type is ADC or DAC. 0 for ADC and 1 for DAC
+* @param	Tile_Id Valid values are 0-3.
+* @param	Block_Id is Digital Data Path number.
+* @param	ConnectedIData is Converter Id to which DigitalPathI connected.
+* @param	ConnectedQData is Converter Id to which DigitalPathQ connected.
+*
+* @return
+*		- None.
+*
+******************************************************************************/
+static inline void XRFdc_SetConnectedIQData(XRFdc *InstancePtr, u32 Type,
+			u32 Tile_Id, u32 Block_Id, int ConnectedIData, int ConnectedQData)
+{
+	if (Type == XRFDC_ADC_TILE) {
+		InstancePtr->ADC_Tile[Tile_Id].
+			ADCBlock_Digital_Datapath[Block_Id].ConnectedIData = ConnectedIData;
+		InstancePtr->ADC_Tile[Tile_Id].
+			ADCBlock_Digital_Datapath[Block_Id].ConnectedQData = ConnectedQData;
+	} else {
+		InstancePtr->DAC_Tile[Tile_Id].
+			DACBlock_Digital_Datapath[Block_Id].ConnectedIData = ConnectedIData;
+		InstancePtr->DAC_Tile[Tile_Id].
+			DACBlock_Digital_Datapath[Block_Id].ConnectedQData = ConnectedQData;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Get Multiband Config data
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	Type is ADC or DAC. 0 for ADC and 1 for DAC
+* @param	Tile_Id Valid values are 0-3.
+*
+* @return
+*		- Return Multiband Configuration.
+*
+******************************************************************************/
+static inline u32 XRFdc_GetMultibandConfig(XRFdc *InstancePtr, u32 Type,
+				 u32 Tile_Id)
+{
+	u32 MultibandConfig;
+
+	if (Type == XRFDC_ADC_TILE) {
+		MultibandConfig = InstancePtr->ADC_Tile[Tile_Id].MultibandConfig;
+	} else {
+		MultibandConfig = InstancePtr->DAC_Tile[Tile_Id].MultibandConfig;
+	}
+
+	return MultibandConfig;
+}
+
+/*****************************************************************************/
+/**
+*
+* Checks whether ADC/DAC block is enabled or not.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param    Type is ADC or DAC. 0 for ADC and 1 for DAC.
+* @param	Tile_Id Valid values are 0-3.
+* @param	Block_Id is ADC/DAC block number inside the tile. Valid values
+*			are 0-3.
+*
+* @return
+*		- XRFDC_SUCCESS if block enabled.
+*       - XRFDC_FAILURE if Block not enabled.
+*
+******************************************************************************/
+static inline u32 XRFdc_CheckBlockEnabled(XRFdc *InstancePtr, u32 Type,
+			u32 Tile_Id, u32 Block_Id)
+{
+	u32 IsBlockAvail;
+	u32 Status;
+
+	if ((Type != XRFDC_ADC_TILE) && (Type != XRFDC_DAC_TILE)) {
+		Status = XRFDC_FAILURE;
+		goto RETURN_PATH;
+	}
+	if ((Tile_Id > XRFDC_TILE_ID_MAX) || (Block_Id > XRFDC_BLOCK_ID_MAX)) {
+		Status = XRFDC_FAILURE;
+		goto RETURN_PATH;
+	}
+	if (Type == XRFDC_ADC_TILE) {
+		IsBlockAvail = XRFdc_IsADCBlockEnabled(InstancePtr, Tile_Id, Block_Id);
+	} else {
+		IsBlockAvail = XRFdc_IsDACBlockEnabled(InstancePtr, Tile_Id, Block_Id);
+	}
+	if (IsBlockAvail == 0U) {
+		Status = XRFDC_FAILURE;
+	} else {
+		Status = XRFDC_SUCCESS;
+	}
+RETURN_PATH:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Checks whether ADC/DAC tile is enabled or not.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param    Type is ADC or DAC. 0 for ADC and 1 for DAC.
+* @param	Tile_Id Valid values are 0-3.
+*
+* @return
+*		- XRFDC_SUCCESS if tile enabled.
+*       - XRFDC_FAILURE if tile not enabled.
+*
+******************************************************************************/
+static inline u32 XRFdc_CheckTileEnabled(XRFdc *InstancePtr, u32 Type,
+								u32 Tile_Id)
+{
+	u32 IsTileAvail;
+	u32 Status;
+
+	if ((Type != XRFDC_ADC_TILE) && (Type != XRFDC_DAC_TILE)) {
+		Status = XRFDC_FAILURE;
+		goto RETURN_PATH;
+	}
+	if (Tile_Id > XRFDC_TILE_ID_MAX) {
+		Status = XRFDC_FAILURE;
+		goto RETURN_PATH;
+	}
+	if (Type == XRFDC_ADC_TILE) {
+		IsTileAvail = InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id].Enable;
+	} else {
+		IsTileAvail = InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].Enable;
+	}
+	if (IsTileAvail == 0U) {
+		Status = XRFDC_FAILURE;
+	} else {
+		Status = XRFDC_SUCCESS;
+	}
+RETURN_PATH:
+	return Status;
+}
+/*****************************************************************************/
+/**
+*
+* Gets ADC/DAC tile maximum sampling rate.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param    Type is ADC or DAC. 0 for ADC and 1 for DAC.
+* @param	Tile_Id Valid values are 0-3.
+* @param	MaxSampleRatePtr pointer for maximum sample rate.
+*
+* @return
+*		- XRFDC_SUCCESS if found sampling rate.
+*       - XRFDC_FAILURE if could not find sampling rate.
+*
+******************************************************************************/
+static inline u32 XRFdc_GetMaxSampleRate(XRFdc *InstancePtr, u32 Type,
+								u32 Tile_Id, double *MaxSampleRatePtr)
+{
+	u32 Status;
+
+	if ((Type != XRFDC_ADC_TILE) && (Type != XRFDC_DAC_TILE)) {
+		Status = XRFDC_FAILURE;
+		goto RETURN_PATH;
+	}
+	if (Tile_Id > XRFDC_TILE_ID_MAX) {
+		Status = XRFDC_FAILURE;
+		goto RETURN_PATH;
+	}
+	if (Type == XRFDC_ADC_TILE) {
+		*MaxSampleRatePtr = InstancePtr->RFdc_Config.ADCTile_Config[Tile_Id].MaxSampleRate*1000;
+		if (*MaxSampleRatePtr == 0) {
+			*MaxSampleRatePtr = XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id)?XRFDC_ADC_4G_SAMPLING_MAX:XRFDC_ADC_2G_SAMPLING_MAX;
+		}
+	} else {
+		*MaxSampleRatePtr = InstancePtr->RFdc_Config.DACTile_Config[Tile_Id].MaxSampleRate*1000;
+		if (*MaxSampleRatePtr == 0) {
+			*MaxSampleRatePtr = XRFDC_DAC_SAMPLING_MAX;
+		}
+	}
+	Status = XRFDC_SUCCESS;
+RETURN_PATH:
+	return Status;
+}
+/*****************************************************************************/
+/**
+*
+* Gets ADC/DAC tile minimum sampling rate.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param    Type is ADC or DAC. 0 for ADC and 1 for DAC.
+* @param	Tile_Id Valid values are 0-3.
+* @param	MinSampleRatePtr pointer for minimum sample rate.
+*
+* @return
+*		- XRFDC_SUCCESS if found sampling rate.
+*       - XRFDC_FAILURE if could not find sampling rate.
+*
+******************************************************************************/
+static inline u32 XRFdc_GetMinSampleRate(XRFdc *InstancePtr, u32 Type,
+								u32 Tile_Id, double *MinSampleRatePtr)
+{
+	u32 Status;
+
+	if ((Type != XRFDC_ADC_TILE) && (Type != XRFDC_DAC_TILE)) {
+		Status = XRFDC_FAILURE;
+		goto RETURN_PATH;
+	}
+	if (Tile_Id > XRFDC_TILE_ID_MAX) {
+		Status = XRFDC_FAILURE;
+		goto RETURN_PATH;
+	}
+	if (Type == XRFDC_ADC_TILE) {
+		*MinSampleRatePtr = XRFdc_IsHighSpeedADC(InstancePtr, Tile_Id)?XRFDC_ADC_4G_SAMPLING_MIN:XRFDC_ADC_2G_SAMPLING_MIN;
+	} else {
+		*MinSampleRatePtr = XRFDC_DAC_SAMPLING_MIN;
+	}
+	Status = XRFDC_SUCCESS;
+RETURN_PATH:
+	return Status;
+}
+/*****************************************************************************/
+/**
+*
+* This API is used to get the driver version.
+*
+* @param	None
+*
+* @return
+*		Driver version number
+*
+* @note		None
+*
+******************************************************************************/
+static inline double XRFdc_GetDriverVersion(void)
+{
+	return 6.0;
+}
+
+/************************** Function Prototypes ******************************/
+
+XRFdc_Config *XRFdc_LookupConfig(u16 DeviceId);
+u32 XRFdc_CfgInitialize(XRFdc *InstancePtr, XRFdc_Config *ConfigPtr);
+u32 XRFdc_StartUp(XRFdc *InstancePtr, u32 Type, int Tile_Id);
+u32 XRFdc_Shutdown(XRFdc *InstancePtr, u32 Type, int Tile_Id);
+u32 XRFdc_Reset(XRFdc *InstancePtr, u32 Type, int Tile_Id);
+u32 XRFdc_GetIPStatus(XRFdc *InstancePtr, XRFdc_IPStatus *IPStatusPtr);
+u32 XRFdc_GetBlockStatus(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
+				u32 Block_Id, XRFdc_BlockStatus *BlockStatusPtr);
+u32 XRFdc_SetMixerSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
+			u32 Block_Id, XRFdc_Mixer_Settings *MixerSettingsPtr);
+u32 XRFdc_GetMixerSettings(XRFdc *InstancePtr, u32 Type,
+				u32 Tile_Id, u32 Block_Id,
+				XRFdc_Mixer_Settings *MixerSettingsPtr);
+u32 XRFdc_SetQMCSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
+				u32 Block_Id, XRFdc_QMC_Settings *QMCSettingsPtr);
+u32 XRFdc_GetQMCSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
+				u32 Block_Id, XRFdc_QMC_Settings *QMCSettingsPtr);
+u32 XRFdc_GetCoarseDelaySettings(XRFdc *InstancePtr, u32 Type,
+				u32 Tile_Id, u32 Block_Id,
+				XRFdc_CoarseDelay_Settings *CoarseDelaySettingsPtr);
+u32 XRFdc_SetCoarseDelaySettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
+						u32 Block_Id, XRFdc_CoarseDelay_Settings *CoarseDelaySettingsPtr);
+u32 XRFdc_GetInterpolationFactor(XRFdc *InstancePtr, u32 Tile_Id,
+				u32 Block_Id, u32 *InterpolationFactorPtr);
+u32 XRFdc_GetDecimationFactor(XRFdc *InstancePtr, u32 Tile_Id,
+				u32 Block_Id, u32 *DecimationFactorPtr);
+u32 XRFdc_GetFabWrVldWords(XRFdc *InstancePtr, u32 Type,
+				u32 Tile_Id, u32 Block_Id, u32 *FabricDataRatePtr);
+u32 XRFdc_GetFabRdVldWords(XRFdc *InstancePtr, u32 Type,
+				u32 Tile_Id, u32 Block_Id, u32 *FabricDataRatePtr);
+u32 XRFdc_SetFabRdVldWords(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
+								u32 FabricRdVldWords);
+u32 XRFdc_SetFabWrVldWords(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
+								u32 FabricWrVldWords);
+u32 XRFdc_GetThresholdSettings(XRFdc *InstancePtr, u32 Tile_Id,
+				u32 Block_Id, XRFdc_Threshold_Settings *ThresholdSettingsPtr);
+u32 XRFdc_SetThresholdSettings(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
+				XRFdc_Threshold_Settings *ThresholdSettingsPtr);
+u32 XRFdc_SetDecoderMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
+				u32 DecoderMode);
+u32 XRFdc_UpdateEvent(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id,
+				u32 Event);
+u32 XRFdc_GetDecoderMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
+				u32 *DecoderModePtr);
+u32 XRFdc_ResetNCOPhase(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
+				u32 Block_Id);
+void XRFdc_DumpRegs(XRFdc *InstancePtr, u32 Type, int Tile_Id);
+u32 XRFdc_MultiBand(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
+		u8 DigitalDataPathMask, u32 MixerInOutDataType, u32 DataConverterMask);
+u32 XRFdc_IntrHandler(u32 Vector, void *XRFdcPtr);
+u32 XRFdc_IntrClr(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
+								u32 Block_Id, u32 IntrMask);
+u32 XRFdc_GetIntrStatus(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
+								u32 Block_Id, u32 *IntrStsPtr);
+u32 XRFdc_IntrDisable(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
+								u32 Block_Id, u32 IntrMask);
+u32 XRFdc_IntrEnable(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
+				u32 Block_Id, u32 IntrMask);
+u32 XRFdc_SetThresholdClrMode(XRFdc *InstancePtr, u32 Tile_Id,
+				u32 Block_Id, u32 ThresholdToUpdate, u32 ClrMode);
+u32 XRFdc_ThresholdStickyClear(XRFdc *InstancePtr, u32 Tile_Id,
+					u32 Block_Id, u32 ThresholdToUpdate);
+void XRFdc_SetStatusHandler(XRFdc *InstancePtr, void *CallBackRef,
+				XRFdc_StatusHandler FunctionPtr);
+u32 XRFdc_SetupFIFO(XRFdc *InstancePtr, u32 Type, int Tile_Id, u8 Enable);
+u32 XRFdc_GetFIFOStatus(XRFdc *InstancePtr, u32 Type,
+				u32 Tile_Id, u8 *EnablePtr);
+u32 XRFdc_SetNyquistZone(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
+						u32 Block_Id, u32 NyquistZone);
+u32 XRFdc_GetNyquistZone(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
+						u32 Block_Id, u32 *NyquistZonePtr);
+u32 XRFdc_GetOutputCurr(XRFdc *InstancePtr, u32 Tile_Id,
+						u32 Block_Id, u32 *OutputCurrPtr);
+u32 XRFdc_SetDecimationFactor(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
+						u32 DecimationFactor);
+u32 XRFdc_SetInterpolationFactor(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
+						u32 InterpolationFactor);
+u32 XRFdc_SetFabClkOutDiv(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
+				u16 FabClkDiv);
+u32 XRFdc_SetCalibrationMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
+				u8 CalibrationMode);
+u32 XRFdc_GetCalibrationMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
+				u8 *CalibrationModePtr);
+u32 XRFdc_GetClockSource(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
+				u32 *ClockSourcePtr);
+u32 XRFdc_GetPLLLockStatus(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
+				u32 *LockStatusPtr);
+u32 XRFdc_GetPLLConfig(XRFdc *InstancePtr, u32 Type,
+					u32 Tile_Id, XRFdc_PLL_Settings *PLLSettings);
+u32 XRFdc_DynamicPLLConfig(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
+				u8 Source, double RefClkFreq, double SamplingRate);
+u32 XRFdc_SetInvSincFIR(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u16 Mode);
+u32 XRFdc_GetInvSincFIR(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
+				u16 *ModePtr);
+u32 XRFdc_GetLinkCoupling(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
+				u32 *ModePtr);
+u32 XRFdc_GetFabClkOutDiv(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
+				u16 *FabClkDivPtr);
+u32 XRFdc_SetDither(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 Mode);
+u32 XRFdc_GetDither(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *ModePtr);
+u32 XRFdc_SetClkDistribution(XRFdc *InstancePtr, XRFdc_Distribution_Settings
+				*DistributionSettingsPtr);
+u32 XRFdc_GetClkDistribution(XRFdc *InstancePtr, XRFdc_Distribution_Settings
+				*DistributionSettingsPtr);
+u32 XRFdc_SetTileClkSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
+						XRFdc_Tile_Clock_Settings *SettingsPtr);
+u32 XRFdc_SetDataPathMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
+					u32 Mode);
+u32 XRFdc_GetDataPathMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
+				u32 *ModePtr);
+u32 XRFdc_SetIMRPassMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
+				u32 Mode);
+u32 XRFdc_GetIMRPassMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
+					u32 *ModePtr);
+u32 XRFdc_SetSignalDetector(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
+					XRFdc_Signal_Detector_Settings *SettingsPtr);
+u32 XRFdc_GetSignalDetector(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
+					XRFdc_Signal_Detector_Settings *SettingsPtr);
+u32 XRFdc_DisableCoefficientsOverride(XRFdc *InstancePtr, u32 Tile_Id, u32
+						Block_Id, u32 CalibrationBlock);
+u32 XRFdc_SetCalCoefficients(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
+					u32 CalibrationBlock, XRFdc_Calibration_Coefficients *CoeffPtr);
+u32 XRFdc_GetCalCoefficients(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
+					u32 CalibrationBlock, XRFdc_Calibration_Coefficients *CoeffPtr);
+u32 XRFdc_SetCalFreeze(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
+					XRFdc_Cal_Freeze_Settings *CalFreezePtr);
+u32 XRFdc_GetCalFreeze(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id,
+					XRFdc_Cal_Freeze_Settings *CalFreezePtr);
+#ifndef __BAREMETAL__
+s32 XRFdc_GetDeviceNameByDeviceId(char *DevNamePtr, u16 DevId);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RFDC_H_ */
+/** @} */
diff --git a/mpm/include/mpm/rfdc/xrfdc_hw.h b/mpm/include/mpm/rfdc/xrfdc_hw.h
new file mode 100644
index 000000000..f02bfdb2c
--- /dev/null
+++ b/mpm/include/mpm/rfdc/xrfdc_hw.h
@@ -0,0 +1,2410 @@
+/******************************************************************************
+*
+* Copyright (C) 2017-2019 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xrfdc_hw.h
+* @addtogroup rfdc_v6_0
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or  macros) that can be used to access the device. Other driver
+* functions are defined in xrfdc.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.0   sk     05/16/17 Initial release
+* 2.1   sk     09/15/17 Remove Libmetal library dependency for MB.
+*       sk     09/21/17 Add support for Over voltage and Over
+*                       Range interrupts.
+* 2.3   sk     11/10/17 Corrected FIFO and DATA Interrupt masks.
+* 2.4   sk     12/11/17 Added DDC and DUC support.
+* 3.0   sg     13/01/18 Added PLL and external clock switch support
+* 3.1   jm     01/24/18 Add Multi-tile sync support.
+*       sk     02/27/18 Add API's to configure Multiband.
+* 4.0   sk     04/09/18 Removed redundant inclusion of xparameters.h file.
+* 5.0   sk     08/03/18 Fixed MISRAC warnings.
+*       sk     08/24/18 Reorganize the code to improve readability and
+*                       optimization.
+* 5.1   cog    01/29/19 Added XRFdc_SetDither() and XRFdc_GetDither() APIs.
+* 6.0   cog    02/17/19 New Interp/Decimation Mask.
+*       cog    02/17/19 Added new Inverse-Sinc mask.
+*       cog    02/17/19 Added new clock Distribution Defs.
+*       cog    02/17/19 Added new intratile clock Defs.
+*       cog    02/17/19 New Masks and offsets for XRFdc_GetPLLConfig() API.
+*       cog    02/17/19 New Masks and offsets for  XRFdc_SetIMRPassMode() and
+*                       XRFdc_SetIMRPassMode() APIs
+*       cog    02/17/19 New Masks and offsets for XRFdc_SetDACMode() and
+*                       XRFdc_GetDACMode() APIs
+*       cog    02/17/19	New Masks and offsets for XRFdc_SetSignalDetector() and
+*                       XRFdc_GetSignalDetector() APIs.
+*       cog    02/17/19 New Masks and offsets for XRFdc_DisableCoefficientsOverride(),
+*                       XRFdc_SetCalCoefficients and XRFdc_GetCalCoefficients APIs.
+*       cog    02/19/19 New Masks and offsets for clock detection register.
+*       cog    02/20/19 New Masks for ADC common mode over/under voltage interrupts.
+*       cog    02/21/19 New Masks and offsets for XRFdc_SetCalFreeze() and
+*                       XRFdc_GetCalFreeze() APIs.
+*       cog    03/25/19 The new common mode over/under voltage interrupts mask
+*                       bits were clashing with other interrupt bits.
+*       cog    03/25/19 Added more calibration bypass masks.
+*
+*</pre>
+*
+******************************************************************************/
+
+#ifndef RFDC_HW_H_
+#define RFDC_HW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#ifdef __BAREMETAL__
+#include "xil_io.h"
+#endif
+#include "metal/io.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an RFDC ADC and DAC device.
+ * @{
+ */
+
+#define XRFDC_CLK_EN_OFFSET	0x000U	/**< ADC Clock Enable
+							Register */
+#define XRFDC_ADC_DEBUG_RST_OFFSET	0x004U	/**< ADC Debug Reset
+							Register */
+#define XRFDC_ADC_FABRIC_RATE_OFFSET	0x008U	/**< ADC Fabric Rate
+							Register */
+#define XRFDC_ADC_FABRIC_OFFSET	0x00CU	/**< ADC Fabric Register */
+#define XRFDC_ADC_FABRIC_ISR_OFFSET	0x010U	/**< ADC Fabric ISR
+							Register */
+#define XRFDC_DAC_FABRIC_ISR_OFFSET	0x014U	/**< DAC Fabric ISR
+							Register */
+#define XRFDC_ADC_FABRIC_IMR_OFFSET	0x014U	/**< ADC Fabric IMR
+							Register */
+#define XRFDC_DAC_FABRIC_IMR_OFFSET	0x018U	/**< DAC Fabric IMR
+							Register */
+#define XRFDC_ADC_FABRIC_DBG_OFFSET	0x018U	/**< ADC Fabric Debug
+							Register */
+#define XRFDC_ADC_UPDATE_DYN_OFFSET	0x01CU	/**< ADC Update Dynamic
+							Register */
+#define XRFDC_DAC_UPDATE_DYN_OFFSET	0x020U	/**< DAC Update Dynamic
+							Register */
+#define XRFDC_ADC_FIFO_LTNC_CRL_OFFSET	0x020U	/**< ADC FIFO Latency
+							Control Register */
+#define XRFDC_ADC_DEC_ISR_OFFSET	0x030U	/**< ADC Decoder interface
+							ISR Register */
+#define XRFDC_DAC_DATAPATH_OFFSET	0x034U	/**< ADC Decoder interface
+							IMR Register */
+#define XRFDC_ADC_DEC_IMR_OFFSET	0x034U	/**< ADC Decoder interface
+							IMR Register */
+#define XRFDC_DATPATH_ISR_OFFSET	0x038U	/**< ADC Data Path
+							ISR Register */
+#define XRFDC_DATPATH_IMR_OFFSET	0x03CU	/**< ADC Data Path
+							IMR Register */
+#define XRFDC_ADC_DECI_CONFIG_OFFSET	0x040U	/**< ADC Decimation
+							Config Register */
+#define XRFDC_DAC_INTERP_CTRL_OFFSET	0x040U	/**< DAC Interpolation
+							Control Register */
+#define XRFDC_ADC_DECI_MODE_OFFSET	0x044U	/**< ADC Decimation mode
+							Register */
+#define XRFDC_DAC_ITERP_DATA_OFFSET	0x044U	/**< DAC interpolation data */
+#define XRFDC_ADC_MXR_CFG0_OFFSET	0x080U	/**< ADC I channel mixer
+							config Register */
+#define XRFDC_ADC_MXR_CFG1_OFFSET	0x084U	/**< ADC Q channel mixer
+							config Register */
+#define XRFDC_MXR_MODE_OFFSET		0x088U	/**< ADC/DAC mixer mode
+							Register */
+#define XRFDC_NCO_UPDT_OFFSET	0x08CU	/**< ADC/DAC NCO Update
+							mode Register */
+#define XRFDC_NCO_RST_OFFSET	0x090U	/**< ADC/DAC NCO Phase
+							Reset Register */
+#define XRFDC_ADC_NCO_FQWD_UPP_OFFSET	0x094U	/**< ADC NCO Frequency
+							Word[47:32] Register */
+#define XRFDC_ADC_NCO_FQWD_MID_OFFSET	0x098U	/**< ADC NCO Frequency
+							Word[31:16] Register */
+#define XRFDC_ADC_NCO_FQWD_LOW_OFFSET	0x09CU	/**< ADC NCO Frequency
+							Word[15:0] Register */
+#define XRFDC_NCO_PHASE_UPP_OFFSET	0x0A0U	/**< ADC/DAC NCO Phase[17:16]
+							Register */
+#define XRFDC_NCO_PHASE_LOW_OFFSET	0x0A4U	/**< ADC/DAC NCO Phase[15:0]
+							Register */
+#define XRFDC_ADC_NCO_PHASE_MOD_OFFSET	0x0A8U	/**< ADC NCO Phase
+							Mode Register */
+#define XRFDC_QMC_UPDT_OFFSET	0x0C8U	/**< ADC/DAC QMC Update Mode
+							Register */
+#define XRFDC_QMC_CFG_OFFSET	0x0CCU	/**< ADC/DAC QMC Config
+							Register */
+#define XRFDC_QMC_OFF_OFFSET	0x0D0U	/**< ADC/DAC QMC Offset
+							Correction Register */
+#define XRFDC_QMC_GAIN_OFFSET	0x0D4U	/**< ADC/DAC QMC Gain
+							Correction Register */
+#define XRFDC_QMC_PHASE_OFFSET	0x0D8U	/**< ADC/DAC QMC Phase
+							Correction Register */
+#define XRFDC_ADC_CRSE_DLY_UPDT_OFFSET	0x0DCU	/**< ADC Coarse Delay
+							Update Register */
+#define XRFDC_DAC_CRSE_DLY_UPDT_OFFSET	0x0E0U	/**< DAC Coarse Delay
+							Update Register */
+#define XRFDC_ADC_CRSE_DLY_CFG_OFFSET	0x0E0U	/**< ADC Coarse delay
+							Config Register */
+#define XRFDC_DAC_CRSE_DLY_CFG_OFFSET	0x0DCU	/**< DAC Coarse delay
+							Config Register */
+#define XRFDC_ADC_DAT_SCAL_CFG_OFFSET	0x0E4U	/**< ADC Data Scaling
+							Config Register */
+#define XRFDC_ADC_SWITCH_MATRX_OFFSET	0x0E8U	/**< ADC Switch Matrix
+							Config Register */
+#define XRFDC_ADC_TRSHD0_CFG_OFFSET		0x0ECU	/**< ADC Threshold0
+							Config Register */
+#define XRFDC_ADC_TRSHD0_AVG_UP_OFFSET	0x0F0U	/**< ADC Threshold0
+							Average[31:16] Register */
+#define XRFDC_ADC_TRSHD0_AVG_LO_OFFSET	0x0F4U	/**< ADC Threshold0
+							Average[15:0] Register */
+#define XRFDC_ADC_TRSHD0_UNDER_OFFSET	0x0F8U	/**< ADC Threshold0
+							Under Threshold Register */
+#define XRFDC_ADC_TRSHD0_OVER_OFFSET	0x0FCU	/**< ADC Threshold0
+							Over Threshold Register */
+#define XRFDC_ADC_TRSHD1_CFG_OFFSET	0x100U	/**< ADC Threshold1
+							Config Register */
+#define XRFDC_ADC_TRSHD1_AVG_UP_OFFSET	0x104U	/**< ADC Threshold1
+							Average[31:16] Register */
+#define XRFDC_ADC_TRSHD1_AVG_LO_OFFSET	0x108U	/**< ADC Threshold1
+							Average[15:0] Register */
+#define XRFDC_ADC_TRSHD1_UNDER_OFFSET	0x10CU	/**< ADC Threshold1
+							Under Threshold Register */
+#define XRFDC_ADC_TRSHD1_OVER_OFFSET	0x110U	/**< ADC Threshold1
+							Over Threshold Register */
+#define XRFDC_ADC_FEND_DAT_CRL_OFFSET	0x140U	/**< ADC Front end
+							Data Control Register */
+#define XRFDC_ADC_TI_DCB_CRL0_OFFSET	0x144U	/**< ADC Time Interleaved
+							digital correction block gain control0 Register */
+#define XRFDC_ADC_TI_DCB_CRL1_OFFSET	0x148U	/**< ADC Time Interleaved
+							digital correction block gain control1 Register */
+#define XRFDC_ADC_TI_DCB_CRL2_OFFSET	0x14CU	/**< ADC Time Interleaved
+							digital correction block gain control2 Register */
+#define XRFDC_ADC_TI_DCB_CRL3_OFFSET	0x150U	/**< ADC Time Interleaved
+							digital correction block gain control3 Register */
+#define XRFDC_ADC_TI_TISK_CRL0_OFFSET	0x154U	/**< ADC Time skew correction
+							control bits0 Register */
+#define XRFDC_DAC_MC_CFG0_OFFSET		0x1C4U	/**< Static Configuration
+							 data for DAC Analog */
+#define XRFDC_ADC_TI_TISK_CRL1_OFFSET	0x158U	/**< ADC Time skew correction
+							control bits1 Register */
+#define XRFDC_ADC_TI_TISK_CRL2_OFFSET	0x15CU	/**< ADC Time skew correction
+							control bits2 Register */
+#define XRFDC_ADC_TI_TISK_CRL3_OFFSET	0x160U	/**< ADC Time skew correction
+							control bits3 Register */
+#define XRFDC_ADC_TI_TISK_CRL4_OFFSET	0x164U	/**< ADC Time skew correction
+							control bits4 Register */
+#define XRFDC_ADC_TI_TISK_DAC0_OFFSET	0x168U	/**< ADC Time skew DAC
+							cal code of subadc ch0 Register */
+#define XRFDC_ADC_TI_TISK_DAC1_OFFSET	0x16CU	/**< ADC Time skew DAC
+							cal code of subadc ch1 Register */
+#define XRFDC_ADC_TI_TISK_DAC2_OFFSET	0x170U	/**< ADC Time skew DAC
+							cal code of subadc ch2 Register */
+#define XRFDC_ADC_TI_TISK_DAC3_OFFSET	0x174U	/**< ADC Time skew DAC
+							cal code of subadc ch3 Register */
+#define XRFDC_ADC_TI_TISK_DACP0_OFFSET	0x178U	/**< ADC Time skew DAC
+							cal code of subadc ch0 Register */
+#define XRFDC_ADC_TI_TISK_DACP1_OFFSET	0x17CU	/**< ADC Time skew DAC
+							cal code of subadc ch1 Register */
+#define XRFDC_ADC_TI_TISK_DACP2_OFFSET	0x180U	/**< ADC Time skew DAC
+							cal code of subadc ch2 Register */
+#define XRFDC_ADC_TI_TISK_DACP3_OFFSET	0x184U	/**< ADC Time skew DAC
+							cal code of subadc ch3 Register */
+#define XRFDC_ADC0_SUBDRP_ADDR_OFFSET	0x198U	/**< subadc0, sub-drp address
+							of target Register */
+#define XRFDC_ADC0_SUBDRP_DAT_OFFSET	0x19CU	/**< subadc0, sub-drp data
+							of target Register */
+#define XRFDC_ADC1_SUBDRP_ADDR_OFFSET	0x1A0U	/**< subadc1, sub-drp address
+							of target Register */
+#define XRFDC_ADC1_SUBDRP_DAT_OFFSET	0x1A4U	/**< subadc1, sub-drp data
+							of target Register */
+#define XRFDC_ADC2_SUBDRP_ADDR_OFFSET	0x1A8U	/**< subadc2, sub-drp address
+							of target Register */
+#define XRFDC_ADC2_SUBDRP_DAT_OFFSET	0x1ACU	/**< subadc2, sub-drp data
+							of target Register */
+#define XRFDC_ADC3_SUBDRP_ADDR_OFFSET	0x1B0U	/**< subadc3, sub-drp address
+							of target Register */
+#define XRFDC_ADC3_SUBDRP_DAT_OFFSET	0x1B4U	/**< subadc3, sub-drp data
+							of target Register */
+#define XRFDC_ADC_RX_MC_PWRDWN_OFFSET	0x1C0U	/**< ADC Static configuration
+							bits for ADC(RX) analog Register */
+#define XRFDC_ADC_DAC_MC_CFG0_OFFSET		0x1C4U	/**< ADC/DAC Static
+							configuration bits for ADC/DAC analog Register */
+#define XRFDC_ADC_DAC_MC_CFG1_OFFSET		0x1C8U	/**< ADC/DAC Static
+							configuration bits for ADC/DAC analog Register */
+#define XRFDC_ADC_DAC_MC_CFG2_OFFSET		0x1CCU	/**< ADC/DAC Static
+							configuration bits for ADC/DAC analog Register */
+#define XRFDC_DAC_MC_CFG3_OFFSET		0x1D0U	/**< DAC Static
+							configuration bits for DAC analog Register */
+#define XRFDC_ADC_RXPR_MC_CFG0_OFFSET	0x1D0U	/**< ADC RX Pair static
+							Configuration Register */
+#define XRFDC_ADC_RXPR_MC_CFG1_OFFSET	0x1D4U	/**< ADC RX Pair static
+							Configuration Register */
+#define XRFDC_ADC_TI_DCBSTS0_BG_OFFSET	0x200U	/**< ADC DCB Status0
+							BG Register */
+#define XRFDC_ADC_TI_DCBSTS0_FG_OFFSET	0x204U	/**< ADC DCB Status0
+							FG Register */
+#define XRFDC_ADC_TI_DCBSTS1_BG_OFFSET	0x208U	/**< ADC DCB Status1
+							BG Register */
+#define XRFDC_ADC_TI_DCBSTS1_FG_OFFSET	0x20CU	/**< ADC DCB Status1
+							FG Register */
+#define XRFDC_ADC_TI_DCBSTS2_BG_OFFSET	0x210U	/**< ADC DCB Status2
+							BG Register */
+#define XRFDC_ADC_TI_DCBSTS2_FG_OFFSET	0x214U	/**< ADC DCB Status2
+							FG Register */
+#define XRFDC_ADC_TI_DCBSTS3_BG_OFFSET	0x218U	/**< ADC DCB Status3
+							BG Register */
+#define XRFDC_ADC_TI_DCBSTS3_FG_OFFSET	0x21CU	/**< ADC DCB Status3
+							FG Register */
+#define XRFDC_ADC_TI_DCBSTS4_MB_OFFSET	0x220U	/**< ADC DCB Status4
+							MSB Register */
+#define XRFDC_ADC_TI_DCBSTS4_LB_OFFSET	0x224U	/**< ADC DCB Status4
+							LSB Register */
+#define XRFDC_ADC_TI_DCBSTS5_MB_OFFSET	0x228U	/**< ADC DCB Status5
+							MSB Register */
+#define XRFDC_ADC_TI_DCBSTS5_LB_OFFSET	0x22CU	/**< ADC DCB Status5
+							LSB Register */
+#define XRFDC_ADC_TI_DCBSTS6_MB_OFFSET	0x230U	/**< ADC DCB Status6
+							MSB Register */
+#define XRFDC_ADC_TI_DCBSTS6_LB_OFFSET	0x234U	/**< ADC DCB Status6
+							LSB Register */
+#define XRFDC_ADC_TI_DCBSTS7_MB_OFFSET	0x238U	/**< ADC DCB Status7
+							MSB Register */
+#define XRFDC_ADC_TI_DCBSTS7_LB_OFFSET	0x23CU	/**< ADC DCB Status7
+							LSB Register */
+#define XRFDC_ADC_FIFO_LTNCY_LB_OFFSET	0x280U	/**< ADC FIFO Latency
+							measurement LSB Register */
+#define XRFDC_ADC_FIFO_LTNCY_MB_OFFSET	0x284U	/**< ADC FIFO Latency
+							measurement MSB Register */
+#define XRFDC_DAC_DECODER_CTRL_OFFSET	0x180U	/**< DAC Unary Decoder/
+							Randomizer settings */
+#define XRFDC_DAC_DECODER_CLK_OFFSET	0x184U	/**< Decoder Clock enable */
+
+#define XRFDC_ADC_SIG_DETECT_CTRL_OFFSET				0x114 /**< ADC Signal Detector Control */
+#define XRFDC_ADC_SIG_DETECT_THRESHOLD0_LEVEL_OFFSET	0x118 /**< ADC Signal Detector Theshold 0 */
+#define XRFDC_ADC_SIG_DETECT_THRESHOLD0_CNT_ON_OFFSET	0x11C /**< ADC Signal Detector Theshold 0 on Counter */
+#define XRFDC_ADC_SIG_DETECT_THRESHOLD0_CNT_OFF_OFFSET	0x120 /**< ADC Signal Detector Theshold 0 off Counter */
+#define XRFDC_ADC_SIG_DETECT_THRESHOLD1_LEVEL_OFFSET	0x124 /**< ADC Signal Detector Theshold 1 */
+#define XRFDC_ADC_SIG_DETECT_THRESHOLD1_CNT_ON_OFFSET	0x128 /**< ADC Signal Detector Theshold 1 on Counter */
+#define XRFDC_ADC_SIG_DETECT_THRESHOLD1_CNT_OFF_OFFSET	0x12C /**< ADC Signal Detector Theshold 1 off Counter */
+#define XRFDC_ADC_SIG_DETECT_MAGN_OFFSET				0x130 /**< ADC Signal Detector Magintude */
+
+
+#define XRFDC_HSCOM_CLK_DSTR_OFFSET	0x088U	/**< Clock Distribution Register*/
+#define XRFDC_HSCOM_CLK_DSTR_MASK	0xC788U	/**< Clock Distribution Register*/
+#define XRFDC_HSCOM_CLK_DSTR_MASK_ALT	0x1870U	/**< Clock Distribution Register
+							for Intratile*/
+#define XRFDC_HSCOM_PWR_OFFSET		0x094	/**< Control register during
+							power-up sequence */
+#define XRFDC_HSCOM_CLK_DIV_OFFSET	0xB0	/**< Fabric clk out divider */
+#define XRFDC_HSCOM_PWR_STATE_OFFSET	0xB4	/**< Check powerup state */
+#define XRFDC_HSCOM_UPDT_DYN_OFFSET		0x0B8	/**< Trigger the update
+							dynamic event */
+#define XRFDC_HSCOM_EFUSE_2_OFFSET	0x144
+#define XRFDC_DAC_INVSINC_OFFSET	0x0C0U	/**< Invsinc control */
+#define XRFDC_DAC_MB_CFG_OFFSET		0x0C4U	/**< Multiband config */
+#define XRFDC_MTS_SRDIST			0x1CA0U
+#define XRFDC_MTS_SRCAP_T1			(0x24U << 2U)
+#define XRFDC_MTS_SRCAP_PLL			(0x0CU << 2U)
+#define XRFDC_MTS_SRCAP_DIG			(0x2CU << 2U)
+#define XRFDC_MTS_SRDTC_T1			(0x27U << 2U)
+#define XRFDC_MTS_SRDTC_PLL			(0x26U << 2U)
+#define XRFDC_MTS_SRFLAG			(0x49U << 2U)
+#define XRFDC_MTS_CLKSTAT			(0x24U << 2U)
+#define XRFDC_MTS_SRCOUNT_CTRL		0x004CU
+#define XRFDC_MTS_SRCOUNT_VAL		0x0050U
+#define XRFDC_MTS_SRFREQ_VAL		0x0054U
+#define XRFDC_MTS_FIFO_CTRL_ADC		0x0010U
+#define XRFDC_MTS_FIFO_CTRL_DAC		0x0014U
+#define XRFDC_MTS_DELAY_CTRL		0x0028U
+#define XRFDC_MTS_ADC_MARKER		0x0018U
+#define XRFDC_MTS_ADC_MARKER_CNT	0x0010U
+#define XRFDC_MTS_DAC_MARKER_CTRL	0x0048U
+#define XRFDC_MTS_DAC_MARKER_CNT	(0x92U << 2U)
+#define XRFDC_MTS_DAC_MARKER_LOC	(0x93U << 2U)
+
+#define XRFDC_RESET_OFFSET				0x00U	/**< Tile reset register */
+#define XRFDC_RESTART_OFFSET			0x04U	/**< Tile restart register */
+#define XRFDC_RESTART_STATE_OFFSET		0x08U	/**< Tile restart state register */
+#define XRFDC_CURRENT_STATE_OFFSET		0x0CU	/**< Current state register */
+#define XRFDC_CLOCK_DETECT_OFFSET		0x80U	/**< Clock detect register */
+#define XRFDC_STATUS_OFFSET				0x228U	/**< Common status register */
+#define XRFDC_COMMON_INTR_STS			0x100U	/**< Common Intr Status register */
+#define XRFDC_COMMON_INTR_ENABLE		0x104U	/**< Common Intr enable register */
+#define XRFDC_INTR_STS					0x200U	/**< Intr status register */
+#define XRFDC_INTR_ENABLE				0x204U	/**< Intr enable register */
+#define XRFDC_CONV_INTR_STS(X)			(0x208U + (X * 0x08U))
+#define XRFDC_CONV_INTR_EN(X)			(0x20CU + (X * 0x08U))
+#define XRFDC_CONV_CAL_STGS(X)			(0x234U + (X * 0x04U))
+#define XRFDC_CAL_GCB_COEFF0_FAB(X)		(0x280U + (X * 0x10U))
+#define XRFDC_CAL_GCB_COEFF1_FAB(X)		(0x284U + (X * 0x10U))
+#define XRFDC_CAL_GCB_COEFF2_FAB(X)		(0x288U + (X * 0x10U))
+#define XRFDC_CAL_GCB_COEFF3_FAB(X)		(0x28CU + (X * 0x10U))
+#define XRFDC_PLL_FREQ					0x300U	/**< PLL output frequency (before divider) register */
+#define XRFDC_PLL_FS					0x304U	/**< Sampling rate register */
+#define XRFDC_FIFO_ENABLE				0x230U	/**< FIFO Enable and Disable */
+#define XRFDC_PLL_SDM_CFG0				0x00U	/**< PLL Configuration bits for sdm */
+#define XRFDC_PLL_SDM_SEED0				0x18U	/**< PLL Bits for sdm LSB */
+#define XRFDC_PLL_SDM_SEED1				0x1CU 	/**< PLL Bits for sdm MSB */
+#define XRFDC_PLL_VREG					0x44U	/**< PLL bits for voltage regulator */
+#define XRFDC_PLL_VCO0					0x54U 	/**< PLL bits for coltage controlled oscillator LSB */
+#define XRFDC_PLL_VCO1					0x58U	/**< PLL bits for coltage controlled oscillator MSB */
+#define XRFDC_PLL_CRS1					0x28U 	/**< PLL bits for coarse frequency control LSB */
+#define XRFDC_PLL_CRS2					0x2CU	/**< PLL bits for coarse frequency control MSB */
+#define XRFDC_PLL_DIVIDER0        		0x30U   /**< PLL Output Divider LSB register */
+#define XRFDC_PLL_DIVIDER1         		0x34U   /**< PLL Output Divider MSB register */
+#define XRFDC_PLL_SPARE0				0x38U	/**< PLL spare inputs LSB */
+#define XRFDC_PLL_SPARE1				0x3CU	/**< PLL spare inputs MSB */
+#define XRFDC_PLL_REFDIV           		0x40U   /**< PLL Reference Divider register */
+#define XRFDC_PLL_VREG             		0x44U   /**< PLL voltage regulator */
+#define XRFDC_PLL_CHARGEPUMP			0x48U	/**< PLL bits for charge pumps */
+#define XRFDC_PLL_LPF0					0x4CU	/**< PLL bits for loop filters LSB */
+#define XRFDC_PLL_LPF1					0x50U	/**< PLL bits for loop filters MSB */
+#define XRFDC_PLL_FPDIV           		0x5CU   /**< PLL Feedback Divider register */
+#define XRFDC_CLK_NETWORK_CTRL0			0x8CU	/**< Clock network control and trim register */
+#define XRFDC_CLK_NETWORK_CTRL1			0x90U	/**< Multi-tile sync and clock source control register */
+
+#define XRFDC_HSCOM_NETWORK_CTRL1_MASK	0x02FU	/**< Clock Network Register Mask for IntraTile*/
+#define XRFDC_PLL_REFDIV_MASK          	0x0E0U  /**< PLL Reference Divider Register Mask for IntraTile */
+#define XRFDC_PLL_DIVIDER0_ALT_MASK     0x800U  /**< PLL Output Divider Register Mask for IntraTile */
+
+#define XRFDC_CAL_OCB1_OFFSET_COEFF0		0x200	/**< Foreground offset correction block */
+#define XRFDC_CAL_OCB1_OFFSET_COEFF1		0x208  	/**< Foreground offset correction block */
+#define XRFDC_CAL_OCB1_OFFSET_COEFF2		0x210  	/**< Foreground offset correction block */
+#define XRFDC_CAL_OCB1_OFFSET_COEFF3		0x218	/**< Foreground offset correction block */
+#define XRFDC_CAL_OCB2_OFFSET_COEFF0		0x204	/**< Background offset correction block */
+#define XRFDC_CAL_OCB2_OFFSET_COEFF1		0x20C	/**< Background offset correction block */
+#define XRFDC_CAL_OCB2_OFFSET_COEFF2		0x214	/**< Background offset correction block */
+#define XRFDC_CAL_OCB2_OFFSET_COEFF3		0x21C	/**< Background offset correction block */
+#define XRFDC_CAL_GCB_OFFSET_COEFF0			0x220	/**< Background gain correction block */
+#define XRFDC_CAL_GCB_OFFSET_COEFF1			0x224	/**< Background gain correction block */
+#define XRFDC_CAL_GCB_OFFSET_COEFF2			0x228	/**< Background gain correction block */
+#define XRFDC_CAL_GCB_OFFSET_COEFF3			0x22C	/**< Background gain correction block */
+#define XRFDC_CAL_GCB_OFFSET_COEFF0_ALT		0x220	/**< Background gain correction block (below Gen 3) */
+#define XRFDC_CAL_GCB_OFFSET_COEFF1_ALT		0x228	/**< Background gain correction block (below Gen 3) */
+#define XRFDC_CAL_GCB_OFFSET_COEFF2_ALT		0x230	/**< Background gain correction block (below Gen 3) */
+#define XRFDC_CAL_GCB_OFFSET_COEFF3_ALT		0x238	/**< Background gain correction block (below Gen 3) */
+#define XRFDC_CAL_TSCB_OFFSET_COEFF0		0x170	/**< Background time skew correction block */
+#define XRFDC_CAL_TSCB_OFFSET_COEFF1		0x174	/**< Background time skew correction block */
+#define XRFDC_CAL_TSCB_OFFSET_COEFF2		0x178	/**< Background time skew correction block */
+#define XRFDC_CAL_TSCB_OFFSET_COEFF3		0x17C	/**< Background time skew correction block */
+#define XRFDC_CAL_TSCB_OFFSET_COEFF4		0x180	/**< Background time skew correction block */
+#define XRFDC_CAL_TSCB_OFFSET_COEFF5		0x184	/**< Background time skew correction block */
+#define XRFDC_CAL_TSCB_OFFSET_COEFF6		0x188	/**< Background time skew correction block */
+#define XRFDC_CAL_TSCB_OFFSET_COEFF7		0x18C	/**< Background time skew correction block */
+#define XRFDC_CAL_TSCB_OFFSET_COEFF0_ALT	0x168	/**< Background time skew correction block (below Gen 3) */
+#define XRFDC_CAL_TSCB_OFFSET_COEFF1_ALT	0x16C	/**< Background time skew correction block (below Gen 3) */
+#define XRFDC_CAL_TSCB_OFFSET_COEFF2_ALT	0x170	/**< Background time skew correction block (below Gen 3) */
+#define XRFDC_CAL_TSCB_OFFSET_COEFF3_ALT	0x174	/**< Background time skew correction block (below Gen 3) */
+#define XRFDC_CAL_TSCB_OFFSET_COEFF4_ALT	0x178	/**< Background time skew correction block (below Gen 3) */
+#define XRFDC_CAL_TSCB_OFFSET_COEFF5_ALT	0x17C	/**< Background time skew correction block (below Gen 3) */
+#define XRFDC_CAL_TSCB_OFFSET_COEFF6_ALT	0x180	/**< Background time skew correction block (below Gen 3) */
+#define XRFDC_CAL_TSCB_OFFSET_COEFF7_ALT	0x184	/**< Background time skew correction block (below Gen 3) */
+
+
+/* @} */
+
+/** @name Calibration Coefficients - Calibration coefficients and disable registers
+ *
+ * This register contains bits for calibration coefficients
+ * for ADC.
+ * @{
+ */
+
+#define XRFDC_CAL_OCB_MASK		0xFFFFU /**< offsets coeff mask*/
+#define XRFDC_CAL_GCB_MASK		0x0FFFU /**< gain coeff mask*/
+#define XRFDC_CAL_GCB_FAB_MASK	0xFFF0U /**< gain coeff mask for IP Gen 2 or below*/
+#define XRFDC_CAL_TSCB_MASK		0x01FFU /**< time skew coeff mask*/
+
+#define XRFDC_CAL_GCB_FLSH_MASK	0x1000U	/**< GCB accumulator flush mask*/
+#define XRFDC_CAL_GCB_ACEN_MASK	0x0800U	/**< GCB accumulator enable mask*/
+#define XRFDC_CAL_GCB_ENFL_MASK	0x1800U	/**< GCB accumulator enable mask*/
+
+#define XRFDC_CAL_OCB_EN_MASK	0x0001U /**< offsets coeff override enable mask*/
+#define XRFDC_CAL_GCB_EN_MASK	0x0080U /**< gain coeff override enable mask*/
+#define XRFDC_CAL_TSCB_EN_MASK	0x8000U /**< time skew coeff override enable mask*/
+
+#define XRFDC_CAL_OCB_EN_SHIFT		0U /**< offsets coeff shift*/
+#define XRFDC_CAL_GCB_EN_SHIFT		7U /**< gain coeff shift*/
+#define XRFDC_CAL_TSCB_EN_SHIFT		15U /**< time skew coeff shift*/
+#define XRFDC_CAL_GCB_FLSH_SHIFT	12U	/**< GCB accumulator flush shift*/
+#define XRFDC_CAL_GCB_ACEN_SHIFT	11U	/**< GCB accumulator enable shift*/
+
+#define XRFDC_CAL_SLICE_SHIFT		16U /**<Coefficient shift for HSADCs*/
+
+/* @} */
+/** @name Calibration Coefficients - Calibration coefficients and disable registers
+ *
+ * This register contains bits for calibration coefficients
+ * for ADC.
+ * @{
+ */
+
+#define XRFDC_CAL_FREEZE_CAL_MASK	0x1U /**< Calibration freeze enable mask*/
+#define XRFDC_CAL_FREEZE_STS_MASK	0x2U /**< Calibration freeze status mask*/
+#define XRFDC_CAL_FREEZE_PIN_MASK	0x4U /**< Calibration freeze pin disable mask*/
+
+#define XRFDC_CAL_FREEZE_CAL_SHIFT	0U /**< Calibration freeze enable shift*/
+#define XRFDC_CAL_FREEZE_STS_SHIFT	1U /**< Calibration freeze status shift*/
+#define XRFDC_CAL_FREEZE_PIN_SHIFT	2U /**< Calibration freeze pin disable shift*/
+
+/* @} */
+
+/** @name FIFO Enable - FIFO enable and disable register
+ *
+ * This register contains bits for FIFO enable and disable
+ * for ADC and DAC.
+ * @{
+ */
+
+#define XRFDC_FIFO_EN_MASK	0x00000001U /**< FIFO enable/disable */
+#define XRFDC_RESTART_MASK	0x00000001U	/**< Restart bit mask */
+
+/* @} */
+
+/** @name Clock Enable - FIFO Latency, fabric, DataPath,
+ * 			full-rate, output register
+ *
+ * This register contains bits for various clock enable options of
+ * the ADC. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_CLK_EN_CAL_MASK	0x00000001U /**< Enable Output
+							Register clock */
+#define XRFDC_CLK_EN_DIG_MASK	0x00000002U /**< Enable full-rate clock */
+#define XRFDC_CLK_EN_DP_MASK	0x00000004U /**< Enable Data Path clock */
+#define XRFDC_CLK_EN_FAB_MASK	0x00000008U /**< Enable fabric clock */
+#define XRFDC_DAT_CLK_EN_MASK	0x0000000FU /**< Data Path Clk enable */
+#define XRFDC_CLK_EN_LM_MASK	0x00000010U /**< Enable for FIFO
+							Latency measurement clock */
+
+/* @} */
+
+/** @name Debug reset - FIFO Latency, fabric, DataPath,
+ * 			full-rate, output register
+ *
+ * This register contains bits for various Debug reset options of
+ * the ADC. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_DBG_RST_CAL_MASK	0x00000001U /**< Reset clk_cal
+							clock domain */
+#define XRFDC_DBG_RST_DP_MASK	0x00000002U /**< Reset data path
+							clock domain */
+#define XRFDC_DBG_RST_FAB_MASK	0x00000004U /**< Reset clock fabric
+							clock domain */
+#define XRFDC_DBG_RST_DIG_MASK	0x00000008U /**< Reset clk_dig clock
+							domain */
+#define XRFDC_DBG_RST_DRP_CAL_MASK	0x00000010U /**< Reset subadc-drp
+							register on clock cal */
+#define XRFDC_DBG_RST_LM_MASK	0x00000020U /**< Reset FIFO Latency
+							measurement clock domain */
+
+/* @} */
+
+/** @name Fabric rate - Fabric data rate for read and write
+ *
+ * This register contains bits for read and write fabric data
+ * rate for ADC. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_ADC_FAB_RATE_WR_MASK	0x0000000FU /**< ADC FIFO Write Number
+							of Words per clock */
+#define XRFDC_DAC_FAB_RATE_WR_MASK	0x0000001FU /**< DAC FIFO Write Number
+							of Words per clock */
+#define XRFDC_FAB_RATE_RD_MASK	0x00000F00U /**< FIFO Read Number
+							of words per clock */
+#define XRFDC_FAB_RATE_RD_SHIFT		8U /**< Fabric Read shift */
+
+/* @} */
+
+/** @name Fabric Offset - FIFO de-skew
+ *
+ * This register contains bits of Fabric Offset.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_FAB_RD_PTR_OFFST_MASK	0x0000003FU /**< FIFO read pointer
+							offset for interface de-skew */
+
+/* @} */
+
+/** @name Fabric ISR - Interrupt status register for FIFO interface
+ *
+ * This register contains bits of margin-indicator and user-data overlap
+ * (overflow/underflow). Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_FAB_ISR_USRDAT_OVR_MASK	0x00000001U /**< User-data overlap-
+							data written faster than read (overflow) */
+#define XRFDC_FAB_ISR_USRDAT_UND_MASK	0x00000002U /**< User-data overlap-
+							data read faster than written (underflow) */
+#define XRFDC_FAB_ISR_USRDAT_MASK	0x00000003U /**< User-data overlap Mask */
+#define XRFDC_FAB_ISR_MARGIND_OVR_MASK	0x00000004U /**< Marginal-indicator
+							overlap (overflow) */
+#define XRFDC_FAB_ISR_MARGIND_UND_MASK	0x00000008U /**< Marginal-indicator
+							overlap (underflow) */
+/* @} */
+
+/** @name Fabric IMR - Interrupt mask register for FIFO interface
+ *
+ * This register contains bits of margin-indicator and user-data overlap
+ * (overflow/underflow). Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_FAB_IMR_USRDAT_OVR_MASK	0x00000001U /**< User-data overlap-
+							data written faster than read (overflow) */
+#define XRFDC_FAB_IMR_USRDAT_UND_MASK	0x00000002U /**< User-data overlap-
+							data read faster than written (underflow) */
+#define XRFDC_FAB_IMR_USRDAT_MASK	0x00000003U /**< User-data overlap Mask */
+#define XRFDC_FAB_IMR_MARGIND_OVR_MASK	0x00000004U /**< Marginal-indicator
+							overlap (overflow) */
+#define XRFDC_FAB_IMR_MARGIND_UND_MASK	0x00000008U /**< Marginal-indicator
+							overlap (underflow) */
+/* @} */
+
+/** @name Update Dynamic - Trigger a dynamic update event
+ *
+ * This register contains bits of update event for slice, nco, qmc
+ * and coarse delay. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_UPDT_EVNT_MASK	0x0000000FU /**< Update event mask */
+#define XRFDC_UPDT_EVNT_SLICE_MASK	0x00000001U /**< Trigger a slice update
+							event apply to _DCONFIG reg */
+#define XRFDC_UPDT_EVNT_NCO_MASK	0x00000002U /**< Trigger a update event
+							apply to NCO_DCONFIG reg */
+#define XRFDC_UPDT_EVNT_QMC_MASK	0x00000004U /**< Trigger a update event
+							apply to QMC_DCONFIG reg */
+#define XRFDC_ADC_UPDT_CRSE_DLY_MASK	0x00000008U /**< ADC Trigger a update event
+							apply to Coarse delay_DCONFIG reg */
+#define XRFDC_DAC_UPDT_CRSE_DLY_MASK	0x00000020U /**< DAC Trigger a update event
+							apply to Coarse delay_DCONFIG reg */
+/* @} */
+
+/** @name FIFO Latency control - Config registers for FIFO Latency measurement
+ *
+ * This register contains bits of FIFO Latency ctrl for disable, restart and
+ * set fifo latency measurement. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_FIFO_LTNCY_PRD_MASK	0x00000007U /**< Set FIFO Latency
+							measurement period */
+#define XRFDC_FIFO_LTNCY_RESTRT_MASK	0x00000008U /**< Restart FIFO Latency
+							measurement */
+#define XRFDC_FIFO_LTNCY_DIS_MASK	0x000000010U /**< Disable FIFO Latency
+							measurement */
+
+/* @} */
+
+/** @name Decode ISR - ISR for Decoder Interface
+ *
+ * This register contains bits of subadc 0,1,2 and 3 decoder overflow
+ * and underflow range. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_DEC_ISR_SUBADC_MASK		0x000000FFU /**< subadc decoder
+							Mask */
+#define XRFDC_DEC_ISR_SUBADC0_UND_MASK	0x00000001U /**< subadc0 decoder
+							underflow range */
+#define XRFDC_DEC_ISR_SUBADC0_OVR_MASK	0x00000002U /**< subadc0 decoder
+							overflow range */
+#define XRFDC_DEC_ISR_SUBADC1_UND_MASK	0x00000004U /**< subadc1 decoder
+							underflow range */
+#define XRFDC_DEC_ISR_SUBADC1_OVR_MASK	0x00000008U /**< subadc1 decoder
+							overflow range */
+#define XRFDC_DEC_ISR_SUBADC2_UND_MASK	0x00000010U /**< subadc2 decoder
+							underflow range */
+#define XRFDC_DEC_ISR_SUBADC2_OVR_MASK	0x00000020U /**< subadc2 decoder
+							overflow range */
+#define XRFDC_DEC_ISR_SUBADC3_UND_MASK	0x00000040U /**< subadc3 decoder
+							underflow range */
+#define XRFDC_DEC_ISR_SUBADC3_OVR_MASK	0x00000080U /**< subadc3 decoder
+							overflow range */
+
+/* @} */
+
+/** @name Decode IMR - IMR for Decoder Interface
+ *
+ * This register contains bits of subadc 0,1,2 and 3 decoder overflow
+ * and underflow range. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_DEC_IMR_SUBADC0_UND_MASK	0x00000001U /**< subadc0 decoder
+							underflow range */
+#define XRFDC_DEC_IMR_SUBADC0_OVR_MASK	0x00000002U /**< subadc0 decoder
+							overflow range */
+#define XRFDC_DEC_IMR_SUBADC1_UND_MASK	0x00000004U /**< subadc1 decoder
+							underflow range */
+#define XRFDC_DEC_IMR_SUBADC1_OVR_MASK	0x00000008U /**< subadc1 decoder
+							overflow range */
+#define XRFDC_DEC_IMR_SUBADC2_UND_MASK	0x00000010U /**< subadc2 decoder
+							underflow range */
+#define XRFDC_DEC_IMR_SUBADC2_OVR_MASK	0x00000020U /**< subadc2 decoder
+							overflow range */
+#define XRFDC_DEC_IMR_SUBADC3_UND_MASK	0x00000040U /**< subadc3 decoder
+							underflow range */
+#define XRFDC_DEC_IMR_SUBADC3_OVR_MASK	0x00000080U /**< subadc3 decoder
+							overflow range */
+#define XRFDC_DEC_IMR_MASK				0x000000FFU
+
+/* @} */
+
+/** @name DataPath (DAC)- FIFO Latency, Image Reject Filter, Mode,
+ *
+ * This register contains bits for DataPath latency, Image Reject Filter
+ * and the Mode for the DAC. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_DATAPATH_MODE_MASK	0x00000003U /**< DataPath Mode */
+#define XRFDC_DATAPATH_IMR_MASK		0x00000004U /**< IMR Mode */
+#define XRFDC_DATAPATH_LATENCY_MASK	0x00000008U /**< DataPath Latency */
+
+/* @} */
+
+
+
+/** @name DataPath ISR - ISR for Data Path interface
+ *
+ * This register contains bits of QMC Gain/Phase overflow, offset overflow,
+ * Decimation I-Path and Interpolation Q-Path overflow for stages 0,1,2.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_ADC_DAT_PATH_ISR_MASK	0x000000FFU /**< ADC Data Path Overflow */
+#define XRFDC_DAC_DAT_PATH_ISR_MASK	0x000001FFU /**< DAC Data Path Overflow */
+#define XRFDC_DAT_ISR_DECI_IPATH_MASK	0x00000007U /**< Decimation I-Path
+							overflow for stages 0,1,2 */
+#define XRFDC_DAT_ISR_INTR_QPATH_MASK	0x00000038U /**< Interpolation
+							Q-Path overflow for stages 0,1,2 */
+#define XRFDC_DAT_ISR_QMC_GAIN_MASK	0x00000040U /**< QMC Gain/Phase
+							overflow */
+#define XRFDC_DAT_ISR_QMC_OFFST_MASK	0x00000080U /**< QMC offset
+							overflow */
+#define XRFDC_DAC_DAT_ISR_INVSINC_MASK	0x00000100U /**< Inverse Sinc offset
+							overflow */
+
+/* @} */
+
+/** @name DataPath IMR - IMR for Data Path interface
+ *
+ * This register contains bits of QMC Gain/Phase overflow, offset overflow,
+ * Decimation I-Path and Interpolation Q-Path overflow for stages 0,1,2.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_DAT_IMR_DECI_IPATH_MASK	0x00000007U /**< Decimation I-Path
+							overflow for stages 0,1,2 */
+#define XRFDC_DAT_IMR_INTR_QPATH_MASK	0x00000038U /**< Interpolation
+							Q-Path overflow for stages 0,1,2 */
+#define XRFDC_DAT_IMR_QMC_GAIN_MASK	0x00000040U /**< QMC Gain/Phase
+							overflow */
+#define XRFDC_DAT_IMR_QMC_OFFST_MASK	0x00000080U /**< QMC offset
+							overflow */
+#define XRFDC_ADC_DAT_IMR_MASK	0x000000FFU	/**< ADC DataPath mask */
+#define XRFDC_DAC_DAT_IMR_MASK	0x00000FFFU	/**< DAC DataPath mask */
+
+/* @} */
+
+/** @name Decimation Config - Decimation control
+ *
+ * This register contains bits to configure the decimation in terms of
+ * the type of data. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_DEC_CFG_MASK	0x00000003U /**< ChannelA (2GSPS real
+							data from Mixer I output) */
+#define XRFDC_DEC_CFG_CHA_MASK	0x00000000U /**< ChannelA(I) */
+#define XRFDC_DEC_CFG_CHB_MASK	0x00000001U /**< ChannelB (2GSPS real
+							data from Mixer Q output) */
+#define XRFDC_DEC_CFG_IQ_MASK	0x00000002U /**< IQ-2GSPS */
+#define XRFDC_DEC_CFG_4GSPS_MASK	0x00000003U /**< 4GSPS may be I or Q
+							or Real depending on high level block config */
+
+/* @} */
+
+/** @name Decimation Mode - Decimation Rate
+ *
+ * This register contains bits to configures the decimation rate.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_DEC_MOD_MASK 		0x00000007U       /**< Decimation mode Mask */
+#define XRFDC_DEC_MOD_MASK_EXT 	0x0000003FU /**< Decimation mode Mask */
+
+/* @} */
+
+/** @name Mixer config0 - Configure I channel coarse mixer mode of operation
+ *
+ * This register contains bits to set the output data sequence of
+ * I channel. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_MIX_CFG0_MASK		0x00000FFFU	/**< Mixer Config0 Mask */
+#define XRFDC_MIX_I_DAT_WRD0_MASK	0x00000007U /**< Output data word[0]
+							of I channel */
+#define XRFDC_MIX_I_DAT_WRD1_MASK	0x00000038U /**< Output data word[1]
+							of I channel */
+#define XRFDC_MIX_I_DAT_WRD2_MASK	0x000001C0U /**< Output data word[2]
+							of I channel */
+#define XRFDC_MIX_I_DAT_WRD3_MASK	0x00000E00U /**< Output data word[3]
+							of I channel */
+
+/* @} */
+
+/** @name Mixer config1 - Configure Q channel coarse mixer mode of operation
+ *
+ * This register contains bits to set the output data sequence of
+ * Q channel. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_MIX_CFG1_MASK		0x00000FFFU	/**< Mixer Config0 Mask */
+#define XRFDC_MIX_Q_DAT_WRD0_MASK	0x00000007U /**< Output data word[0]
+							of Q channel */
+#define XRFDC_MIX_Q_DAT_WRD1_MASK	0x00000038U /**< Output data word[1]
+							of Q channel */
+#define XRFDC_MIX_Q_DAT_WRD2_MASK	0x000001C0U /**< Output data word[2]
+							of Q channel */
+#define XRFDC_MIX_Q_DAT_WRD3_MASK	0x00000E00U /**< Output data word[3]
+							of Q channel */
+
+/* @} */
+
+/** @name Mixer mode - Configure mixer mode of operation
+ *
+ * This register contains bits to set NCO phases, NCO output scale
+ * and fine mixer multipliers. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_EN_I_IQ_MASK			0x00000003U	/**< Enable fine mixer
+							multipliers on IQ i/p for I output */
+#define XRFDC_EN_Q_IQ_MASK			0x0000000CU	/**< Enable fine mixer
+							multipliers on IQ i/p for Q output */
+#define XRFDC_FINE_MIX_SCALE_MASK	0x00000010U	/**< NCO output scale */
+#define XRFDC_SEL_I_IQ_MASK			0x00000F00U	/**< Select NCO phases
+							for I output */
+#define XRFDC_SEL_Q_IQ_MASK			0x0000F000U	/**< Select NCO phases
+							for Q output */
+#define XRFDC_I_IQ_COS_MINSIN	0x00000C00U	/**< Select NCO phases
+							for I output */
+#define XRFDC_Q_IQ_SIN_COS		0x00001000U	/**< Select NCO phases
+							for Q output */
+#define XRFDC_MIXER_MODE_C2C_MASK	0x0000000FU	/**< Mixer mode C2C Mask */
+#define XRFDC_MIXER_MODE_R2C_MASK	0x00000005U	/**< Mixer mode R2C Mask */
+#define XRFDC_MIXER_MODE_C2R_MASK	0x00000003U	/**< Mixer mode C2R Mask */
+#define XRFDC_MIXER_MODE_OFF_MASK	0x00000000U	/**< Mixer mode OFF Mask */
+/* @} */
+
+/** @name NCO update - NCO update mode
+ *
+ * This register contains bits to Select event source, delay and reset delay.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_NCO_UPDT_MODE_MASK	0x00000007U	/**< NCO event source
+							selection mask */
+#define XRFDC_NCO_UPDT_MODE_GRP		0x00000000U	/**< NCO event source
+							selection is Group */
+#define XRFDC_NCO_UPDT_MODE_SLICE	0x00000001U	/**< NCO event source
+							selection is slice */
+#define XRFDC_NCO_UPDT_MODE_TILE	0x00000002U	/**< NCO event source
+							selection is tile */
+#define XRFDC_NCO_UPDT_MODE_SYSREF	0x00000003U	/**< NCO event source
+							selection is Sysref */
+#define XRFDC_NCO_UPDT_MODE_MARKER	0x00000004U	/**< NCO event source
+							selection is Marker */
+#define XRFDC_NCO_UPDT_MODE_FABRIC	0x00000005U	/**< NCO event source
+							selection is fabric */
+#define XRFDC_NCO_UPDT_DLY_MASK		0x00001FF8U	/**< delay in clk_dp
+							cycles in application of event after arrival */
+#define XRFDC_NCO_UPDT_RST_DLY_MASK	0x0000D000U	/**< optional delay on
+							the NCO phase reset delay */
+
+/* @} */
+
+/** @name NCO Phase Reset - NCO Slice Phase Reset
+ *
+ * This register contains bits to reset the nco phase of the current
+ * slice phase accumulator. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_NCO_PHASE_RST_MASK	0x00000001U	/**< Reset NCO Phase
+							of current slice */
+
+/* @} */
+
+/** @name DAC interpolation data
+ *
+ * This register contains bits for DAC interpolation data type
+ * @{
+ */
+
+#define XRFDC_DAC_INTERP_DATA_MASK	0x00000001U	/**< Data type mask */
+
+/* @} */
+
+/** @name NCO Freq Word[47:32] - NCO Phase increment(nco freq 48-bit)
+ *
+ * This register contains bits for frequency control word of the
+ * NCO. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_NCO_FQWD_UPP_MASK		0x0000FFFFU	/**< NCO Phase
+							increment[47:32] */
+#define XRFDC_NCO_FQWD_UPP_SHIFT	32U	/**< Freq Word upper shift */
+
+/* @} */
+
+/** @name NCO Freq Word[31:16] - NCO Phase increment(nco freq 48-bit)
+ *
+ * This register contains bits for frequency control word of the
+ * NCO. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_NCO_FQWD_MID_MASK		0x0000FFFFU	/**< NCO Phase
+							increment[31:16] */
+#define XRFDC_NCO_FQWD_MID_SHIFT	16U	/**< Freq Word Mid shift */
+
+/* @} */
+
+/** @name NCO Freq Word[15:0] - NCO Phase increment(nco freq 48-bit)
+ *
+ * This register contains bits for frequency control word of the
+ * NCO. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_NCO_FQWD_LOW_MASK		0x0000FFFFU	/**< NCO Phase
+							increment[15:0] */
+#define XRFDC_NCO_FQWD_MASK			0x0000FFFFFFFFFFFFU	/**< NCO Freq
+							offset[48:0] */
+
+/* @} */
+
+/** @name NCO Phase Offset[17:16] - NCO Phase offset
+ *
+ * This register contains bits to set NCO Phase offset(18-bit offset
+ * added to the phase accumulator). Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_NCO_PHASE_UPP_MASK		0x00000003U	/**< NCO Phase
+							offset[17:16] */
+#define XRFDC_NCO_PHASE_UPP_SHIFT		16U	/**< NCO phase upper shift */
+
+/* @} */
+
+/** @name NCO Phase Offset[15:0] - NCO Phase offset
+ *
+ * This register contains bits to set NCO Phase offset(18-bit offset
+ * added to the phase accumulator). Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_NCO_PHASE_LOW_MASK		0x0000FFFFU	/**< NCO Phase
+							offset[15:0] */
+#define XRFDC_NCO_PHASE_MASK			0x0003FFFFU	/**< NCO Phase
+							offset[17:0] */
+
+/* @} */
+
+/** @name NCO Phase mode - NCO Control setting mode
+ *
+ * This register contains bits to set NCO mode of operation.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_NCO_PHASE_MOD_MASK		0x00000003U	/**< NCO mode
+							of operation  mask */
+#define XRFDC_NCO_PHASE_MOD_4PHASE		0x00000003U	/**< NCO output
+							4 successive phase */
+#define XRFDC_NCO_PHASE_MOD_EVEN		0x00000001U	/**< NCO output
+							even phase */
+#define XRFDC_NCO_PHASE_MODE_ODD		0x00000002U	/**< NCO output
+							odd phase */
+/* @} */
+
+/** @name QMC update - QMC update mode
+ *
+ * This register contains bits to Select event source and delay.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_QMC_UPDT_MODE_MASK	0x00000007U	/**< QMC event source
+							selection mask */
+#define XRFDC_QMC_UPDT_MODE_GRP		0x00000000U	/**< QMC event source
+							selection is group */
+#define XRFDC_QMC_UPDT_MODE_SLICE	0x00000001U	/**< QMC event source
+							selection is slice */
+#define XRFDC_QMC_UPDT_MODE_TILE	0x00000002U	/**< QMC event source
+							selection is tile */
+#define XRFDC_QMC_UPDT_MODE_SYSREF	0x00000003U	/**< QMC event source
+							selection is Sysref */
+#define XRFDC_QMC_UPDT_MODE_MARKER	0x00000004U	/**< QMC event source
+							selection is Marker */
+#define XRFDC_QMC_UPDT_MODE_FABRIC	0x00000005U	/**< QMC event source
+							selection is fabric */
+#define XRFDC_QMC_UPDT_DLY_MASK		0x00001FF8U	/**< delay in clk_dp
+							cycles in application of event after arrival */
+
+/* @} */
+
+/** @name QMC Config - QMC Config register
+ *
+ * This register contains bits to enable QMC gain and QMC
+ * Phase correction. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_QMC_CFG_EN_GAIN_MASK	0x00000001U	/**< enable QMC gain
+							correction mask */
+#define XRFDC_QMC_CFG_EN_PHASE_MASK	0x00000002U	/**< enable QMC Phase
+							correction mask */
+#define XRFDC_QMC_CFG_PHASE_SHIFT	1U	/**< QMC config phase shift */
+
+/* @} */
+
+/** @name QMC Offset - QMC offset correction
+ *
+ * This register contains bits to set QMC offset correction
+ * factor. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_QMC_OFFST_CRCTN_MASK	0x00000FFFU	/**< QMC offset
+							correction factor */
+
+/* @} */
+
+/** @name QMC Gain - QMC Gain correction
+ *
+ * This register contains bits to set QMC gain correction
+ * factor. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_QMC_GAIN_CRCTN_MASK	0x00003FFFU	/**< QMC gain
+							correction factor */
+
+/* @} */
+
+/** @name QMC Phase - QMC Phase correction
+ *
+ * This register contains bits to set QMC phase correction
+ * factor. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_QMC_PHASE_CRCTN_MASK	0x00000FFFU	/**< QMC phase
+							correction factor */
+
+/* @} */
+
+/** @name Coarse Delay Update - Coarse delay update mode.
+ *
+ * This register contains bits to Select event source and delay.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_CRSEDLY_UPDT_MODE_MASK	0x00000007U	/**< Coarse delay event
+							source selection mask */
+#define XRFDC_CRSEDLY_UPDT_MODE_GRP		0x00000000U	/**< Coarse delay event
+							source selection is group */
+#define XRFDC_CRSEDLY_UPDT_MODE_SLICE	0x00000001U/**< Coarse delay event
+							source selection is slice */
+#define XRFDC_CRSEDLY_UPDT_MODE_TILE	0x00000002U	/**< Coarse delay event
+							source selection is tile */
+#define XRFDC_CRSEDLY_UPDT_MODE_SYSREF	0x00000003U	/**< Coarse delay event
+							source selection is sysref */
+#define XRFDC_CRSEDLY_UPDT_MODE_MARKER	0x00000004U	/**< Coarse delay event
+							source selection is Marker */
+#define XRFDC_CRSEDLY_UPDT_MODE_FABRIC	0x00000005U	/**< Coarse delay event
+							source selection is fabric */
+#define XRFDC_CRSEDLY_UPDT_DLY_MASK		0x00001FF8U	/**< delay in clk_dp
+							cycles in application of event after arrival */
+
+/* @} */
+
+/** @name Coarse delay Config - Coarse delay select
+ *
+ * This register contains bits to select coarse delay.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_CRSE_DLY_CFG_MASK		0x00000007U	/**< Coarse delay select */
+#define XRFDC_CRSE_DLY_CFG_MASK_EXT	0x0000003FU	/**< Extended coarse delay select*/
+
+/* @} */
+
+/** @name Data Scaling Config - Data Scaling enable
+ *
+ * This register contains bits to enable data scaling.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_DAT_SCALE_CFG_MASK		0x00000001U	/**< Enable data scaling */
+
+/* @} */
+
+/** @name Data Scaling Config - Data Scaling enable
+ *
+ * This register contains bits to enable data scaling.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_DAT_SCALE_CFG_MASK		0x00000001U	/**< Enable data scaling */
+
+/* @} */
+
+/** @name Switch Matrix Config
+ *
+ * This register contains bits to control crossbar switch that select
+ * data to mixer block. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_SWITCH_MTRX_MASK		0x0000003FU /**< Switch matrix mask */
+#define XRFDC_SEL_CB_TO_MIX1_MASK		0x00000003U	/**< Control crossbar
+							switch that select the data to mixer block mux1 */
+#define XRFDC_SEL_CB_TO_MIX0_MASK		0x0000000CU	/**< Control crossbar
+							switch that select the data to mixer block mux0 */
+#define XRFDC_SEL_CB_TO_QMC_MASK		0x00000010U	/**< Control crossbar
+							switch that select the data to QMC */
+#define XRFDC_SEL_CB_TO_DECI_MASK		0x00000020U	/**< Control crossbar
+							switch that select the data to decimation filter */
+#define XRFDC_SEL_CB_TO_MIX0_SHIFT		2U	/**< Crossbar Mixer0 shift */
+
+/* @} */
+
+/** @name Threshold0 Config
+ *
+ * This register contains bits to select mode, clear mode and to
+ * clear sticky bit. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TRSHD0_EN_MOD_MASK		0x00000003U	/**< Enable Threshold0
+							block */
+#define XRFDC_TRSHD0_CLR_MOD_MASK		0x00000004U	/**< Clear mode */
+#define XRFDC_TRSHD0_STIKY_CLR_MASK		0x00000008U	/**< Clear sticky bit */
+
+/* @} */
+
+/** @name Threshold0 Average[31:16]
+ *
+ * This register contains bits to select Threshold0 under averaging.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TRSHD0_AVG_UPP_MASK		0x0000FFFFU	/**< Threshold0 under
+							Averaging[31:16] */
+#define XRFDC_TRSHD0_AVG_UPP_SHIFT	16U	/**< Threshold0 Avg upper shift */
+/* @} */
+
+/** @name Threshold0 Average[15:0]
+ *
+ * This register contains bits to select Threshold0 under averaging.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TRSHD0_AVG_LOW_MASK		0x0000FFFFU	/**< Threshold0 under
+							Averaging[15:0] */
+
+/* @} */
+
+/** @name Threshold0 Under threshold
+ *
+ * This register contains bits to select Threshold0 under threshold.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TRSHD0_UNDER_MASK		0x00007FFFU	/**< Threshold0 under
+							Threshold[14:0] */
+
+/* @} */
+
+/** @name Threshold0 Over threshold
+ *
+ * This register contains bits to select Threshold0 over threshold.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TRSHD0_OVER_MASK		0x00007FFFU	/**< Threshold0 under
+							Threshold[14:0] */
+
+/* @} */
+
+/** @name Threshold1 Config
+ *
+ * This register contains bits to select mode, clear mode and to
+ * clear sticky bit. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TRSHD1_EN_MOD_MASK		0x00000003U	/**< Enable Threshold1
+							block */
+#define XRFDC_TRSHD1_CLR_MOD_MASK		0x00000004U	/**< Clear mode */
+#define XRFDC_TRSHD1_STIKY_CLR_MASK		0x00000008U	/**< Clear sticky bit */
+
+/* @} */
+
+/** @name Threshold1 Average[31:16]
+ *
+ * This register contains bits to select Threshold1 under averaging.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TRSHD1_AVG_UPP_MASK		0x0000FFFFU	/**< Threshold1 under
+							Averaging[31:16] */
+#define XRFDC_TRSHD1_AVG_UPP_SHIFT	16U	/**< Threshold1 Avg upper shift */
+
+/* @} */
+
+/** @name Threshold1 Average[15:0]
+ *
+ * This register contains bits to select Threshold1 under averaging.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TRSHD1_AVG_LOW_MASK		0x0000FFFFU	/**< Threshold1 under
+							Averaging[15:0] */
+
+/* @} */
+
+/** @name Threshold1 Under threshold
+ *
+ * This register contains bits to select Threshold1 under threshold.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TRSHD1_UNDER_MASK		0x00007FFFU	/**< Threshold1 under
+							Threshold[14:0] */
+
+/* @} */
+
+/** @name Threshold1 Over threshold
+ *
+ * This register contains bits to select Threshold1 over threshold.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TRSHD1_OVER_MASK		0x00007FFFU	/**< Threshold1 under
+							Threshold[14:0] */
+
+/* @} */
+
+/** @name FrontEnd Data Control
+ *
+ * This register contains bits to select raw data and cal coefficient to
+ * be streamed to memory. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_FEND_DAT_CTRL_MASK	0x000000FFU	/**< raw data and cal
+							coefficient to be streamed to memory */
+
+/* @} */
+
+/** @name TI Digital Correction Block control0
+ *
+ * This register contains bits for Time Interleaved digital correction
+ * block gain and offset correction. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TI_DCB_CTRL0_MASK		0x0000FFFFU	/**< TI  DCB gain and
+							offset correction */
+#define XRFDC_TI_DCB_MODE_MASK	0x00007800U /**< TI DCB Mode mask */
+
+/* @} */
+
+/** @name TI Digital Correction Block control1
+ *
+ * This register contains bits for Time Interleaved digital correction
+ * block gain and offset correction. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TI_DCB_CTRL1_MASK		0x00001FFFU	/**< TI  DCB gain and
+							offset correction */
+
+/* @} */
+
+/** @name TI Digital Correction Block control2
+ *
+ * This register contains bits for Time Interleaved digital correction
+ * block gain and offset correction. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TI_DCB_CTRL2_MASK		0x00001FFFU	/**< TI  DCB gain and
+							offset correction */
+
+/* @} */
+
+/** @name TI Time Skew control0
+ *
+ * This register contains bits for Time skew correction control bits0(enables,
+ * mode, multiplier factors, debug). Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TI_TISK_EN_MASK		0x00000001U	/**< Block Enable */
+#define XRFDC_TI_TISK_MODE_MASK		0x00000002U	/**< Mode (2G/4G) */
+#define XRFDC_TI_TISK_ZONE_MASK		0x00000004U	/**< Specifies Nyquist zone */
+#define XRFDC_TI_TISK_CHOP_EN_MASK	0x00000008U	/**< enable chopping mode */
+#define XRFDC_TI_TISK_MU_CM_MASK	0x000000F0U	/**< Constant mu_cm multiplying
+							common mode path */
+#define XRFDC_TI_TISK_MU_DF_MASK	0x00000F00U	/**< Constant mu_df multiplying
+							differential path */
+#define XRFDC_TI_TISK_DBG_CTRL_MASK	0x0000F000U	/**< Debug control */
+#define XRFDC_TI_TISK_DBG_UPDT_RT_MASK	0x00001000U	/**< Debug update rate */
+#define XRFDC_TI_TISK_DITH_DLY_MASK	0x0000E000U	/**< Programmable delay on
+							dither path to match data path */
+#define XRFDC_TISK_ZONE_SHIFT		2U	/**< Nyquist zone shift */
+
+/* @} */
+
+/** @name DAC MC Config0
+ *
+ * This register contains bits for enable/disable shadow logic , Nyquist zone
+ * selction, enable full speed clock, Programmable delay.
+ * @{
+ */
+
+#define XRFDC_MC_CFG0_MIX_MODE_MASK		0x00000002U	/**< Enable
+								Mixing mode */
+#define XRFDC_MC_CFG0_MIX_MODE_SHIFT	1U	/**< Mix mode shift */
+
+/* @} */
+
+/** @name TI Time Skew control0
+ *
+ * This register contains bits for Time skew correction control bits0(enables,
+ * mode, multiplier factors, debug). Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TISK_EN_MASK		0x00000001U	/**< Block Enable */
+#define XRFDC_TISK_MODE_MASK		0x00000002U	/**< Mode (2G/4G) */
+#define XRFDC_TISK_ZONE_MASK		0x00000004U	/**< Specifies Nyquist zone */
+#define XRFDC_TISK_CHOP_EN_MASK	0x00000008U	/**< enable chopping mode */
+#define XRFDC_TISK_MU_CM_MASK	0x000000F0U	/**< Constant mu_cm multiplying
+							common mode path */
+#define XRFDC_TISK_MU_DF_MASK	0x00000F00U	/**< Constant mu_df multiplying
+							differential path */
+#define XRFDC_TISK_DBG_CTRL_MASK	0x0000F000U	/**< Debug control */
+#define XRFDC_TISK_DBG_UPDT_RT_MASK	0x00001000U	/**< Debug update rate */
+#define XRFDC_TISK_DITH_DLY_MASK	0x0000E000U	/**< Programmable delay on
+							dither path to match data path */
+
+/* @} */
+
+/** @name TI Time Skew control1
+ *
+ * This register contains bits for Time skew correction control bits1
+ * (Deadzone Parameters). Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TISK_DZ_MIN_VAL_MASK		0x000000FFU	/**< Deadzone min */
+#define XRFDC_TISK_DZ_MAX_VAL_MASK		0x0000FF00U	/**< Deadzone max */
+
+/* @} */
+
+/** @name TI Time Skew control2
+ *
+ * This register contains bits for Time skew correction control bits2
+ * (Filter parameters). Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TISK_MU0_MASK			0x0000000FU	/**< Filter0 multiplying factor */
+#define XRFDC_TISK_BYPASS0_MASK		0x00000080U	/**< ByPass filter0 */
+#define XRFDC_TISK_MU1_MASK			0x00000F00U	/**< Filter1 multiplying factor */
+#define XRFDC_TISK_BYPASS1_MASK		0x00008000U	/**< Filter1 multiplying factor */
+
+/* @} */
+
+/** @name TI Time Skew control3
+ *
+ * This register contains bits for Time skew control settling time
+ * following code update. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TISK_SETTLE_MASK		0x000000FFU	/**< Settling time following
+							code update */
+
+/* @} */
+
+/** @name TI Time Skew control4
+ *
+ * This register contains bits for Time skew control setting time
+ * following code update. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TISK_CAL_PRI_MASK		0x00000001U	/**< */
+#define XRFDC_TISK_DITH_INV_MASK	0x00000FF0U	/**< */
+
+/* @} */
+
+/** @name TI Time Skew DAC0
+ *
+ * This register contains bits for Time skew DAC cal code of
+ * subadc ch0. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TISK_DAC0_CODE_MASK		0x000000FFU	/**< Code to correction
+							DAC of subadc ch0 front end switch0 */
+#define XRFDC_TISK_DAC0_OVRID_EN_MASK	0x00008000U	/**< override enable */
+
+/* @} */
+
+/** @name TI Time Skew DAC1
+ *
+ * This register contains bits for Time skew DAC cal code of
+ * subadc ch1. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TISK_DAC1_CODE_MASK		0x000000FFU	/**< Code to correction
+							DAC of subadc ch1 front end switch0 */
+#define XRFDC_TISK_DAC1_OVRID_EN_MASK	0x00008000U	/**< override enable */
+
+/* @} */
+
+/** @name TI Time Skew DAC2
+ *
+ * This register contains bits for Time skew DAC cal code of
+ * subadc ch2. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TISK_DAC2_CODE_MASK		0x000000FFU	/**< Code to correction
+							DAC of subadc ch2 front end switch0 */
+#define XRFDC_TISK_DAC2_OVRID_EN_MASK	0x00008000U	/**< override enable */
+
+/* @} */
+
+/** @name TI Time Skew DAC3
+ *
+ * This register contains bits for Time skew DAC cal code of
+ * subadc ch3. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TISK_DAC3_CODE_MASK		0x000000FFU	/**< Code to correction
+							DAC of subadc ch3 front end switch0 */
+#define XRFDC_TISK_DAC3_OVRID_EN_MASK	0x00008000U	/**< override enable */
+
+/* @} */
+
+/** @name TI Time Skew DACP0
+ *
+ * This register contains bits for Time skew DAC cal code of
+ * subadc ch0. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TISK_DACP0_CODE_MASK		0x000000FFU	/**< Code to correction
+							DAC of subadc ch0 front end switch1 */
+#define XRFDC_TISK_DACP0_OVRID_EN_MASK	0x00008000U	/**< override enable */
+
+/* @} */
+
+/** @name TI Time Skew DACP1
+ *
+ * This register contains bits for Time skew DAC cal code of
+ * subadc ch1. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TISK_DACP1_CODE_MASK		0x000000FFU	/**< Code to correction
+							DAC of subadc ch1 front end switch1 */
+#define XRFDC_TISK_DACP1_OVRID_EN_MASK	0x00008000U	/**< override enable */
+
+/* @} */
+
+/** @name TI Time Skew DACP2
+ *
+ * This register contains bits for Time skew DAC cal code of
+ * subadc ch2. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TISK_DACP2_CODE_MASK		0x000000FFU	/**< Code to correction
+							DAC of subadc ch2 front end switch1 */
+#define XRFDC_TISK_DACP2_OVRID_EN_MASK	0x00008000U	/**< override enable */
+
+/* @} */
+
+/** @name TI Time Skew DACP3
+ *
+ * This register contains bits for Time skew DAC cal code of
+ * subadc ch3. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TISK_DACP3_CODE_MASK		0x000000FFU	/**< Code to correction
+							DAC of subadc ch3 front end switch1 */
+#define XRFDC_TISK_DACP3_OVRID_EN_MASK	0x00008000U	/**< override enable */
+
+/* @} */
+
+/** @name SubDRP ADC0 address
+ *
+ * This register contains the sub-drp address of the target register.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_SUBDRP_ADC0_ADDR_MASK		0x000000FFU	/**< sub-drp0 address */
+
+/* @} */
+
+/** @name SubDRP ADC0 Data
+ *
+ * This register contains the sub-drp data of the target register.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_SUBDRP_ADC0_DAT_MASK		0x0000FFFFU	/**< sub-drp0 data
+							for read or write transaction */
+
+/* @} */
+
+/** @name SubDRP ADC1 address
+ *
+ * This register contains the sub-drp address of the target register.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_SUBDRP_ADC1_ADDR_MASK		0x000000FFU	/**< sub-drp1 address */
+
+/* @} */
+
+/** @name SubDRP ADC1 Data
+ *
+ * This register contains the sub-drp data of the target register.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_SUBDRP_ADC1_DAT_MASK		0x0000FFFFU	/**< sub-drp1 data
+							for read or write transaction */
+
+/* @} */
+
+/** @name SubDRP ADC2 address
+ *
+ * This register contains the sub-drp address of the target register.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_SUBDRP_ADC2_ADDR_MASK		0x000000FFU	/**< sub-drp2 address */
+
+/* @} */
+
+/** @name SubDRP ADC2 Data
+ *
+ * This register contains the sub-drp data of the target register.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_SUBDRP_ADC2_DAT_MASK		0x0000FFFFU	/**< sub-drp2 data
+							for read or write transaction */
+
+/* @} */
+
+/** @name SubDRP ADC3 address
+ *
+ * This register contains the sub-drp address of the target register.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_SUBDRP_ADC3_ADDR_MASK		0x000000FFU	/**< sub-drp3 address */
+
+/* @} */
+
+/** @name SubDRP ADC3 Data
+ *
+ * This register contains the sub-drp data of the target register.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_SUBDRP_ADC3_DAT_MASK		0x0000FFFFU	/**< sub-drp3 data
+							for read or write transaction */
+
+/* @} */
+
+/** @name RX MC PWRDWN
+ *
+ * This register contains the static configuration bits of ADC(RX) analog.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_RX_MC_PWRDWN_MASK		0x0000FFFFU	/**< RX MC power down */
+
+/* @} */
+
+/** @name RX MC Config0
+ *
+ * This register contains the static configuration bits of ADC(RX) analog.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_RX_MC_CFG0_MASK		    0x0000FFFFU	/**< RX MC config0 */
+#define XRFDC_RX_MC_CFG0_CM_MASK	    0x00000040U /**< Coupling mode mask */
+#define XRFDC_RX_MC_CFG0_IM3_DITH_MASK  0x00000020U /**< IM3 Dither Enable mode mask */
+#define XRFDC_RX_MC_CFG0_IM3_DITH_SHIFT 5U 			/**< IM3 Dither Enable mode shift */
+
+/* @} */
+
+/** @name RX MC Config1
+ *
+ * This register contains the static configuration bits of ADC(RX) analog.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_RX_MC_CFG1_MASK		0x0000FFFFU	/**< RX MC Config1 */
+
+/* @} */
+
+/** @name RX MC Config2
+ *
+ * This register contains the static configuration bits of ADC(RX) analog.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_RX_MC_CFG2_MASK		0x0000FFFFU	/**< RX MC Config2 */
+
+/* @} */
+
+/** @name RX Pair MC Config0
+ *
+ * This register contains the RX Pair (RX0 and RX1 or RX2 and RX3)static
+ * configuration bits of ADC(RX) analog. Read/Write apart from the
+ * reserved bits.
+ * @{
+ */
+
+#define XRFDC_RX_PR_MC_CFG0_MASK		0x0000FFFFU	/**< RX Pair MC Config0 */
+
+/* @} */
+
+/** @name RX Pair MC Config1
+ *
+ * This register contains the RX Pair (RX0 and RX1 or RX2 and RX3)static
+ * configuration bits of ADC(RX) analog. Read/Write apart from the
+ * reserved bits.
+ * @{
+ */
+
+#define XRFDC_RX_PR_MC_CFG1_MASK		0x0000FFFFU	/**< RX Pair MC Config1 */
+
+/* @} */
+
+/** @name TI DCB Status0 BG
+ *
+ * This register contains the subadc ch0 ocb1 BG offset correction factor
+ * value. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TI_DCB_STS0_BG_MASK		0x0000FFFFU	/**< DCB Status0 BG */
+
+/* @} */
+
+/** @name TI DCB Status0 FG
+ *
+ * This register contains the subadc ch0 ocb2 FG offset correction factor
+ * value(read and write). Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TI_DCB_STS0_FG_MASK		0x0000FFFFU	/**< DCB Status0 FG */
+
+/* @} */
+
+/** @name TI DCB Status1 BG
+ *
+ * This register contains the subadc ch1 ocb1 BG offset correction factor
+ * value. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TI_DCB_STS1_BG_MASK		0x0000FFFFU	/**< DCB Status1 BG */
+
+/* @} */
+
+/** @name TI DCB Status1 FG
+ *
+ * This register contains the subadc ch1 ocb2 FG offset correction factor
+ * value(read and write). Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TI_DCB_STS1_FG_MASK		0x0000FFFFU	/**< DCB Status1 FG */
+
+/* @} */
+
+/** @name TI DCB Status2 BG
+ *
+ * This register contains the subadc ch2 ocb1 BG offset correction factor
+ * value. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TI_DCB_STS2_BG_MASK		0x0000FFFFU	/**< DCB Status2 BG */
+
+/* @} */
+
+/** @name TI DCB Status2 FG
+ *
+ * This register contains the subadc ch2 ocb2 FG offset correction factor
+ * value(read and write). Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TI_DCB_STS2_FG_MASK		0x0000FFFFU	/**< DCB Status2 FG */
+
+/* @} */
+
+/** @name TI DCB Status3 BG
+ *
+ * This register contains the subadc ch3 ocb1 BG offset correction factor
+ * value. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TI_DCB_STS3_BG_MASK		0x0000FFFFU	/**< DCB Status3 BG */
+
+/* @} */
+
+/** @name TI DCB Status3 FG
+ *
+ * This register contains the subadc ch3 ocb2 FG offset correction factor
+ * value(read and write). Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_TI_DCB_STS3_FG_MASK		0x0000FFFFU	/**< DCB Status3 FG */
+
+/* @} */
+
+/** @name TI DCB Status4 MSB
+ *
+ * This register contains the DCB status. Read/Write apart from the
+ * reserved bits.
+ * @{
+ */
+
+#define XRFDC_TI_DCB_STS4_MSB_MASK		0x0000FFFFU	/**< read the status of
+							gcb acc0 msb bits(subadc chan0) */
+
+/* @} */
+
+/** @name TI DCB Status4 LSB
+ *
+ * This register contains the DCB Status. Read/Write apart from the
+ * reserved bits.
+ * @{
+ */
+
+#define XRFDC_TI_DCB_STS4_LSB_MASK		0x0000FFFFU	/**< read the status of
+							gcb acc0 lsb bits(subadc chan0) */
+
+/* @} */
+
+/** @name TI DCB Status5 MSB
+ *
+ * This register contains the DCB status. Read/Write apart from the
+ * reserved bits.
+ * @{
+ */
+
+#define XRFDC_TI_DCB_STS5_MSB_MASK		0x0000FFFFU	/**< read the status of
+							gcb acc1 msb bits(subadc chan1) */
+
+/* @} */
+
+/** @name TI DCB Status5 LSB
+ *
+ * This register contains the DCB Status. Read/Write apart from the
+ * reserved bits.
+ * @{
+ */
+
+#define XRFDC_TI_DCB_STS5_LSB_MASK		0x0000FFFFU	/**< read the status of
+							gcb acc1 lsb bits(subadc chan1) */
+
+/* @} */
+
+/** @name TI DCB Status6 MSB
+ *
+ * This register contains the DCB status. Read/Write apart from the
+ * reserved bits.
+ * @{
+ */
+
+#define XRFDC_TI_DCB_STS6_MSB_MASK		0x0000FFFFU	/**< read the status of
+							gcb acc2 msb bits(subadc chan2) */
+
+/* @} */
+
+/** @name TI DCB Status6 LSB
+ *
+ * This register contains the DCB Status. Read/Write apart from the
+ * reserved bits.
+ * @{
+ */
+
+#define XRFDC_TI_DCB_STS6_LSB_MASK		0x0000FFFFU	/**< read the status of
+							gcb acc2 lsb bits(subadc chan2) */
+
+/* @} */
+
+/** @name TI DCB Status7 MSB
+ *
+ * This register contains the DCB status. Read/Write apart from the
+ * reserved bits.
+ * @{
+ */
+
+#define XRFDC_TI_DCB_STS7_MSB_MASK		0x0000FFFFU	/**< read the status of
+							gcb acc3 msb bits(subadc chan3) */
+
+/* @} */
+
+/** @name TI DCB Status7 LSB
+ *
+ * This register contains the DCB Status. Read/Write apart from the
+ * reserved bits.
+ * @{
+ */
+
+#define XRFDC_TI_DCB_STS7_LSB_MASK		0x0000FFFFU	/**< read the status of
+							gcb acc3 lsb bits(subadc chan3) */
+
+/* @} */
+
+/** @name PLL_REFDIV
+ *
+ * This register contains the bits for Reference Clock Divider
+ * @{
+ */
+
+#define XRFDC_REFCLK_DIV_MASK		0x1FU
+#define XRFDC_REFCLK_DIV_1_MASK		0x10U	/**< Mask for Div1 */
+#define XRFDC_REFCLK_DIV_2_MASK		0x0U	/**< Mask for Div2 */
+#define XRFDC_REFCLK_DIV_3_MASK		0x1U	/**< Mask for Div3 */
+#define XRFDC_REFCLK_DIV_4_MASK		0x2U	/**< Mask for Div4 */
+
+/* @} */
+
+/** @name FIFO Latency
+ *
+ * This register contains bits for result, key and done flag.
+ * Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XRFDC_FIFO_LTNCY_RES_MASK	0x00000FFFU	/**< Latency
+							measurement result */
+#define XRFDC_FIFO_LTNCY_KEY_MASK		0x00004000U	/**< Latency
+							measurement result identification key */
+#define XRFDC_FIFO_LTNCY_DONE_MASK		0x00008000U	/**< Latency
+							measurement done flag */
+
+/* @} */
+
+/** @name Decoder Control
+ *
+ * This register contains Unary Decoder/Randomizer settings to use.
+ * @{
+ */
+
+#define XRFDC_DEC_CTRL_MODE_MASK		0x00000007U	/**< Decoder mode */
+
+/* @} */
+
+/** @name HSCOM Power state mask
+ *
+ * This register contains HSCOM_PWR to check powerup_state.
+ * @{
+ */
+
+#define XRFDC_HSCOM_PWR_STATE_MASK		0x0000FFFFU	/**< powerup state mask */
+
+/* @} */
+
+/** @name Interpolation Control
+ *
+ * This register contains Interpolation filter modes.
+ * @{
+ */
+
+#define XRFDC_INTERP_MODE_MASK 			0x00000077U   /**< Interp filter mask */
+#define XRFDC_INTERP_MODE_I_MASK 		0x00000007U /**< Interp filter I */
+#define XRFDC_INTERP_MODE_Q_SHIFT 		4U	 /**< Interp mode Q shift */
+#define XRFDC_INTERP_MODE_MASK_EXT 		0x00003F3FU   /**< Interp filter mask */
+#define XRFDC_INTERP_MODE_I_MASK_EXT 	0x0000003FU /**< Interp filter I */
+#define XRFDC_INTERP_MODE_Q_SHIFT_EXT 	8U	 /**< Interp mode Q shift */
+
+
+/* @} */
+
+/** @name Tile Reset
+ *
+ * This register contains Tile reset bit.
+ * @{
+ */
+
+#define XRFDC_TILE_RESET_MASK		0x00000001U	/**< Tile reset mask */
+
+/* @} */
+
+/** @name Status register
+ *
+ * This register contains common status bits.
+ * @{
+ */
+
+#define XRFDC_PWR_UP_STAT_MASK		0x00000004U	/**< Power Up state mask */
+#define XRFDC_PWR_UP_STAT_SHIFT		2U	/**< PowerUp status shift */
+#define XRFDC_PLL_LOCKED_MASK		0x00000008U	/**< PLL Locked mask */
+#define XRFDC_PLL_LOCKED_SHIFT		3U	/**< PLL locked shift */
+
+/* @} */
+
+/** @name Restart State register
+ *
+ * This register contains Start and End state bits.
+ * @{
+ */
+
+#define XRFDC_PWR_STATE_MASK		0x0000FFFFU	/**< State mask */
+#define XRFDC_RSR_START_SHIFT		8U	/**< Start state shift */
+
+
+/* @} */
+
+/** @name Clock Detect register
+ *
+ * This register contains Start and End state bits.
+ * @{
+ */
+
+#define XRFDC_CLOCK_DETECT_MASK		0x0000FFFFU	/**< Clock detect mask */
+
+
+/* @} */
+
+/** @name Common interrupt enable register
+ *
+ * This register contains bits to enable interrupt for
+ * ADC and DAC tiles.
+ * @{
+ */
+
+#define XRFDC_EN_INTR_DAC_TILE0_MASK		0x00000001U	/**< DAC Tile0
+								interrupt enable mask */
+#define XRFDC_EN_INTR_DAC_TILE1_MASK		0x00000002U	/**< DAC Tile1
+								interrupt enable mask */
+#define XRFDC_EN_INTR_DAC_TILE2_MASK		0x00000004U	/**< DAC Tile2
+								interrupt enable mask */
+#define XRFDC_EN_INTR_DAC_TILE3_MASK		0x00000008U	/**< DAC Tile3
+								interrupt enable mask */
+#define XRFDC_EN_INTR_ADC_TILE0_MASK		0x00000010U	/**< ADC Tile0
+								interrupt enable mask */
+#define XRFDC_EN_INTR_ADC_TILE1_MASK		0x00000020U	/**< ADC Tile1
+								interrupt enable mask */
+#define XRFDC_EN_INTR_ADC_TILE2_MASK		0x00000040U	/**< ADC Tile2
+								interrupt enable mask */
+#define XRFDC_EN_INTR_ADC_TILE3_MASK		0x00000080U	/**< ADC Tile3
+								interrupt enable mask */
+/* @} */
+
+
+/** @name interrupt enable register
+ *
+ * This register contains bits to enable interrupt for blocks.
+ * @{
+ */
+
+#define XRFDC_EN_INTR_SLICE_MASK	0x0000000FU /**< Slice intr mask */
+#define XRFDC_EN_INTR_SLICE0_MASK		0x00000001U	/**< slice0
+								interrupt enable mask */
+#define XRFDC_EN_INTR_SLICE1_MASK		0x00000002U	/**< slice1
+								interrupt enable mask */
+#define XRFDC_EN_INTR_SLICE2_MASK		0x00000004U	/**< slice2
+								interrupt enable mask */
+#define XRFDC_EN_INTR_SLICE3_MASK		0x00000008U	/**< slice3
+								interrupt enable mask */
+/* @} */
+
+/** @name Converter(X) interrupt register
+ *
+ * This register contains bits to enable different interrupts for block X.
+ * @{
+ */
+
+#define XRFDC_INTR_OVR_RANGE_MASK		0x00000008U	/**< Over Range
+								interrupt mask */
+#define XRFDC_INTR_OVR_VOLTAGE_MASK		0x00000004U	/**< Over Voltage
+								interrupt mask */
+#define XRFDC_INTR_FIFO_OVR_MASK	0x00008000U	/**< FIFO OF mask */
+#define XRFDC_INTR_DAT_OVR_MASK		0x00004000U	/**< Data OF mask */
+#define XRFDC_INTR_CMODE_OVR_MASK	0x00040000U /**< Common mode OV mask */
+#define XRFDC_INTR_CMODE_UNDR_MASK	0x00080000U /**< Common mode UV mask */
+/* @} */
+
+/** @name Multiband config register
+ *
+ * This register contains bits to configure multiband.
+ * @{
+ */
+
+#define XRFDC_EN_MB_MASK		0x00000008U	/**< multi-band adder mask */
+#define XRFDC_EN_MB_SHIFT		3U			/** <Enable Multiband shift */
+#define XRFDC_ALT_BOND_MASK		0x0100		/** <Alt bondout mask */
+#define XRFDC_ALT_BOND_SHIFT	8U			/** <Alt bondout shift */
+
+/* @} */
+
+/** @name Invsinc control register
+ *
+ * This register contains bits to configure Invsinc.
+ * @{
+ */
+#define XRFDC_EN_INVSINC_MASK	0x00000001U	/**< invsinc enable mask */
+#define XRFDC_MODE_INVSINC_MASK	0x00000003U	/**< invsinc mode mask */
+/* @} */
+
+/* @} */
+
+/** @name Signal Detector control register
+ *
+ * This register contains bits to configure Signal Detector.
+ * @{
+ */
+#define XRFDC_ADC_SIG_DETECT_MASK				0xFF /**< signal detector mask */
+#define XRFDC_ADC_SIG_DETECT_THRESH_MASK		0xFF /**< signal detector thresholds mask */
+#define XRFDC_ADC_SIG_DETECT_INTG_MASK			0x01 /**< leaky integrator enable mask */
+#define XRFDC_ADC_SIG_DETECT_FLUSH_MASK			0x02 /**< leaky integrator flush mask */
+#define XRFDC_ADC_SIG_DETECT_TCONST_MASK		0x1C /**< time constant mask */
+#define XRFDC_ADC_SIG_DETECT_MODE_MASK			0x60 /**< mode mask */
+#define XRFDC_ADC_SIG_DETECT_HYST_MASK			0x80 /**< hysteresis enable mask */
+#define XRFDC_ADC_SIG_DETECT_INTG_SHIFT			0 	 /**< leaky integrator enable shift */
+#define XRFDC_ADC_SIG_DETECT_FLUSH_SHIFT		1 	 /**< leaky integrator flush shift */
+#define XRFDC_ADC_SIG_DETECT_TCONST_SHIFT		2    /**< time constant shift */
+#define XRFDC_ADC_SIG_DETECT_MODE_WRITE_SHIFT	5    /**< mode shift fror writing */
+#define XRFDC_ADC_SIG_DETECT_MODE_READ_SHIFT	6    /**< mode shift fror reading */
+#define XRFDC_ADC_SIG_DETECT_HYST_SHIFT			7    /**< hysteresis enable shift */
+/* @} */
+
+/** @name CLK_DIV register
+ *
+ * This register contains the bits to control the clock
+ * divider providing the clock fabric out.
+ * @{
+ */
+
+#define XRFDC_FAB_CLK_DIV_MASK		0x0000000FU	/**< clk div mask */
+
+/* @} */
+
+/** @name Multiband Config
+ *
+ * This register contains bits to configure multiband for DAC.
+ * @{
+ */
+
+#define XRFDC_MB_CFG_MASK		0x000001FFU /**< MB config mask */
+#define XRFDC_MB_EN_4X_MASK		0x00000100U /**< Enable 4X MB mask */
+
+/* @} */
+
+/** @name Multi Tile Sync
+ *
+ * Multi-Tile Sync bit masks.
+ * @{
+ */
+
+#define XRFDC_MTS_SRCAP_PLL_M		0x0100U
+#define XRFDC_MTS_SRCAP_DIG_M		0x0100U
+#define XRFDC_MTS_SRCAP_EN_TRX_M	0x0400U
+#define XRFDC_MTS_SRCAP_INIT_M		0x8200U
+#define XRFDC_MTS_SRCLR_T1_M		0x2000U
+#define XRFDC_MTS_SRCLR_PLL_M		0x0200U
+#define XRFDC_MTS_PLLEN_M			0x0001U
+#define XRFDC_MTS_SRCOUNT_M			0x00FFU
+#define XRFDC_MTS_DELAY_VAL_M		0x041FU
+#define XRFDC_MTS_AMARK_CNT_M		0x00FFU
+#define XRFDC_MTS_AMARK_LOC_M		0x0F0000U
+#define XRFDC_MTS_AMARK_DONE_M		0x100000U
+
+/* @} */
+
+/** @name Output divider LSB register
+ *
+ * This register contains bits to configure output divisor
+ * @{
+ */
+
+#define XRFDC_PLL_DIVIDER0_MASK 		0x00FFU
+#define XRFDC_PLL_DIVIDER0_MODE_MASK 	0x00C0U
+#define XRFDC_PLL_DIVIDER0_VALUE_MASK 	0x003FU
+#define XRFDC_PLL_DIVIDER0_SHIFT		6U
+
+/* @} */
+
+/** @name Multi-tile sync and clock source control register
+ *
+ * This register contains bits to Multi-tile sync and clock source control
+ * @{
+ */
+#define XRFDC_CLK_NETWORK_CTRL1_USE_PLL_MASK	0x1U /**< PLL clock mask */
+
+/* @} */
+
+/** @name PLL_CRS1 - PLL CRS1 register
+ *
+ * This register contains bits for VCO sel_auto, VCO band selection etc.,
+ * @{
+ */
+
+#define XRFDC_PLL_CRS1_VCO_SEL_MASK		0x00008001U /**< VCO SEL Mask */
+#define XRFDC_PLL_VCO_SEL_AUTO_MASK		0x00008000U /**< VCO Auto SEL Mask */
+
+/* @} */
+
+/** Register bits Shift, Width Masks
+ *
+ * @{
+ */
+#define XRFDC_DIGI_ANALOG_SHIFT4	4U
+#define XRFDC_DIGI_ANALOG_SHIFT8	8U
+#define XRFDC_DIGI_ANALOG_SHIFT12	12U
+
+/* @} */
+
+#define XRFDC_IXR_FIFOUSRDAT_MASK			0x0000000FU
+#define XRFDC_IXR_FIFOUSRDAT_OF_MASK		0x00000001U
+#define XRFDC_IXR_FIFOUSRDAT_UF_MASK 		0x00000002U
+#define XRFDC_IXR_FIFOMRGNIND_OF_MASK 		0x00000004U
+#define XRFDC_IXR_FIFOMRGNIND_UF_MASK 		0x00000008U
+#define XRFDC_ADC_IXR_DATAPATH_MASK			0x00000FF0U
+#define XRFDC_ADC_IXR_DMON_STG_MASK			0x000003F0U
+#define XRFDC_DAC_IXR_DATAPATH_MASK			0x00001FF0U
+#define XRFDC_DAC_IXR_INTP_STG_MASK 		0x000003F0U
+#define XRFDC_DAC_IXR_INTP_I_STG0_MASK 		0x00000010U
+#define XRFDC_DAC_IXR_INTP_I_STG1_MASK 		0x00000020U
+#define XRFDC_DAC_IXR_INTP_I_STG2_MASK 		0x00000040U
+#define XRFDC_DAC_IXR_INTP_Q_STG0_MASK 		0x00000080U
+#define XRFDC_DAC_IXR_INTP_Q_STG1_MASK 		0x00000100U
+#define XRFDC_DAC_IXR_INTP_Q_STG2_MASK 		0x00000200U
+#define XRFDC_ADC_IXR_DMON_I_STG0_MASK 		0x00000010U
+#define XRFDC_ADC_IXR_DMON_I_STG1_MASK 		0x00000020U
+#define XRFDC_ADC_IXR_DMON_I_STG2_MASK 		0x00000040U
+#define XRFDC_ADC_IXR_DMON_Q_STG0_MASK 		0x00000080U
+#define XRFDC_ADC_IXR_DMON_Q_STG1_MASK 		0x00000100U
+#define XRFDC_ADC_IXR_DMON_Q_STG2_MASK 		0x00000200U
+#define XRFDC_IXR_QMC_GAIN_PHASE_MASK 		0x00000400U
+#define XRFDC_IXR_QMC_OFFST_MASK 			0x00000800U
+#define XRFDC_DAC_IXR_INVSNC_OF_MASK 		0x00001000U
+#define XRFDC_SUBADC_IXR_DCDR_MASK 			0x00FF0000U
+#define XRFDC_SUBADC0_IXR_DCDR_OF_MASK 		0x00010000U
+#define XRFDC_SUBADC0_IXR_DCDR_UF_MASK 		0x00020000U
+#define XRFDC_SUBADC1_IXR_DCDR_OF_MASK 		0x00040000U
+#define XRFDC_SUBADC1_IXR_DCDR_UF_MASK 		0x00080000U
+#define XRFDC_SUBADC2_IXR_DCDR_OF_MASK 		0x00100000U
+#define XRFDC_SUBADC2_IXR_DCDR_UF_MASK 		0x00200000U
+#define XRFDC_SUBADC3_IXR_DCDR_OF_MASK 		0x00400000U
+#define XRFDC_SUBADC3_IXR_DCDR_UF_MASK 		0x00800000U
+#define XRFDC_ADC_OVR_VOLTAGE_MASK			0x04000000U
+#define XRFDC_ADC_OVR_RANGE_MASK			0x08000000U
+#define XRFDC_ADC_CMODE_OVR_MASK			0x10000000U
+#define XRFDC_ADC_CMODE_UNDR_MASK			0x20000000U
+#define XRFDC_ADC_DAT_OVR_MASK				0x40000000U
+#define XRFDC_ADC_FIFO_OVR_MASK				0x80000000U
+#define XRFDC_DAC_MC_CFG2_OPCSCAS_MASK		0x0000F8F8U
+#define XRFDC_DAC_MC_CFG3_CSGAIN_MASK		0x0000FFC0U
+#define XRFDC_DAC_MC_CFG2_OPCSCAS_20MA		0x00004858U
+#define XRFDC_DAC_MC_CFG3_CSGAIN_20MA		0x000087C0U
+#define XRFDC_DAC_MC_CFG2_OPCSCAS_32MA		0x0000A0D8U
+#define XRFDC_DAC_MC_CFG3_CSGAIN_32MA		0x0000FFC0U
+
+#define XRFDC_ADC_OVR_VOL_RANGE_SHIFT		24U
+#define XRFDC_ADC_DAT_FIFO_OVR_SHIFT		16U
+#define XRFDC_ADC_SUBADC_DCDR_SHIFT			16U
+#define XRFDC_DATA_PATH_SHIFT				4U
+#define XRFDC_ADC_CMODE_SHIFT				10U
+
+#define XRFDC_DAC_TILE_DRP_ADDR(X)			(0x6000U + (X * 0x4000U))
+#define XRFDC_DAC_TILE_CTRL_STATS_ADDR(X)	(0x4000U + (X * 0x4000U))
+#define XRFDC_ADC_TILE_DRP_ADDR(X)			(0x16000U + (X * 0x4000U))
+#define XRFDC_ADC_TILE_CTRL_STATS_ADDR(X)	(0x14000U + (X * 0x4000U))
+#define XRFDC_CTRL_STATS_OFFSET		0x0U
+#define XRFDC_HSCOM_ADDR	0x1C00U
+#define XRFDC_BLOCK_ADDR_OFFSET(X)	(X * 0x400U)
+#define XRFDC_TILE_DRP_OFFSET		0x2000U
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define XRFdc_In64 metal_io_read64
+#define XRFdc_Out64 metal_io_write64
+
+#define XRFdc_In32 metal_io_read32
+#define XRFdc_Out32 metal_io_write32
+
+#define XRFdc_In16 metal_io_read16
+#define XRFdc_Out16 metal_io_write16
+
+#define XRFdc_In8 metal_io_read8
+#define XRFdc_Out8 metal_io_write8
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XRFdc_ReadReg64(XRFdc *InstancePtr. u32 BaseAddress, s32 RegOffset)
+*
+******************************************************************************/
+#define XRFdc_ReadReg64(InstancePtr, BaseAddress, RegOffset) \
+	XRFdc_In64(InstancePtr->io, ((u32)RegOffset + (u32)BaseAddress))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*			device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*	void XRFdc_WriteReg64(XRFdc *InstancePtr, u32 BaseAddress, s32 RegOffset,
+*	u64 RegisterValue)
+*
+******************************************************************************/
+#define XRFdc_WriteReg64(InstancePtr, BaseAddress, RegOffset, RegisterValue) \
+	XRFdc_Out64((InstancePtr->io), ((u32)RegOffset + (u32)BaseAddress), \
+		(u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XRFdc_ReadReg(XRFdc *InstancePtr, u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XRFdc_ReadReg(InstancePtr, BaseAddress, RegOffset) \
+	XRFdc_In32((InstancePtr->io), ((u32)BaseAddress + (u32)RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XRFdc_WriteReg(XRFdc *InstancePtr, u32 BaseAddress, int RegOffset,
+*		u32 RegisterValue)
+*
+******************************************************************************/
+#define XRFdc_WriteReg(InstancePtr, BaseAddress, RegOffset, RegisterValue) \
+	XRFdc_Out32((InstancePtr->io), ((u32)RegOffset + (u32)BaseAddress), \
+			(u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u16 XRFdc_ReadReg16(XRFdc *InstancePtr, u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XRFdc_ReadReg16(InstancePtr, BaseAddress, RegOffset) \
+	XRFdc_In16((InstancePtr->io), ((u32)RegOffset + (u32)BaseAddress))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*	void XRFdc_WriteReg16(XRFdc *InstancePtr, u32 BaseAddress, int RegOffset,
+*	u16 RegisterValue)
+*
+******************************************************************************/
+#define XRFdc_WriteReg16(InstancePtr, BaseAddress, RegOffset, RegisterValue) \
+	XRFdc_Out16((InstancePtr->io), ((u32)RegOffset + (u32)BaseAddress), \
+			(u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u8 XRFdc_ReadReg8(XRFdc *InstancePtr, u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XRFdc_ReadReg8(InstancePtr, BaseAddress, RegOffset) \
+	XRFdc_In8((InstancePtr->io), ((u32)RegOffset + (u32)BaseAddress))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	InstancePtr is a pointer to the XRfdc instance.
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*	void XRFdc_WriteReg8(XRFdc *InstancePtr, u32 BaseAddress, int RegOffset,
+*	u8 RegisterValue)
+*
+******************************************************************************/
+#define XRFdc_WriteReg8(InstancePtr, BaseAddress, RegOffset, RegisterValue) \
+	XRFdc_Out8((InstancePtr->io), ((u32)RegOffset + (u32)BaseAddress), \
+			(u32)(RegisterValue))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RFDC_HW_H_ */
+/** @} */
diff --git a/mpm/include/mpm/rfdc/xrfdc_mts.h b/mpm/include/mpm/rfdc/xrfdc_mts.h
new file mode 100644
index 000000000..ef56a6193
--- /dev/null
+++ b/mpm/include/mpm/rfdc/xrfdc_mts.h
@@ -0,0 +1,166 @@
+/******************************************************************************
+*
+* Copyright (C) 2018-2019 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xrfdc_mts.c
+* @addtogroup xrfdc_v6_0
+* @{
+*
+* Contains the multi tile sync related structures, Macros of the XRFdc driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 3.1   jm     01/24/18 Initial release
+* 3.2   jm     03/12/18 Fixed DAC latency calculation.
+*       jm     03/12/18 Added support for reloading DTC scans.
+*       jm     03/12/18 Add option to configure sysref capture after MTS.
+* 4.0   sk     04/09/18 Added API to enable/disable the sysref.
+*       rk     04/17/18 Adjust calculated latency by sysref period, where doing
+*                       so results in closer alignment to the target latency.
+* 5.0   sk     08/03/18 Fixed MISRAC warnings.
+*       sk     08/03/18 Check for Block0 enable for tiles participating in MTS.
+*       sk     08/24/18 Reorganize the code to improve readability and
+*                       optimization.
+* 6.0   cog    02/17/19 Added XRFdc_GetMTSEnable API.
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef RFDC_MTS_H_
+#define RFDC_MTS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xrfdc.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XRFDC_MTS_RMW(read, mask, data)    (((read) & ~(mask)) | ((data) & (mask)))
+#define XRFDC_MTS_FIELD(data, mask, shift) (((data) & (mask)) >> (shift))
+
+/**************************** Type Definitions *******************************/
+
+typedef struct {
+	u32 RefTile;
+	u32 IsPLL;
+	int Target[4];
+	int Scan_Mode;
+	int DTC_Code[4];
+	int Num_Windows[4];
+	int Max_Gap[4];
+	int Min_Gap[4];
+	int Max_Overlap[4];
+} XRFdc_MTS_DTC_Settings;
+
+typedef struct {
+	u32 RefTile;
+	u32 Tiles;
+	int Target_Latency;
+	int Offset[4];
+	int Latency[4];
+	int Marker_Delay;
+	int SysRef_Enable;
+	XRFdc_MTS_DTC_Settings DTC_Set_PLL;
+	XRFdc_MTS_DTC_Settings DTC_Set_T1;
+} XRFdc_MultiConverter_Sync_Config;
+
+typedef struct {
+	u32 Count[4];
+	u32 Loc[4];
+} XRFdc_MTS_Marker;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XRFDC_MTS_SYSREF_DISABLE	0U
+#define XRFDC_MTS_SYSREF_ENABLE		1U
+
+#define XRFDC_MTS_NUM_DTC			128U
+#define XRFDC_MTS_REF_TARGET		64U
+#define XRFDC_MTS_MAX_CODE			16U
+#define XRFDC_MTS_MIN_GAP_T1		10U
+#define XRFDC_MTS_MIN_GAP_PLL		5U
+#define XRFDC_MTS_SR_TIMEOUT		4096U
+#define XRFDC_MTS_DTC_COUNT			10U
+#define XRFDC_MTS_MARKER_COUNT		4U
+#define XRFDC_MTS_SCAN_INIT			0U
+#define XRFDC_MTS_SCAN_RELOAD		1U
+#define XRFDC_MTS_SRCOUNT_TIMEOUT	1000U
+#define XRFDC_MTS_DELAY_MAX			31U
+#define XRFDC_MTS_CHECK_ALL_FIFOS	0U
+
+#define XRFDC_MTS_SRCAP_T1_EN		0x4000U
+#define XRFDC_MTS_SRCAP_T1_RST		0x0800U
+#define XRFDC_MTS_SRFLAG_T1			0x4U
+#define XRFDC_MTS_SRFLAG_PLL		0x2U
+#define XRFDC_MTS_FIFO_DEFAULT		0x0000U
+#define XRFDC_MTS_FIFO_ENABLE		0x0003U
+#define XRFDC_MTS_FIFO_DISABLE		0x0002U
+#define XRFDC_MTS_AMARK_LOC_S		0x10U
+#define XRFDC_MTS_AMARK_DONE_S		0x14U
+#define XRFDC_MTS_DLY_ALIGNER		0x28U
+
+/* Error Codes */
+#define XRFDC_MTS_OK				0U
+#define XRFDC_MTS_NOT_SUPPORTED		1U
+#define XRFDC_MTS_TIMEOUT			2U
+#define XRFDC_MTS_MARKER_RUN		4U
+#define XRFDC_MTS_MARKER_MISM		8U
+#define XRFDC_MTS_DELAY_OVER		16U
+#define XRFDC_MTS_TARGET_LOW		32U
+#define XRFDC_MTS_IP_NOT_READY      64U
+#define XRFDC_MTS_DTC_INVALID       128U
+#define XRFDC_MTS_NOT_ENABLED       512U
+#define XRFDC_MTS_SYSREF_GATE_ERROR 2048U
+#define XRFDC_MTS_SYSREF_FREQ_NDONE 4096U
+
+/************************** Function Prototypes ******************************/
+
+u32 XRFdc_MultiConverter_Sync(XRFdc *InstancePtr, u32 Type,
+							XRFdc_MultiConverter_Sync_Config *ConfigPtr);
+void XRFdc_MultiConverter_Init(XRFdc_MultiConverter_Sync_Config *ConfigPtr,
+						int *PLL_CodesPtr, int *T1_CodesPtr);
+u32 XRFdc_MTS_Sysref_Config(XRFdc *InstancePtr,
+		XRFdc_MultiConverter_Sync_Config *DACSyncConfigPtr,
+		XRFdc_MultiConverter_Sync_Config *ADCSyncConfigPtr, u32 SysRefEnable);
+u32 XRFdc_GetMTSEnable(XRFdc *InstancePtr, u32 Type,u32 Tile, u32 *EnablePtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RFDC_MTS_H_ */
+/** @} */