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| author | Michael West <michael.west@ettus.com> | 2017-03-27 19:22:13 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2017-04-05 17:26:28 -0700 |
| commit | fe1088f9ce5bc6b2b2054a70aed60f62eb6c4c12 (patch) | |
| tree | dd3dcfcce3040f88f6e18f7511977d3209665587 /host | |
| parent | 171f85e4c7c0c1dbe796c5ba42215184ef2d6065 (diff) | |
| download | uhd-fe1088f9ce5bc6b2b2054a70aed60f62eb6c4c12.tar.gz uhd-fe1088f9ce5bc6b2b2054a70aed60f62eb6c4c12.tar.bz2 uhd-fe1088f9ce5bc6b2b2054a70aed60f62eb6c4c12.zip | |
X300: Change default frame sizes for PCIe to be page aligned for better
performance
Diffstat (limited to 'host')
| -rw-r--r-- | host/lib/usrp/x300/x300_impl.cpp | 8 | ||||
| -rw-r--r-- | host/lib/usrp/x300/x300_impl.hpp | 21 |
2 files changed, 16 insertions, 13 deletions
diff --git a/host/lib/usrp/x300/x300_impl.cpp b/host/lib/usrp/x300/x300_impl.cpp index fe422db46..4f3870357 100644 --- a/host/lib/usrp/x300/x300_impl.cpp +++ b/host/lib/usrp/x300/x300_impl.cpp @@ -1107,14 +1107,14 @@ uhd::both_xports_t x300_impl::make_transport( ? X300_PCIE_RX_DATA_FRAME_SIZE : X300_PCIE_MSG_FRAME_SIZE; - default_buff_args.num_send_frames = - (xport_type == TX_DATA) - ? X300_PCIE_DATA_NUM_FRAMES + default_buff_args.num_send_frames = + (xport_type == TX_DATA) + ? X300_PCIE_TX_DATA_NUM_FRAMES : X300_PCIE_MSG_NUM_FRAMES; default_buff_args.num_recv_frames = (xport_type == RX_DATA) - ? X300_PCIE_DATA_NUM_FRAMES + ? X300_PCIE_RX_DATA_NUM_FRAMES : X300_PCIE_MSG_NUM_FRAMES; xports.recv = nirio_zero_copy::make( diff --git a/host/lib/usrp/x300/x300_impl.hpp b/host/lib/usrp/x300/x300_impl.hpp index 27ea6f40e..14120bd1f 100644 --- a/host/lib/usrp/x300/x300_impl.hpp +++ b/host/lib/usrp/x300/x300_impl.hpp @@ -51,15 +51,18 @@ static const size_t X300_RX_SW_BUFF_SIZE_ETH = 0x2000000;//32MiB For a static const size_t X300_RX_SW_BUFF_SIZE_ETH_MACOS = 0x100000; //1Mib //The FIFO closest to the DMA controller is 1023 elements deep for RX and 1029 elements deep for TX -//where an element is 8 bytes. For best throughput ensure that the data frame fits in these buffers. -//Also ensure that the kernel has enough frames to hold buffered TX and RX data -static const size_t X300_PCIE_RX_DATA_FRAME_SIZE = 8184; //bytes -static const size_t X300_PCIE_TX_DATA_FRAME_SIZE = 8184; //bytes -static const size_t X300_PCIE_DATA_NUM_FRAMES = 2048; -static const size_t X300_PCIE_MSG_FRAME_SIZE = 256; //bytes -static const size_t X300_PCIE_MSG_NUM_FRAMES = 64; -static const size_t X300_PCIE_MAX_CHANNELS = 6; -static const size_t X300_PCIE_MAX_MUXED_XPORTS = 32; +//where an element is 8 bytes. The buffers (number of frames * frame size) must be aligned to the +//memory page size. For the control, we are getting lucky because 64 frames * 256 bytes each aligns +//with the typical page size of 4096 bytes. Since most page sizes are 4096 bytes or some multiple of +//that, keep the number of frames * frame size aligned to it. +static const size_t X300_PCIE_RX_DATA_FRAME_SIZE = 4096; //bytes +static const size_t X300_PCIE_RX_DATA_NUM_FRAMES = 4096; +static const size_t X300_PCIE_TX_DATA_FRAME_SIZE = 4096; //bytes +static const size_t X300_PCIE_TX_DATA_NUM_FRAMES = 4096; +static const size_t X300_PCIE_MSG_FRAME_SIZE = 256; //bytes +static const size_t X300_PCIE_MSG_NUM_FRAMES = 64; +static const size_t X300_PCIE_MAX_CHANNELS = 6; +static const size_t X300_PCIE_MAX_MUXED_XPORTS = 32; static const size_t X300_10GE_DATA_FRAME_MAX_SIZE = 8000; // CHDR packet size in bytes static const size_t X300_1GE_DATA_FRAME_MAX_SIZE = 1472; // CHDR packet size in bytes |