examples: Update x310_rfnoc_image_core.yml example

1 files changed, 99 insertions, 82 deletions

diff --git a/host/examples/rfnoc-example/icores/x310_rfnoc_image_core.yml b/host/examples/rfnoc-example/icores/x310_rfnoc_image_core.yml
index 2fa512990..1ecf5a36d 100644
--- a/host/examples/rfnoc-example/icores/x310_rfnoc_image_core.yml
+++ b/host/examples/rfnoc-example/icores/x310_rfnoc_image_core.yml
@@ -5,105 +5,122 @@ copyright: 'Ettus Research, A National Instruments Brand' # Copyright informatio
 license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers
 version: 1.0                            # File version
 rfnoc_version: 1.0                      # RFNoC protocol version
-chdr_width: 64                          # Bitwidth of the CHDR bus for this block
-device: 'x310'                          # USRP device descriptor file
+chdr_width: 64                          # Bit width of the CHDR bus for this image
+device: 'x310'
 default_target: 'X310_HG'
 
 # A list of all stream endpoints in design
 # ----------------------------------------
 stream_endpoints:
-    ep0:                       # Stream endpoint name
-      ctrl: True                      # Endpoint passes control traffic
-      data: True                      # Endpoint passes data traffic
-      buff_size: 32768                # Ingress buffer size for data
-    ep1:                       # Stream endpoint name
-      ctrl: False                     # Endpoint passes control traffic
-      data: True                      # Endpoint passes data traffic
-      buff_size: 0                    # Ingress buffer size for data
-    ep2:                       # Stream endpoint name
-      ctrl: False                     # Endpoint passes control traffic
-      data: True                      # Endpoint passes data traffic
-      buff_size: 32768                # Ingress buffer size for data
-    ep3:                       # Stream endpoint name
-      ctrl: False                     # Endpoint passes control traffic
-      data: True                      # Endpoint passes data traffic
-      buff_size: 0                    # Ingress buffer size for data
-    ep4:                       # Stream endpoint name
-      ctrl: False                     # Endpoint passes control traffic
-      data: True                      # Endpoint passes data traffic
-      buff_size: 32768                # Ingress buffer size for data
+  ep0:                       # Stream endpoint name
+    ctrl: True                      # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 32768                # Ingress buffer size for data
+  ep1:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 0                    # Ingress buffer size for data
+  ep2:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 32768                # Ingress buffer size for data
+  ep3:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 0                    # Ingress buffer size for data
+  ep4:                       # Stream endpoint name
+    ctrl: False                     # Endpoint passes control traffic
+    data: True                      # Endpoint passes data traffic
+    buff_size: 32768                # Ingress buffer size for data
 
 # A list of all NoC blocks in design
 # ----------------------------------
 noc_blocks:
-    duc0:                          # NoC block name
-      block_desc: 'duc_1x64.yml'   # Block device descriptor file
-    ddc0:
-      block_desc: 'ddc_2x64.yml'
-    radio0:
-      block_desc: 'radio_2x64.yml'
-    duc1:
-      block_desc: 'duc_1x64.yml'
-    ddc1:
-      block_desc: 'ddc_2x64.yml'
-    radio1:
-      block_desc: 'radio_2x64.yml'
-    fifo0:
-      block_desc: 'axi_ram_fifo_2x64.yml'
-      parameters:
-        # These parameters match the interface on the x300/X310
-        MEM_DATA_W: 64
-        MEM_ADDR_W: 30
-        FIFO_ADDR_BASE: "{30'h02000000, 30'h00000000}"
-        FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF}"
-        MEM_CLK_RATE: "300e6"
-    gain0:
-      block_desc: 'gain.yml'
+  duc0:                      # NoC block name
+    block_desc: 'duc.yml'    # Block device descriptor file
+    parameters:
+      NUM_PORTS: 1
+  ddc0:
+    block_desc: 'ddc.yml'
+    parameters:
+      NUM_PORTS: 2
+  radio0:
+    block_desc: 'radio_2x64.yml'
+  duc1:
+    block_desc: 'duc.yml'
+    parameters:
+      NUM_PORTS: 1
+  ddc1:
+    block_desc: 'ddc.yml'
+    parameters:
+        NUM_PORTS: 2
+  radio1:
+    block_desc: 'radio_2x64.yml'
+  fifo0:
+    block_desc: 'axi_ram_fifo_2x64.yml'
+    parameters:
+      # These parameters match the interface on the x300/X310
+      MEM_DATA_W: 64
+      MEM_ADDR_W: 30
+      FIFO_ADDR_BASE: "{30'h02000000, 30'h00000000}"
+      FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF}"
+      MEM_CLK_RATE: "300e6"
+  gain0:
+    block_desc: 'gain.yml'
 
 # A list of all static connections in design
 # ------------------------------------------
 # Format: A list of connection maps (list of key-value pairs) with the following keys
-#         - srcblk = Source block to connect
+#         - srcblk  = Source block to connect
 #         - srcport = Port on the source block to connect
-#         - dstblk = Destination block to connect
+#         - dstblk  = Destination block to connect
 #         - dstport = Port on the destination block to connect
 connections:
-    - { srcblk: ep0,  srcport: out0, dstblk: fifo0, dstport: port0 }
-    - { srcblk: fifo0,  srcport: port0, dstblk: duc0, dstport: port0 }
-    - { srcblk: duc0, srcport: port0, dstblk: radio0, dstport: port0 }
-    - { srcblk: radio0, srcport: port0, dstblk: ddc0,  dstport: port0 }
-    - { srcblk: radio0, srcport: port1, dstblk: ddc0,  dstport: port1 }
-    - { srcblk: ddc0, srcport: port0, dstblk: ep0,  dstport: in0 }
-    - { srcblk: ddc0, srcport: port1, dstblk: ep1,  dstport: in0 }
-    - { srcblk: ep2,  srcport: out0, dstblk: fifo0, dstport: port1 }
-    - { srcblk: fifo0,  srcport: port1, dstblk: duc1, dstport: port0 }
-    - { srcblk: duc1, srcport: port0, dstblk: radio1, dstport: port0 }
-    - { srcblk: radio1, srcport: port0, dstblk: ddc1,  dstport: port0 }
-    - { srcblk: radio1, srcport: port1, dstblk: ddc1,  dstport: port1 }
-    - { srcblk: ddc1, srcport: port0, dstblk: ep2,  dstport: in0 }
-    - { srcblk: ddc1, srcport: port1, dstblk: ep3,  dstport: in0 }
-    - { srcblk: ep4, srcport: out0, dstblk: gain0,  dstport: in }
-    - { srcblk: gain0, srcport: out, dstblk: ep4,  dstport: in0 }
-    - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 }
-    - { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio1 }
-    - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport: x300_radio }
-    - { srcblk: _device_, srcport: x300_radio1, dstblk: radio1, dstport: x300_radio }
-    - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper }
-    - { srcblk: _device_, srcport: time_keeper, dstblk: radio1, dstport: time_keeper }
-    - { srcblk: _device_, srcport: dram, dstblk: fifo0, dstport: axi_ram }
+  # ep0 to radio0(0) - RFA TX
+  - { srcblk: ep0,    srcport: out0,  dstblk: fifo0,  dstport: in_0 }
+  - { srcblk: fifo0,  srcport: out_0, dstblk: duc0,   dstport: in_0 }
+  - { srcblk: duc0,   srcport: out_0, dstblk: radio0, dstport: in_0 }
+  # radio0(0) to ep0 - RFA RX
+  - { srcblk: radio0, srcport: out_0, dstblk: ddc0,   dstport: in_0 }
+  - { srcblk: ddc0,   srcport: out_0, dstblk: ep0,    dstport: in0  }
+  # radio0(1) to ep1 - RFA RX
+  - { srcblk: radio0, srcport: out_1, dstblk: ddc0,   dstport: in_1 }
+  - { srcblk: ddc0,   srcport: out_1, dstblk: ep1,    dstport: in0  }
+  # ep2 to radio1(0) - RFB TX
+  - { srcblk: ep2,    srcport: out0,  dstblk: fifo0,  dstport: in_1 }
+  - { srcblk: fifo0,  srcport: out_1, dstblk: duc1,   dstport: in_0 }
+  - { srcblk: duc1,   srcport: out_0, dstblk: radio1, dstport: in_0 }
+  # radio1(0) to ep2 - RFB RX
+  - { srcblk: radio1, srcport: out_0, dstblk: ddc1,   dstport: in_0 }
+  - { srcblk: ddc1,   srcport: out_0, dstblk: ep2,    dstport: in0  }
+  # radio1(1) to ep3 - RFB RX
+  - { srcblk: radio1, srcport: out_1, dstblk: ddc1,   dstport: in_1 }
+  - { srcblk: ddc1,   srcport: out_1, dstblk: ep3,    dstport: in0  }
+  # ep4 to gain0 and gain0 to ep4
+  - { srcblk: ep4,    srcport: out0,  dstblk: gain0,  dstport: in   }
+  - { srcblk: gain0,  srcport: out,   dstblk: ep4,    dstport: in0  }
+  # BSP Connections
+  - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 }
+  - { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio1 }
+  - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport: x300_radio }
+  - { srcblk: _device_, srcport: x300_radio1, dstblk: radio1, dstport: x300_radio }
+  - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper }
+  - { srcblk: _device_, srcport: time_keeper, dstblk: radio1, dstport: time_keeper }
+  - { srcblk: _device_, srcport: dram, dstblk: fifo0, dstport: axi_ram }
 
 # A list of all clock domain connections in design
-# # ------------------------------------------
-# # Format: A list of connection maps (list of key-value pairs) with the following keys
-# #         - srcblk  = Source block to connect (Always "_device"_)
-# #         - srcport = Clock domain on the source block to connect
-# #         - dstblk  = Destination block to connect
-# #         - dstport = Clock domain on the destination block to connect
+# ------------------------------------------------
+# Format: A list of connection maps (list of key-value pairs) with the following keys
+#         - srcblk  = Source block to connect (Always "_device"_)
+#         - srcport = Clock domain on the source block to connect
+#         - dstblk  = Destination block to connect
+#         - dstport = Clock domain on the destination block to connect
 clk_domains:
-    - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
-    - { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
-    - { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
-    - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
-    - { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
-    - { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
+  - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
+  - { srcblk: _device_, srcport: ce,    dstblk: ddc0,   dstport: ce    }
+  - { srcblk: _device_, srcport: ce,    dstblk: duc0,   dstport: ce    }
+  - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
+  - { srcblk: _device_, srcport: ce,    dstblk: ddc1,   dstport: ce    }
+  - { srcblk: _device_, srcport: ce,    dstblk: duc1,   dstport: ce    }
+  - { srcblk: _device_, srcport: dram,  dstblk: fifo0,  dstport: mem   }