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| author | Wade Fife <wade.fife@ettus.com> | 2020-05-14 09:07:09 -0500 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2020-05-28 15:04:05 -0500 |
| commit | 5134b6caea58da825c4da1888a4d26888acc126a (patch) | |
| tree | fb576fa8af08a11325fce7eec1094eae6d0fa6d4 /host | |
| parent | 902c6f4488d5a75cf7a83cc1dc998d42703b0929 (diff) | |
| download | uhd-5134b6caea58da825c4da1888a4d26888acc126a.tar.gz uhd-5134b6caea58da825c4da1888a4d26888acc126a.tar.bz2 uhd-5134b6caea58da825c4da1888a4d26888acc126a.zip | |
fpga: rfnoc: Add RFNoC Add/Sub block
Diffstat (limited to 'host')
| -rw-r--r-- | host/include/uhd/rfnoc/blocks/addsub.yml | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/host/include/uhd/rfnoc/blocks/addsub.yml b/host/include/uhd/rfnoc/blocks/addsub.yml new file mode 100644 index 000000000..6e1bd671e --- /dev/null +++ b/host/include/uhd/rfnoc/blocks/addsub.yml @@ -0,0 +1,62 @@ +schema: rfnoc_modtool_args +module_name: addsub +version: 1.0 +rfnoc_version: 1.0 +chdr_width: 64 +noc_id: 0xADD00000 + +parameters: + USE_IMPL: '"Verilog"' + +clocks: + - name: rfnoc_chdr + freq: "[]" + - name: rfnoc_ctrl + freq: "[]" + - name: ce + freq: "[]" + +control: + sw_iface: nocscript + fpga_iface: axis_ctrl + interface_direction: slave + fifo_depth: 2 + clk_domain: rfnoc_ctrl + +data: + fpga_iface: axis_pyld_ctxt + clk_domain: ce + inputs: + in_a: + item_width: 32 + nipc: 1 + context_fifo_depth: 2 + payload_fifo_depth: 2 + format: sc16 + mdata_sig: ~ + in_b: + item_width: 32 + nipc: 1 + context_fifo_depth: 2 + payload_fifo_depth: 2 + format: sc16 + mdata_sig: ~ + outputs: + add: + item_width: 32 + nipc: 1 + context_fifo_depth: 2 + payload_fifo_depth: 2 + format: sc16 + mdata_sig: ~ + sub: + item_width: 32 + nipc: 1 + context_fifo_depth: 2 + payload_fifo_depth: 2 + format: sc16 + mdata_sig: ~ + +registers: + +properties: |