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| author | Josh Blum <josh@joshknows.com> | 2010-10-08 18:04:37 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-10-11 10:12:14 -0700 |
| commit | 37f1f1451f65aace9ca978ac3edcaa31d16e8c0d (patch) | |
| tree | 0573f4525e022bbdd6be25bb31d1100fbfe455e7 /host | |
| parent | 369c0e1dbc1518bd0fe2f81bec5e197d0c3bfe41 (diff) | |
| download | uhd-37f1f1451f65aace9ca978ac3edcaa31d16e8c0d.tar.gz uhd-37f1f1451f65aace9ca978ac3edcaa31d16e8c0d.tar.bz2 uhd-37f1f1451f65aace9ca978ac3edcaa31d16e8c0d.zip | |
usrp2: add fc control registers, use small timeout for control packets again
Diffstat (limited to 'host')
| -rw-r--r-- | host/lib/usrp/usrp2/usrp2_iface.cpp | 12 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/usrp2_regs.hpp | 5 |
2 files changed, 6 insertions, 11 deletions
diff --git a/host/lib/usrp/usrp2/usrp2_iface.cpp b/host/lib/usrp/usrp2/usrp2_iface.cpp index 2d450bfc6..6fdde7b2e 100644 --- a/host/lib/usrp/usrp2/usrp2_iface.cpp +++ b/host/lib/usrp/usrp2/usrp2_iface.cpp @@ -30,17 +30,7 @@ using namespace uhd; using namespace uhd::transport; -/*! - * FIXME: large timeout, ethernet pause frames... - * - * Use a large timeout to work-around the fact that - * flow-control may throttle outgoing control packets - * due to its use of ethernet pause frames. - * - * This will be fixed when host-based flow control is implemented, - * along with larger incoming send buffers using the on-board SRAM. - */ -static const size_t CONTROL_TIMEOUT_MS = 3000; //3 seconds +static const size_t CONTROL_TIMEOUT_MS = 200; class usrp2_iface_impl : public usrp2_iface{ public: diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index 064ad4e95..bdd5194f9 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -193,9 +193,14 @@ #define U2_REG_TX_CTRL_CLEAR_STATE _SR_ADDR(SR_TX_CTRL + 1) #define U2_REG_TX_CTRL_REPORT_SID _SR_ADDR(SR_TX_CTRL + 2) #define U2_REG_TX_CTRL_POLICY _SR_ADDR(SR_TX_CTRL + 3) +#define U2_REG_TX_CTRL_CYCLES_PER_ACK _SR_ADDR(SR_TX_CTRL + 4) +#define U2_REG_TX_CTRL_PACKETS_PER_ACK _SR_ADDR(SR_TX_CTRL + 5) #define U2_FLAG_TX_CTRL_POLICY_WAIT (0x1 << 0) #define U2_FLAG_TX_CTRL_POLICY_NEXT_PACKET (0x1 << 1) #define U2_FLAG_TX_CTRL_POLICY_NEXT_BURST (0x1 << 2) +//enable flag for registers: cycles and packets per ack +#define U2_FLAG_TX_CTRL_ACK_ENB (1ul << 31) + #endif /* INCLUDED_USRP2_REGS_HPP */ |