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| author | Sugandha Gupta <sugandha.gupta@ettus.com> | 2019-10-17 18:27:34 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2019-11-26 12:21:32 -0800 |
| commit | 3e2cceeaed7c3a2a70318dab695d6adb9ee5602e (patch) | |
| tree | 8967ee5d8470405630fc408d0d62156aaf01c781 /host/utils/bin/rfnoc_image_builder | |
| parent | 2da39536bb886f3f80858f531f86b95988e84bb3 (diff) | |
| download | uhd-3e2cceeaed7c3a2a70318dab695d6adb9ee5602e.tar.gz uhd-3e2cceeaed7c3a2a70318dab695d6adb9ee5602e.tar.bz2 uhd-3e2cceeaed7c3a2a70318dab695d6adb9ee5602e.zip | |
utils: image_builder: Fix ordering of noc_blocks, ports
The ports in the fpga need to be ordered to make correct
connections in verilog. This also keeps generated verilog
constant across runs.
Diffstat (limited to 'host/utils/bin/rfnoc_image_builder')
0 files changed, 0 insertions, 0 deletions