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| author | Sugandha Gupta <sugandha.gupta@ettus.com> | 2018-09-25 15:27:11 -0700 |
|---|---|---|
| committer | Brent Stapleton <bstapleton@g.hmc.edu> | 2018-09-26 14:10:23 -0700 |
| commit | 167be5318376a4a431f18f9f7779cb9cdab6d8f8 (patch) | |
| tree | 3582212d86b911d05089518538b9b0782fcba40e /host/tests/devtest/devtest_e320.py | |
| parent | d50e013646de654b5c82745eccbc6310be4bda5d (diff) | |
| download | uhd-167be5318376a4a431f18f9f7779cb9cdab6d8f8.tar.gz uhd-167be5318376a4a431f18f9f7779cb9cdab6d8f8.tar.bz2 uhd-167be5318376a4a431f18f9f7779cb9cdab6d8f8.zip | |
e320: devtest: Reduce sample rate for 1G devtest
The E320 default master clock rate is 16MHz, therefore we need to
reduce the 2 channel receive rate to 8MHz in order to be able to meet
the requested rate.
Diffstat (limited to 'host/tests/devtest/devtest_e320.py')
| -rw-r--r-- | host/tests/devtest/devtest_e320.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/host/tests/devtest/devtest_e320.py b/host/tests/devtest/devtest_e320.py index 3d08a2521..04d240e94 100644 --- a/host/tests/devtest/devtest_e320.py +++ b/host/tests/devtest/devtest_e320.py @@ -23,7 +23,7 @@ uhd_benchmark_rate_test.tests = { 'duration': 1, 'direction': 'tx,rx', 'chan': '0,1', - 'rate': 12.5e6, + 'rate': 8e6, 'acceptable-underruns': 500, 'tx_buffer': (0.1*12.5e6)+32e6*8*1/32, # 32 MB DRAM for each channel (32 bit OTW format), 'rx_buffer': 0.1*12.5e6, |