python: Add rfnoc_image_core.vh generation

This causes a header file, rfnoc_image_core.vh, to be generated along
with rfnoc_image_core.v so that parameters like the CHDR width can be
shared betweend RFNoC and the BSP.

2 files changed, 87 insertions, 1 deletions

diff --git a/host/python/uhd/imgbuilder/image_builder.py b/host/python/uhd/imgbuilder/image_builder.py
index 2521ee31c..1276ab693 100755
--- a/host/python/uhd/imgbuilder/image_builder.py
+++ b/host/python/uhd/imgbuilder/image_builder.py
@@ -675,6 +675,8 @@ def write_verilog(config, destination, source, source_hash):
     template engine.
     :param config: ImageBuilderConfig derived from script parameter
     :param destination: Filepath to write to
+    :param source: Filepath to the image YAML/GRC to generate from
+    :param source_hash: Source file hash value
     :return: None
     """
     template_dir = os.path.join(os.path.dirname(__file__), "templates")
@@ -700,6 +702,38 @@ def write_verilog(config, destination, source, source_hash):
         image_core_file.write(block)
 
 
+def write_verilog_header(config, destination, source, source_hash):
+    """
+    Generates rfnoc_image_core.vh file for the device.
+    :param config: ImageBuilderConfig derived from script parameter
+    :param destination: Filepath to write to
+    :param source: Filepath to the image YAML/GRC to generate from
+    :param source_hash: Source file hash value
+    :return: None
+    """
+    template_dir = os.path.join(os.path.dirname(__file__), "templates")
+    lookup = mako.lookup.TemplateLookup(directories=[template_dir])
+    tpl_filename = os.path.join(template_dir, "rfnoc_image_core.vh.mako")
+    tpl = mako.template.Template(
+        filename=tpl_filename,
+        lookup=lookup,
+        strict_undefined=True)
+
+    try:
+        block = tpl.render(**{
+            "config": config,
+            "source": source,
+            "source_hash": source_hash,
+            })
+    except:
+        print(exceptions.text_error_template().render())
+        sys.exit(1)
+
+    logging.info("Writing image core header to %s", destination)
+    with open(destination, "w") as image_core_file:
+        image_core_file.write(block)
+
+
 def write_build_env():
     """
     # TODO update Makefile entries according to used blocks
@@ -804,10 +838,23 @@ def generate_image_core_path(output_path, device, source):
     source: Otherwise, this path is returned, combined with a default file name
     """
     if output_path is not None:
-        return output_path
+        return os.path.splitext(output_path)[0] + '.v'
     source = os.path.split(os.path.abspath(os.path.normpath(source)))[0]
     return os.path.join(source, "{}_rfnoc_image_core.v".format(device))
 
+def generate_image_core_header_path(output_path, device, source):
+    """
+    Creates the path where the image core header file will be stored.
+
+    output_path: If not None, this is returned
+    device: Device type string, used to generate default file name
+    source: Otherwise, this path is returned, combined with a default file name
+    """
+    if output_path is not None:
+        return os.path.splitext(output_path)[0] + '.vh'
+    source = os.path.split(os.path.abspath(os.path.normpath(source)))[0]
+    return os.path.join(source, "{}_rfnoc_image_core.vh".format(device))
+
 def generate_edge_file_path(output_path, device, source):
     """
     Creates a valid path for the edge file to get stored.
@@ -843,11 +890,15 @@ def build_image(config, fpga_path, config_path, device, **args):
     image_core_path = \
         generate_image_core_path(
             args.get('output_path'), device, args.get('source'))
+    image_core_header_path = \
+        generate_image_core_header_path(
+            args.get('output_path'), device, args.get('source'))
     edge_file = \
         generate_edge_file_path(
             args.get('router_hex_path'), device, args.get('source'))
 
     logging.debug("Image core output file: %s", image_core_path)
+    logging.debug("Image core header output file: %s", image_core_header_path)
     logging.debug("Edge output file: %s", edge_file)
 
     core_config_path = get_core_config_path(config_path)
@@ -869,6 +920,11 @@ def build_image(config, fpga_path, config_path, device, **args):
         image_core_path,
         source=args.get('source'),
         source_hash=args.get('source_hash'))
+    write_verilog_header(
+        builder_conf,
+        image_core_header_path,
+        source=args.get('source'),
+        source_hash=args.get('source_hash'))
     write_build_env()
 
     if "generate_only" in args and args["generate_only"]:
diff --git a/host/python/uhd/imgbuilder/templates/rfnoc_image_core.vh.mako b/host/python/uhd/imgbuilder/templates/rfnoc_image_core.vh.mako
new file mode 100644
index 000000000..a9f8c8c4c
--- /dev/null
+++ b/host/python/uhd/imgbuilder/templates/rfnoc_image_core.vh.mako
@@ -0,0 +1,30 @@
+<%
+    import datetime
+    protover = config.rfnoc_version.split('.')
+    protover_major = protover[0];
+    protover_minor = protover[1];
+%>//
+// Copyright ${datetime.datetime.now().year} ${config.copyright}
+//
+// ${config.license}
+//
+// Header: rfnoc_image_core.vh (for ${config.device.type})
+//
+// Description:
+//
+//   This is the header file for the RFNoC Image Core.
+//
+//   This file was automatically generated by the RFNoC image builder tool.
+//   Re-running that tool will overwrite this file!
+//
+// File generated on: ${datetime.datetime.now().isoformat()}
+% if source:
+// Source: ${source}
+% endif
+% if source_hash:
+// Source SHA256: ${source_hash}
+% endif
+//
+
+`define CHDR_WIDTH     ${config.chdr_width}
+`define RFNOC_PROTOVER { 8'd${protover_major}, 8'd${protover_minor} }