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| author | Ashish Chaudhari <ashish@ettus.com> | 2015-07-21 17:18:33 -0700 |
|---|---|---|
| committer | Ashish Chaudhari <ashish@ettus.com> | 2015-07-22 11:26:28 -0700 |
| commit | a12b24027fe1af9ca51949f6a9333ac5451690ef (patch) | |
| tree | 76091ecc59bc4fd416fd954adf368069317385be /host/lib | |
| parent | edf041ee0353717fd3cde86dbe7621bc34812951 (diff) | |
| download | uhd-a12b24027fe1af9ca51949f6a9333ac5451690ef.tar.gz uhd-a12b24027fe1af9ca51949f6a9333ac5451690ef.tar.bz2 uhd-a12b24027fe1af9ca51949f6a9333ac5451690ef.zip | |
x300: Changed ADC clock swing to 1.6V from 0.7V
- This changed with the ADS62P44 -> ADS62P48 design change
Diffstat (limited to 'host/lib')
| -rw-r--r-- | host/lib/usrp/x300/x300_clock_ctrl.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/host/lib/usrp/x300/x300_clock_ctrl.cpp b/host/lib/usrp/x300/x300_clock_ctrl.cpp index 0812bcc8e..a8cc9b2b4 100644 --- a/host/lib/usrp/x300/x300_clock_ctrl.cpp +++ b/host/lib/usrp/x300/x300_clock_ctrl.cpp @@ -644,10 +644,10 @@ private: _lmk04816_regs.CLKout5_TYPE = lmk04816_regs_t::CLKOUT5_TYPE_LVPECL_700MVPP; //DB_0_TX _lmk04816_regs.CLKout6_TYPE = lmk04816_regs_t::CLKOUT6_TYPE_LVPECL_700MVPP; //DB0_DAC _lmk04816_regs.CLKout7_TYPE = lmk04816_regs_t::CLKOUT7_TYPE_LVPECL_700MVPP; //DB1_DAC - _lmk04816_regs.CLKout8_TYPE = lmk04816_regs_t::CLKOUT8_TYPE_LVPECL_700MVPP; //DB0_ADC + _lmk04816_regs.CLKout8_TYPE = lmk04816_regs_t::CLKOUT8_TYPE_LVPECL_1600MVPP; //DB0_ADC // Register 8 - _lmk04816_regs.CLKout9_TYPE = lmk04816_regs_t::CLKOUT9_TYPE_LVPECL_700MVPP; //DB1_ADC + _lmk04816_regs.CLKout9_TYPE = lmk04816_regs_t::CLKOUT9_TYPE_LVPECL_1600MVPP; //DB1_ADC _lmk04816_regs.CLKout10_TYPE = lmk04816_regs_t::CLKOUT10_TYPE_LVDS; //REF_CLKOUT _lmk04816_regs.CLKout11_TYPE = lmk04816_regs_t::CLKOUT11_TYPE_P_DOWN; //Debug header, use LVPECL |