fpga: lib: add Intel MAX10 architecture for 2clk FIFO

This commit derives parameters for MAX10 devices if provided by the
DEVICE parameter.

MAX10 devices FIFO generator support up to 36 bit wide FIFOs using
embedded memory (M9K) in simple dual port mode, which is treated
equally to RAM in the parameters.

In combination with sorting the ctrlport signals by usage, the used
resources can be reduced on the MAX10 devices from 6 to 3 M9K blocks
for a ctrlport_clk_cross instance without time and portids.

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