uhd: mpm: apply clang-format to all files

Applying formatting changes to all .cpp and .hpp files in the following
directories:
```
find host/examples/ -iname *.hpp -o -iname *.cpp | \
    xargs clang-format -i -style=file
find host/tests/ -iname *.hpp -o -iname *.cpp | \
    xargs clang-format -i -style=file
find host/lib/usrp/dboard/neon/ -iname *.hpp -o -iname *.cpp | \
    xargs clang-format -i -style=file
find host/lib/usrp/dboard/magnesium/ -iname *.hpp -o -iname *.cpp | \
    xargs clang-format -i -style=file
find host/lib/usrp/device3/ -iname *.hpp -o -iname *.cpp | \
    xargs clang-format -i -style=file
find host/lib/usrp/mpmd/ -iname *.hpp -o -iname *.cpp | \
    xargs clang-format -i -style=file
find host/lib/usrp/x300/ -iname *.hpp -o -iname *.cpp | \
    xargs clang-format -i -style=file
find host/utils/ -iname *.hpp -o -iname *.cpp | \
    xargs clang-format -i -style=file
find mpm/ -iname *.hpp -o -iname *.cpp | \
    xargs clang-format -i -style=file
```

Also formatted host/include/, except Cpp03 was used as a the language
standard instead of Cpp11.
```
sed -i 's/ Cpp11/ Cpp03/g' .clang-format
find host/include/ -iname *.hpp -o -iname *.cpp | \
    xargs clang-format -i -style=file
```

Formatting style was designated by the .clang-format file.

1 files changed, 85 insertions, 68 deletions

diff --git a/host/lib/usrp/x300/x300_dac_ctrl.cpp b/host/lib/usrp/x300/x300_dac_ctrl.cpp
index a9df96002..f951a44a2 100644
--- a/host/lib/usrp/x300/x300_dac_ctrl.cpp
+++ b/host/lib/usrp/x300/x300_dac_ctrl.cpp
@@ -7,11 +7,11 @@
 
 #include "x300_dac_ctrl.hpp"
 #include "x300_regs.hpp"
-#include <uhdlib/utils/system_time.hpp>
+#include <uhd/exception.hpp>
 #include <uhd/types/time_spec.hpp>
 #include <uhd/utils/log.hpp>
 #include <uhd/utils/safe_call.hpp>
-#include <uhd/exception.hpp>
+#include <uhdlib/utils/system_time.hpp>
 #include <boost/format.hpp>
 #include <chrono>
 #include <thread>
@@ -22,10 +22,12 @@ using namespace uhd;
 
 #define write_ad9146_reg(addr, data) \
     _iface->write_spi(_slaveno, spi_config_t::EDGE_RISE, ((addr) << 8) | (data), 16)
-#define read_ad9146_reg(addr) \
-    (_iface->read_spi(_slaveno, spi_config_t::EDGE_RISE, ((addr) << 8) | (1 << 15), 16) & 0xff)
+#define read_ad9146_reg(addr)                                                           \
+    (_iface->read_spi(_slaveno, spi_config_t::EDGE_RISE, ((addr) << 8) | (1 << 15), 16) \
+        & 0xff)
 
-x300_dac_ctrl::~x300_dac_ctrl(void){
+x300_dac_ctrl::~x300_dac_ctrl(void)
+{
     /* NOP */
 }
 
@@ -35,38 +37,41 @@ x300_dac_ctrl::~x300_dac_ctrl(void){
 class x300_dac_ctrl_impl : public x300_dac_ctrl
 {
 public:
-    x300_dac_ctrl_impl(uhd::spi_iface::sptr iface, const size_t slaveno, const double refclk):
-        _iface(iface), _slaveno(static_cast<int>(slaveno)), _refclk(refclk)
+    x300_dac_ctrl_impl(
+        uhd::spi_iface::sptr iface, const size_t slaveno, const double refclk)
+        : _iface(iface), _slaveno(static_cast<int>(slaveno)), _refclk(refclk)
     {
-        //Power up all DAC subsystems
-        write_ad9146_reg(0x01, 0x10); //Up: I DAC, Q DAC, Receiver, Voltage Ref, Clocks
-        write_ad9146_reg(0x02, 0x00); //No extended delays. Up: Voltage Ref, PLL, DAC, FIFO, Filters
+        // Power up all DAC subsystems
+        write_ad9146_reg(0x01, 0x10); // Up: I DAC, Q DAC, Receiver, Voltage Ref, Clocks
+        write_ad9146_reg(
+            0x02, 0x00); // No extended delays. Up: Voltage Ref, PLL, DAC, FIFO, Filters
 
         reset();
     }
 
     ~x300_dac_ctrl_impl(void)
     {
-        UHD_SAFE_CALL
-        (
-            //Power down all DAC subsystems
-            write_ad9146_reg(0x01, 0xEF); //Down: I DAC, Q DAC, Receiver, Voltage Ref, Clocks
-            write_ad9146_reg(0x02, 0x1F); //No extended delays. Down: Voltage Ref, PLL, DAC, FIFO, Filters
+        UHD_SAFE_CALL(
+            // Power down all DAC subsystems
+            write_ad9146_reg(
+                0x01, 0xEF); // Down: I DAC, Q DAC, Receiver, Voltage Ref, Clocks
+            write_ad9146_reg(0x02,
+                0x1F); // No extended delays. Down: Voltage Ref, PLL, DAC, FIFO, Filters
         )
     }
 
     void reset()
     {
-        //ADI recommendations:
+        // ADI recommendations:
         //- soft reset the chip before configuration
         //- put the chip in sleep mode during configuration and wake it up when done
         //- configure synchronization settings when sleeping
         _soft_reset();
         _sleep_mode(true);
         _init();
-        //We run backend sync regardless of whether we need to sync multiple DACs
-        //because we use the internal DAC FIFO to meet system synchronous timing
-        //and we need to guarantee that the FIFO is not empty.
+        // We run backend sync regardless of whether we need to sync multiple DACs
+        // because we use the internal DAC FIFO to meet system synchronous timing
+        // and we need to guarantee that the FIFO is not empty.
         _backend_sync();
         _sleep_mode(false);
     }
@@ -78,20 +83,20 @@ public:
             _check_pll();
             _check_dac_sync();
             return;
-        } catch (...) {}
+        } catch (...) {
+        }
 
         std::string err_str;
 
         // Try 3 times to sync before giving up
-        for (size_t retries = 0; retries < 3; retries++)
-        {
+        for (size_t retries = 0; retries < 3; retries++) {
             try {
                 _sleep_mode(true);
                 _init();
                 _backend_sync();
                 _sleep_mode(false);
                 return;
-            } catch (const uhd::runtime_error &e) {
+            } catch (const uhd::runtime_error& e) {
                 err_str = e.what();
             }
         }
@@ -114,23 +119,23 @@ public:
     //
     void _init()
     {
-        write_ad9146_reg(0x1e, 0x01);   //Datasheet: "Set 1 for proper operation"
-        write_ad9146_reg(0x06, 0xFF);   //Clear all event flags
+        write_ad9146_reg(0x1e, 0x01); // Datasheet: "Set 1 for proper operation"
+        write_ad9146_reg(0x06, 0xFF); // Clear all event flags
 
         // Calculate N0 to be VCO friendly.
         // Aim for VCO between 1 and 2GHz, assert otherwise.
         const int N1 = 4;
         int N0_val, N0;
-        for (N0_val = 0; N0_val < 3; N0_val++)
-        {
-            N0 = (1 << N0_val); //1, 2, 4
-            if ((_refclk * N0 * N1) >= 1e9) break;
+        for (N0_val = 0; N0_val < 3; N0_val++) {
+            N0 = (1 << N0_val); // 1, 2, 4
+            if ((_refclk * N0 * N1) >= 1e9)
+                break;
         }
         UHD_ASSERT_THROW((_refclk * N0 * N1) >= 1e9);
         UHD_ASSERT_THROW((_refclk * N0 * N1) <= 2e9);
 
         // Start PLL
-        write_ad9146_reg(0x06, 0xC0);   //Clear PLL event flags
+        write_ad9146_reg(0x06, 0xC0); // Clear PLL event flags
         write_ad9146_reg(0x0C, 0xD1); // Narrow PLL loop filter, Midrange charge pump.
         write_ad9146_reg(0x0D, 0xD1 | (N0_val << 2)); // N1=4, N2=16, N0 as calculated
         write_ad9146_reg(0x0A, 0xCF); // Auto init VCO band training as per datasheet
@@ -149,7 +154,7 @@ public:
         // - First transaction goes into low bits
         // - Second transaction goes into high bits
         //   therefore, we want Q to go first (bit 6 == 1)
-        write_ad9146_reg(0x03, (1 << 6)); //2s comp, i first, byte mode
+        write_ad9146_reg(0x03, (1 << 6)); // 2s comp, i first, byte mode
 
         // Configure interpolation filters
         write_ad9146_reg(0x1C, 0x00); // Configure HB1
@@ -165,31 +170,33 @@ public:
     //
     void _backend_sync(void)
     {
-        write_ad9146_reg(0x10, 0x40);   // Disable SYNC mode to reset state machines.
+        write_ad9146_reg(0x10, 0x40); // Disable SYNC mode to reset state machines.
 
-        //SYNC Settings:
+        // SYNC Settings:
         //- SYNC = Enabled
         //- Data Rate Mode: Synchronize at the rate at which data is consumed and not at
         //                  the granularity of the FIFO
         //- Falling edge sync: For the X300, DACCLK is generated using RefClk. Within the
         //                     DAC, the RefClk is sampled by DACCLK to sync interpolation
         //                     stages across multiple DACs. To ensure that we capture the
-        //                     RefClk when it is not transitioning, we sample on the falling
-        //                     edge of DACCLK
+        //                     RefClk when it is not transitioning, we sample on the
+        //                     falling edge of DACCLK
         //- Averaging = MAX
-        write_ad9146_reg(0x10, 0xC7);   // Enable SYNC mode. Falling edge sync. Averaging set to 128.
+        write_ad9146_reg(
+            0x10, 0xC7); // Enable SYNC mode. Falling edge sync. Averaging set to 128.
 
-        //Wait for backend SYNC state machine to lock before proceeding. This guarantees that the
-        //inputs and output of the FIFO have synchronized clocks
+        // Wait for backend SYNC state machine to lock before proceeding. This guarantees
+        // that the inputs and output of the FIFO have synchronized clocks
         _check_dac_sync();
 
-        //FIFO write pointer offset
-        //One of ADI's requirements to use data-rate synchronization in PLL mode is to meet
-        //setup and hold times for RefClk -> DCI clock which we *do not* currently meet in
-        //the FPGA. The DCI clock reaches a full RefClk cycle later which results in the
-        //FIFO popping before the first push. This results in a steady-state FIFO fullness
-        //of pointer - 1. To reach the optimal FIFO fullness of 4 we set the pointer to 5.
-        //FIXME: At some point we should meet timing on this interface
+        // FIFO write pointer offset
+        // One of ADI's requirements to use data-rate synchronization in PLL mode is to
+        // meet setup and hold times for RefClk -> DCI clock which we *do not* currently
+        // meet in the FPGA. The DCI clock reaches a full RefClk cycle later which results
+        // in the FIFO popping before the first push. This results in a steady-state FIFO
+        // fullness of pointer - 1. To reach the optimal FIFO fullness of 4 we set the
+        // pointer to 5.
+        // FIXME: At some point we should meet timing on this interface
         write_ad9146_reg(0x17, 0x05);
 
         // We are requesting a soft FIFO align just to put the FIFO
@@ -204,22 +211,23 @@ public:
     //
     void _check_pll()
     {
-        //Clear PLL event flags
+        // Clear PLL event flags
         write_ad9146_reg(0x06, 0xC0);
 
         // Verify PLL is Locked. 1 sec timeout.
         // NOTE: Data sheet inconsistent about which pins give PLL lock status. FIXME!
         const time_spec_t exit_time = uhd::get_system_time() + time_spec_t(1.0);
-        while (true)
-        {
+        while (true) {
             const size_t reg_e = read_ad9146_reg(0x0E); // PLL Status (Expect bit 7 = 1)
-            const size_t reg_6 = read_ad9146_reg(0x06); // Event Flags (Expect bit 7 = 0 and bit 6 = 1)
+            const size_t reg_6 =
+                read_ad9146_reg(0x06); // Event Flags (Expect bit 7 = 0 and bit 6 = 1)
             if ((((reg_e >> 7) & 0x1) == 0x1) && (((reg_6 >> 6) & 0x3) == 0x1))
                 break;
             if (exit_time < uhd::get_system_time())
-                throw uhd::runtime_error("x300_dac_ctrl: timeout waiting for DAC PLL to lock");
-            if (reg_6 & (1 << 7))               // Lock lost?
-                write_ad9146_reg(0x06, 0xC0);   // Clear PLL event flags
+                throw uhd::runtime_error(
+                    "x300_dac_ctrl: timeout waiting for DAC PLL to lock");
+            if (reg_6 & (1 << 7)) // Lock lost?
+                write_ad9146_reg(0x06, 0xC0); // Clear PLL event flags
             std::this_thread::sleep_for(std::chrono::milliseconds(10));
         }
     }
@@ -234,21 +242,25 @@ public:
         write_ad9146_reg(0x12, 0x00);
 
         const time_spec_t exit_time = uhd::get_system_time() + time_spec_t(1.0);
-        while (true)
-        {
-            std::this_thread::sleep_for(std::chrono::milliseconds(1));  // wait for sync to complete
-            const size_t reg_12 = read_ad9146_reg(0x12);    // Sync Status (Expect bit 7 = 0, bit 6 = 1)
-            const size_t reg_6 = read_ad9146_reg(0x06);     // Event Flags (Expect bit 5 = 0 and bit 4 = 1)
+        while (true) {
+            std::this_thread::sleep_for(
+                std::chrono::milliseconds(1)); // wait for sync to complete
+            const size_t reg_12 =
+                read_ad9146_reg(0x12); // Sync Status (Expect bit 7 = 0, bit 6 = 1)
+            const size_t reg_6 =
+                read_ad9146_reg(0x06); // Event Flags (Expect bit 5 = 0 and bit 4 = 1)
             if ((((reg_12 >> 6) & 0x3) == 0x1) && (((reg_6 >> 4) & 0x3) == 0x1))
                 break;
             if (exit_time < uhd::get_system_time())
-                throw uhd::runtime_error("x300_dac_ctrl: timeout waiting for backend synchronization");
+                throw uhd::runtime_error(
+                    "x300_dac_ctrl: timeout waiting for backend synchronization");
             if (reg_6 & (1 << 5))
-                write_ad9146_reg(0x06, 0x30);   // Clear Sync event flags
+                write_ad9146_reg(0x06, 0x30); // Clear Sync event flags
 #ifdef X300_DAC_RETRY_BACKEND_SYNC
-            if (reg_12 & (1 << 7)) {            // Sync acquired and lost?
-                write_ad9146_reg(0x10, 0xC7);   // Enable SYNC mode. Falling edge sync. Averaging set to 128.
-                write_ad9146_reg(0x12, 0x00);   // Clear Sync event flags
+            if (reg_12 & (1 << 7)) { // Sync acquired and lost?
+                write_ad9146_reg(0x10,
+                    0xC7); // Enable SYNC mode. Falling edge sync. Averaging set to 128.
+                write_ad9146_reg(0x12, 0x00); // Clear Sync event flags
             }
 #endif
         }
@@ -262,7 +274,11 @@ public:
         // Register 0x19 has a thermometer indicator of the FIFO depth
         const size_t reg_19 = read_ad9146_reg(0x19);
         if ((reg_19 & 0xFF) != 0xF) {
-            std::string msg((boost::format("x300_dac_ctrl: front-end sync failed. unexpected FIFO depth [0x%x]") % (reg_19 & 0xFF)).str());
+            std::string msg(
+                (boost::format(
+                     "x300_dac_ctrl: front-end sync failed. unexpected FIFO depth [0x%x]")
+                    % (reg_19 & 0xFF))
+                    .str());
             if (failure_is_fatal) {
                 throw uhd::runtime_error(msg);
             } else {
@@ -273,10 +289,10 @@ public:
 
     void _sleep_mode(bool sleep)
     {
-        uint8_t sleep_val = sleep ? (1<<7) : 0x00;
-        //Set sleep word and default fullscale value
-        write_ad9146_reg(0x41, sleep_val | 0x01);    //I DAC
-        write_ad9146_reg(0x45, sleep_val | 0x01);    //Q DAC
+        uint8_t sleep_val = sleep ? (1 << 7) : 0x00;
+        // Set sleep word and default fullscale value
+        write_ad9146_reg(0x41, sleep_val | 0x01); // I DAC
+        write_ad9146_reg(0x45, sleep_val | 0x01); // Q DAC
     }
 
     void _soft_reset()
@@ -294,7 +310,8 @@ private:
 /***********************************************************************
  * Public make function for the DAC control
  **********************************************************************/
-x300_dac_ctrl::sptr x300_dac_ctrl::make(uhd::spi_iface::sptr iface, const size_t slaveno, const double clock_rate)
+x300_dac_ctrl::sptr x300_dac_ctrl::make(
+    uhd::spi_iface::sptr iface, const size_t slaveno, const double clock_rate)
 {
     return sptr(new x300_dac_ctrl_impl(iface, slaveno, clock_rate));
 }