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| author | Josh Blum <josh@joshknows.com> | 2011-01-22 14:02:53 +0000 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-01-22 14:02:53 +0000 |
| commit | d27817a7ade49e74d29bf20a8ffa3ee35cbfe7ea (patch) | |
| tree | 70d71e0f82e55fef61a67a7e605f1115074318e1 /host/lib/usrp/usrp_e100/usrp_e100_regs.hpp | |
| parent | 2cb6092ddfcf5f3881faa455566d4f332b01d0ac (diff) | |
| download | uhd-d27817a7ade49e74d29bf20a8ffa3ee35cbfe7ea.tar.gz uhd-d27817a7ade49e74d29bf20a8ffa3ee35cbfe7ea.tar.bz2 uhd-d27817a7ade49e74d29bf20a8ffa3ee35cbfe7ea.zip | |
usrp-e100: changes for global reset and non-zero sids on rx
Diffstat (limited to 'host/lib/usrp/usrp_e100/usrp_e100_regs.hpp')
| -rw-r--r-- | host/lib/usrp/usrp_e100/usrp_e100_regs.hpp | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp b/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp index 7dc3a4ba8..a030462d0 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp @@ -126,6 +126,14 @@ #define UE_REG_SR_MISC_TEST32 UE_REG_SETTINGS_BASE_ADDR(52) ///////////////////////////////////////////////// +// Magic reset regs +//////////////////////////////////////////////// +#define UE_REG_CLEAR_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(48) + (4*(n))) +#define UE_REG_CLEAR_RX UE_REG_CLEAR_ADDR(0) +#define UE_REG_CLEAR_TX UE_REG_CLEAR_ADDR(1) +#define UE_REG_CLEAR_GLOBAL UE_REG_CLEAR_ADDR(2) + +///////////////////////////////////////////////// // DSP RX Regs //////////////////////////////////////////////// #define UE_REG_DSP_RX_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(16) + (4*(n))) @@ -145,7 +153,7 @@ #define UE_REG_CTRL_RX_STREAM_CMD UE_REG_CTRL_RX_ADDR(0) // {now, chain, num_samples(30) #define UE_REG_CTRL_RX_TIME_SECS UE_REG_CTRL_RX_ADDR(1) #define UE_REG_CTRL_RX_TIME_TICKS UE_REG_CTRL_RX_ADDR(2) -#define UE_REG_CTRL_RX_CLEAR_OVERRUN UE_REG_CTRL_RX_ADDR(3) // write anything to clear overrun +#define UE_REG_CTRL_RX_CLEAR UE_REG_CTRL_RX_ADDR(3) // write anything to clear #define UE_REG_CTRL_RX_VRT_HEADER UE_REG_CTRL_RX_ADDR(4) // word 0 of packet. FPGA fills in packet counter #define UE_REG_CTRL_RX_VRT_STREAM_ID UE_REG_CTRL_RX_ADDR(5) // word 1 of packet. #define UE_REG_CTRL_RX_VRT_TRAILER UE_REG_CTRL_RX_ADDR(6) @@ -167,7 +175,7 @@ //////////////////////////////////////////////// #define UE_REG_CTRL_TX_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(24) + (4*(n))) #define UE_REG_CTRL_TX_NCHANNELS UE_REG_CTRL_TX_ADDR(0) -#define UE_REG_CTRL_TX_CLEAR_UNDERRUN UE_REG_CTRL_TX_ADDR(1) +#define UE_REG_CTRL_TX_CLEAR UE_REG_CTRL_TX_ADDR(1) #define UE_REG_CTRL_TX_REPORT_SID UE_REG_CTRL_TX_ADDR(2) #define UE_REG_CTRL_TX_POLICY UE_REG_CTRL_TX_ADDR(3) |