Merge branch 'master' of git@ettus.sourcerepo.com:ettus/uhd into usrp_e

Conflicts:
	host/include/uhd/usrp/CMakeLists.txt

8 files changed, 388 insertions, 290 deletions

diff --git a/host/lib/usrp/usrp2/dboard_impl.cpp b/host/lib/usrp/usrp2/dboard_impl.cpp
index fd72aeaa4..30883cd50 100644
--- a/host/lib/usrp/usrp2/dboard_impl.cpp
+++ b/host/lib/usrp/usrp2/dboard_impl.cpp
@@ -15,10 +15,13 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
+
+#include "usrp2_impl.hpp"
+#include "usrp2_regs.hpp"
+#include <uhd/usrp/subdev_props.hpp>
+#include <uhd/usrp/dboard_props.hpp>
 #include <uhd/utils/assert.hpp>
-#include <uhd/types/clock_config.hpp>
 #include <boost/format.hpp>
-#include "usrp2_impl.hpp"
 
 using namespace uhd;
 using namespace uhd::usrp;
@@ -57,11 +60,13 @@ void usrp2_impl::dboard_init(void){
 
     //init the subdevs in use (use the first subdevice)
     _rx_subdevs_in_use = prop_names_t(1, _dboard_manager->get_rx_subdev_names().at(0));
+    update_rx_mux_config();
+
     _tx_subdevs_in_use = prop_names_t(1, _dboard_manager->get_tx_subdev_names().at(0));
-    update_mux_config();
+    update_tx_mux_config();
 }
 
-void usrp2_impl::update_mux_config(void){
+void usrp2_impl::update_rx_mux_config(void){
     //calculate the rx mux
     boost::uint32_t rx_mux = 0;
     ASSERT_THROW(_rx_subdevs_in_use.size() == 1);
@@ -76,6 +81,10 @@ void usrp2_impl::update_mux_config(void){
         rx_mux = (((rx_mux >> 0) & 0x3) << 2) | (((rx_mux >> 2) & 0x3) << 0);
     }
 
+    this->poke(FR_DSP_RX_MUX, rx_mux);
+}
+
+void usrp2_impl::update_tx_mux_config(void){
     //calculate the tx mux
     boost::uint32_t tx_mux = 0x10;
     ASSERT_THROW(_tx_subdevs_in_use.size() == 1);
@@ -85,15 +94,7 @@ void usrp2_impl::update_mux_config(void){
         tx_mux = (((tx_mux >> 0) & 0x1) << 1) | (((tx_mux >> 1) & 0x1) << 0);
     }
 
-    //setup the out data
-    usrp2_ctrl_data_t out_data;
-    out_data.id = htonl(USRP2_CTRL_ID_UPDATE_THOSE_MUX_SETTINGS_BRO);
-    out_data.data.mux_args.rx_mux = htonl(rx_mux);
-    out_data.data.mux_args.tx_mux = htonl(tx_mux);
-
-    //send and recv
-    usrp2_ctrl_data_t in_data = ctrl_send_and_recv(out_data);
-    ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_UPDATED_THE_MUX_SETTINGS_DUDE);
+    this->poke(FR_DSP_TX_MUX, tx_mux);
 }
 
 /***********************************************************************
@@ -129,7 +130,7 @@ void usrp2_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){
 void usrp2_impl::rx_dboard_set(const wax::obj &key, const wax::obj &val){
     if (key.as<dboard_prop_t>() == DBOARD_PROP_USED_SUBDEVS){
         _rx_subdevs_in_use = val.as<prop_names_t>();
-        update_mux_config(); //if the val is bad, this will throw
+        update_rx_mux_config(); //if the val is bad, this will throw
         return;
     }
 
@@ -169,7 +170,7 @@ void usrp2_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){
 void usrp2_impl::tx_dboard_set(const wax::obj &key, const wax::obj &val){
     if (key.as<dboard_prop_t>() == DBOARD_PROP_USED_SUBDEVS){
         _tx_subdevs_in_use = val.as<prop_names_t>();
-        update_mux_config(); //if the val is bad, this will throw
+        update_tx_mux_config(); //if the val is bad, this will throw
         return;
     }
 
diff --git a/host/lib/usrp/usrp2/dboard_interface.cpp b/host/lib/usrp/usrp2/dboard_interface.cpp
index 5a7d870b4..dcd6453a8 100644
--- a/host/lib/usrp/usrp2/dboard_interface.cpp
+++ b/host/lib/usrp/usrp2/dboard_interface.cpp
@@ -15,8 +15,12 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
-#include <uhd/utils/assert.hpp>
 #include "usrp2_impl.hpp"
+#include "usrp2_regs.hpp"
+#include <uhd/types/dict.hpp>
+#include <uhd/utils/assert.hpp>
+#include <boost/assign/list_of.hpp>
+#include <algorithm>
 
 using namespace uhd::usrp;
 
@@ -28,9 +32,8 @@ public:
     void write_aux_dac(unit_type_t, int, int);
     int read_aux_adc(unit_type_t, int);
 
-    void set_atr_reg(gpio_bank_t, boost::uint16_t, boost::uint16_t, boost::uint16_t);
+    void set_atr_reg(gpio_bank_t, atr_reg_t, boost::uint16_t);
     void set_gpio_ddr(gpio_bank_t, boost::uint16_t);
-    void write_gpio(gpio_bank_t, boost::uint16_t);
     boost::uint16_t read_gpio(gpio_bank_t);
 
     void write_i2c(int, const byte_vector_t &);
@@ -41,14 +44,21 @@ public:
 
 private:
     byte_vector_t transact_spi(
-        spi_dev_t dev,
-        spi_latch_t latch,
-        spi_push_t push,
-        const byte_vector_t &buf,
-        bool readback
+        spi_dev_t, spi_edge_t, const byte_vector_t &, bool
     );
 
     usrp2_impl *_impl;
+
+    //shadows
+    boost::uint32_t _ddr_shadow;
+    uhd::dict<atr_reg_t, uint32_t> _atr_reg_shadows;
+
+    //utilities
+    static int bank_to_shift(gpio_bank_t bank){
+        static const uhd::dict<gpio_bank_t, int> _bank_to_shift = \
+        boost::assign::map_list_of(GPIO_BANK_RX, 0)(GPIO_BANK_TX, 16);
+        return _bank_to_shift[bank];
+    }
 };
 
 /***********************************************************************
@@ -63,6 +73,7 @@ dboard_interface::sptr make_usrp2_dboard_interface(usrp2_impl *impl){
  **********************************************************************/
 usrp2_dboard_interface::usrp2_dboard_interface(usrp2_impl *impl){
     _impl = impl;
+    _ddr_shadow = 0;
 }
 
 usrp2_dboard_interface::~usrp2_dboard_interface(void){
@@ -83,70 +94,43 @@ double usrp2_dboard_interface::get_tx_clock_rate(void){
 /***********************************************************************
  * GPIO
  **********************************************************************/
-/*!
- * Static function to convert a gpio bank enum
- * to an over-the-wire value for the usrp2 control.
- * \param bank the dboard interface gpio bank enum
- * \return an over the wire representation
- */
-static boost::uint8_t gpio_bank_to_otw(dboard_interface::gpio_bank_t bank){
-    switch(bank){
-    case uhd::usrp::dboard_interface::GPIO_TX_BANK: return USRP2_DIR_TX;
-    case uhd::usrp::dboard_interface::GPIO_RX_BANK: return USRP2_DIR_RX;
-    }
-    throw std::invalid_argument("unknown gpio bank type");
-}
-
 void usrp2_dboard_interface::set_gpio_ddr(gpio_bank_t bank, boost::uint16_t value){
-    //setup the out data
-    usrp2_ctrl_data_t out_data;
-    out_data.id = htonl(USRP2_CTRL_ID_USE_THESE_GPIO_DDR_SETTINGS_BRO);
-    out_data.data.gpio_config.bank = gpio_bank_to_otw(bank);
-    out_data.data.gpio_config.value = htons(value);
-    out_data.data.gpio_config.mask = htons(0xffff);
-
-    //send and recv
-    usrp2_ctrl_data_t in_data = _impl->ctrl_send_and_recv(out_data);
-    ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_GOT_THE_GPIO_DDR_SETTINGS_DUDE);
-}
-
-void usrp2_dboard_interface::write_gpio(gpio_bank_t bank, boost::uint16_t value){
-    //setup the out data
-    usrp2_ctrl_data_t out_data;
-    out_data.id = htonl(USRP2_CTRL_ID_SET_YOUR_GPIO_PIN_OUTS_BRO);
-    out_data.data.gpio_config.bank = gpio_bank_to_otw(bank);
-    out_data.data.gpio_config.value = htons(value);
-    out_data.data.gpio_config.mask = htons(0xffff);
-
-    //send and recv
-    usrp2_ctrl_data_t in_data = _impl->ctrl_send_and_recv(out_data);
-    ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_I_SET_THE_GPIO_PIN_OUTS_DUDE);
+    //calculate the new 32 bit ddr value
+    int shift = bank_to_shift(bank);
+    boost::uint32_t new_ddr_val =
+        (_ddr_shadow & ~(boost::uint32_t(0xffff) << shift)) //zero out new bits
+        | (boost::uint32_t(value) << shift); //or'ed in the new bits
+
+    //poke in the value and shadow
+    _impl->poke(FR_GPIO_DDR, new_ddr_val);
+    _ddr_shadow = new_ddr_val;
 }
 
 boost::uint16_t usrp2_dboard_interface::read_gpio(gpio_bank_t bank){
-    //setup the out data
-    usrp2_ctrl_data_t out_data;
-    out_data.id = htonl(USRP2_CTRL_ID_GIVE_ME_YOUR_GPIO_PIN_VALS_BRO);
-    out_data.data.gpio_config.bank = gpio_bank_to_otw(bank);
-
-    //send and recv
-    usrp2_ctrl_data_t in_data = _impl->ctrl_send_and_recv(out_data);
-    ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_HERE_IS_YOUR_GPIO_PIN_VALS_DUDE);
-    return ntohs(in_data.data.gpio_config.value);
+    boost::uint32_t data = _impl->peek(FR_GPIO_IO);
+    return boost::uint16_t(data >> bank_to_shift(bank));
 }
 
-void usrp2_dboard_interface::set_atr_reg(gpio_bank_t bank, boost::uint16_t tx_value, boost::uint16_t rx_value, boost::uint16_t mask){
-    //setup the out data
-    usrp2_ctrl_data_t out_data;
-    out_data.id = htonl(USRP2_CTRL_ID_USE_THESE_ATR_SETTINGS_BRO);
-    out_data.data.atr_config.bank = gpio_bank_to_otw(bank);
-    out_data.data.atr_config.tx_value = htons(tx_value);
-    out_data.data.atr_config.rx_value = htons(rx_value);
-    out_data.data.atr_config.mask = htons(mask);
-
-    //send and recv
-    usrp2_ctrl_data_t in_data = _impl->ctrl_send_and_recv(out_data);
-    ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_GOT_THE_ATR_SETTINGS_DUDE);
+void usrp2_dboard_interface::set_atr_reg(gpio_bank_t bank, atr_reg_t reg, boost::uint16_t value){
+    //map the atr reg to an offset in register space
+    static const uhd::dict<atr_reg_t, int> reg_to_addr = boost::assign::map_list_of
+        (ATR_REG_IDLE, FR_ATR_IDLE) (ATR_REG_TX_ONLY, FR_ATR_TX)
+        (ATR_REG_RX_ONLY, FR_ATR_RX) (ATR_REG_FULL_DUPLEX, FR_ATR_FULL)
+    ;
+    ASSERT_THROW(reg_to_addr.has_key(reg));
+
+    //ensure a value exists in the shadow
+    if (not _atr_reg_shadows.has_key(reg)) _atr_reg_shadows[reg] = 0;
+
+    //calculate the new 32 bit atr value
+    int shift = bank_to_shift(bank);
+    boost::uint32_t new_atr_val =
+        (_atr_reg_shadows[reg] & ~(boost::uint32_t(0xffff) << shift)) //zero out new bits
+        | (boost::uint32_t(value) << shift); //or'ed in the new bits
+
+    //poke in the value and shadow
+    _impl->poke(reg_to_addr[reg], new_atr_val);
+    _atr_reg_shadows[reg] = new_atr_val;
 }
 
 /***********************************************************************
@@ -160,44 +144,29 @@ void usrp2_dboard_interface::set_atr_reg(gpio_bank_t bank, boost::uint16_t tx_va
  */
 static boost::uint8_t spi_dev_to_otw(dboard_interface::spi_dev_t dev){
     switch(dev){
-    case uhd::usrp::dboard_interface::SPI_TX_DEV: return USRP2_DIR_TX;
-    case uhd::usrp::dboard_interface::SPI_RX_DEV: return USRP2_DIR_RX;
+    case uhd::usrp::dboard_interface::SPI_DEV_TX: return SPI_SS_TX_DB;
+    case uhd::usrp::dboard_interface::SPI_DEV_RX: return SPI_SS_RX_DB;
     }
     throw std::invalid_argument("unknown spi device type");
 }
 
 /*!
- * Static function to convert a spi latch enum
+ * Static function to convert a spi edge enum
  * to an over-the-wire value for the usrp2 control.
- * \param latch the dboard interface spi latch enum
+ * \param edge the dboard interface spi edge enum
  * \return an over the wire representation
  */
-static boost::uint8_t spi_latch_to_otw(dboard_interface::spi_latch_t latch){
-    switch(latch){
-    case uhd::usrp::dboard_interface::SPI_LATCH_RISE: return USRP2_CLK_EDGE_RISE;
-    case uhd::usrp::dboard_interface::SPI_LATCH_FALL: return USRP2_CLK_EDGE_FALL;
+static boost::uint8_t spi_edge_to_otw(dboard_interface::spi_edge_t edge){
+    switch(edge){
+    case uhd::usrp::dboard_interface::SPI_EDGE_RISE: return USRP2_CLK_EDGE_RISE;
+    case uhd::usrp::dboard_interface::SPI_EDGE_FALL: return USRP2_CLK_EDGE_FALL;
     }
-    throw std::invalid_argument("unknown spi latch type");
-}
-
-/*!
- * Static function to convert a spi push enum
- * to an over-the-wire value for the usrp2 control.
- * \param push the dboard interface spi push enum
- * \return an over the wire representation
- */
-static boost::uint8_t spi_push_to_otw(dboard_interface::spi_push_t push){
-    switch(push){
-    case uhd::usrp::dboard_interface::SPI_PUSH_RISE: return USRP2_CLK_EDGE_RISE;
-    case uhd::usrp::dboard_interface::SPI_PUSH_FALL: return USRP2_CLK_EDGE_FALL;
-    }
-    throw std::invalid_argument("unknown spi push type");
+    throw std::invalid_argument("unknown spi edge type");
 }
 
 dboard_interface::byte_vector_t usrp2_dboard_interface::transact_spi(
     spi_dev_t dev,
-    spi_latch_t latch,
-    spi_push_t push,
+    spi_edge_t edge,
     const byte_vector_t &buf,
     bool readback
 ){
@@ -205,8 +174,7 @@ dboard_interface::byte_vector_t usrp2_dboard_interface::transact_spi(
     usrp2_ctrl_data_t out_data;
     out_data.id = htonl(USRP2_CTRL_ID_TRANSACT_ME_SOME_SPI_BRO);
     out_data.data.spi_args.dev = spi_dev_to_otw(dev);
-    out_data.data.spi_args.latch = spi_latch_to_otw(latch);
-    out_data.data.spi_args.push = spi_push_to_otw(push);
+    out_data.data.spi_args.edge = spi_edge_to_otw(edge);
     out_data.data.spi_args.readback = (readback)? 1 : 0;
     out_data.data.spi_args.bytes = buf.size();
 
@@ -214,9 +182,7 @@ dboard_interface::byte_vector_t usrp2_dboard_interface::transact_spi(
     ASSERT_THROW(buf.size() <= sizeof(out_data.data.spi_args.data));
 
     //copy in the data
-    for (size_t i = 0; i < buf.size(); i++){
-        out_data.data.spi_args.data[i] = buf[i];
-    }
+    std::copy(buf.begin(), buf.end(), out_data.data.spi_args.data);
 
     //send and recv
     usrp2_ctrl_data_t in_data = _impl->ctrl_send_and_recv(out_data);
@@ -224,10 +190,8 @@ dboard_interface::byte_vector_t usrp2_dboard_interface::transact_spi(
     ASSERT_THROW(in_data.data.spi_args.bytes == buf.size());
 
     //copy out the data
-    byte_vector_t result;
-    for (size_t i = 0; i < buf.size(); i++){
-        result.push_back(in_data.data.spi_args.data[i]);
-    }
+    byte_vector_t result(buf.size());
+    std::copy(in_data.data.spi_args.data, in_data.data.spi_args.data + buf.size(), result.begin());
     return result;
 }
 
@@ -245,9 +209,7 @@ void usrp2_dboard_interface::write_i2c(int i2c_addr, const byte_vector_t &buf){
     ASSERT_THROW(buf.size() <= sizeof(out_data.data.i2c_args.data));
 
     //copy in the data
-    for (size_t i = 0; i < buf.size(); i++){
-        out_data.data.i2c_args.data[i] = buf[i];
-    }
+    std::copy(buf.begin(), buf.end(), out_data.data.i2c_args.data);
 
     //send and recv
     usrp2_ctrl_data_t in_data = _impl->ctrl_send_and_recv(out_data);
@@ -270,10 +232,8 @@ dboard_interface::byte_vector_t usrp2_dboard_interface::read_i2c(int i2c_addr, s
     ASSERT_THROW(in_data.data.i2c_args.addr = num_bytes);
 
     //copy out the data
-    byte_vector_t result;
-    for (size_t i = 0; i < num_bytes; i++){
-        result.push_back(in_data.data.i2c_args.data[i]);
-    }
+    byte_vector_t result(num_bytes);
+    std::copy(in_data.data.i2c_args.data, in_data.data.i2c_args.data + num_bytes, result.begin());
     return result;
 }
 
diff --git a/host/lib/usrp/usrp2/dsp_impl.cpp b/host/lib/usrp/usrp2/dsp_impl.cpp
index 0d43fac0e..d70248682 100644
--- a/host/lib/usrp/usrp2/dsp_impl.cpp
+++ b/host/lib/usrp/usrp2/dsp_impl.cpp
@@ -15,13 +15,16 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
+#include "usrp2_impl.hpp"
+#include "usrp2_regs.hpp"
+#include <uhd/usrp/dsp_props.hpp>
 #include <uhd/utils/assert.hpp>
 #include <boost/format.hpp>
 #include <boost/assign/list_of.hpp>
 #include <boost/math/special_functions/round.hpp>
-#include "usrp2_impl.hpp"
 
 using namespace uhd;
+using namespace uhd::usrp;
 
 static const size_t default_decim = 16;
 static const size_t default_interp = 16;
@@ -64,25 +67,22 @@ void usrp2_impl::init_ddc_config(void){
     update_ddc_config();
 
     //initial command that kills streaming (in case if was left on)
-    //issue_ddc_stream_cmd(TODO)
+    stream_cmd_t stream_cmd_off;
+    stream_cmd_off.stream_now = true;
+    stream_cmd_off.continuous = false;
+    stream_cmd_off.num_samps = 0;
+    issue_ddc_stream_cmd(stream_cmd_off);
 }
 
 void usrp2_impl::update_ddc_config(void){
-    //setup the out data
-    usrp2_ctrl_data_t out_data;
-    out_data.id = htonl(USRP2_CTRL_ID_SETUP_THIS_DDC_FOR_ME_BRO);
-    out_data.data.ddc_args.freq_word = htonl(
-        calculate_freq_word_and_update_actual_freq(_ddc_freq, get_master_clock_freq())
-    );
-    out_data.data.ddc_args.decim = htonl(_ddc_decim);
+    //set the decimation
+    this->poke(FR_DSP_RX_DECIM_RATE, _ddc_decim);
+
+    //set the scaling
     static const boost::int16_t default_rx_scale_iq = 1024;
-    out_data.data.ddc_args.scale_iq = htonl(
+    this->poke(FR_DSP_RX_SCALE_IQ,
         calculate_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq)
     );
-
-    //send and recv
-    usrp2_ctrl_data_t in_data = ctrl_send_and_recv(out_data);
-    ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_TOTALLY_SETUP_THE_DDC_DUDE);
 }
 
 void usrp2_impl::issue_ddc_stream_cmd(const stream_cmd_t &stream_cmd){
@@ -172,7 +172,9 @@ void usrp2_impl::ddc_set(const wax::obj &key, const wax::obj &val){
         ASSERT_THROW(new_freq <= get_master_clock_freq()/2.0);
         ASSERT_THROW(new_freq >= -get_master_clock_freq()/2.0);
         _ddc_freq = new_freq; //shadow
-        update_ddc_config();
+        this->poke(FR_DSP_RX_FREQ,
+            calculate_freq_word_and_update_actual_freq(_ddc_freq, get_master_clock_freq())
+        );
         return;
     }
     else if (key_name == "stream_cmd"){
@@ -210,20 +212,11 @@ void usrp2_impl::update_duc_config(void){
     double interp_cubed = std::pow(double(tmp_interp), 3);
     boost::int16_t scale = rint((4096*std::pow(2, ceil(log2(interp_cubed))))/(1.65*interp_cubed));
 
-    //setup the out data
-    usrp2_ctrl_data_t out_data;
-    out_data.id = htonl(USRP2_CTRL_ID_SETUP_THIS_DUC_FOR_ME_BRO);
-    out_data.data.duc_args.freq_word = htonl(
-        calculate_freq_word_and_update_actual_freq(_duc_freq, get_master_clock_freq())
-    );
-    out_data.data.duc_args.interp = htonl(_duc_interp);
-    out_data.data.duc_args.scale_iq = htonl(
-        calculate_iq_scale_word(scale, scale)
-    );
+    //set the interpolation
+    this->poke(FR_DSP_TX_INTERP_RATE, _ddc_decim);
 
-    //send and recv
-    usrp2_ctrl_data_t in_data = ctrl_send_and_recv(out_data);
-    ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_TOTALLY_SETUP_THE_DUC_DUDE);
+    //set the scaling
+    this->poke(FR_DSP_TX_SCALE_IQ, calculate_iq_scale_word(scale, scale));
 }
 
 /***********************************************************************
@@ -297,7 +290,9 @@ void usrp2_impl::duc_set(const wax::obj &key, const wax::obj &val){
         ASSERT_THROW(new_freq <= get_master_clock_freq()/2.0);
         ASSERT_THROW(new_freq >= -get_master_clock_freq()/2.0);
         _duc_freq = new_freq; //shadow
-        update_duc_config();
+        this->poke(FR_DSP_TX_FREQ,
+            calculate_freq_word_and_update_actual_freq(_duc_freq, get_master_clock_freq())
+        );
         return;
     }
 
diff --git a/host/lib/usrp/usrp2/fw_common.h b/host/lib/usrp/usrp2/fw_common.h
index 30fee6c32..c168614ee 100644
--- a/host/lib/usrp/usrp2/fw_common.h
+++ b/host/lib/usrp/usrp2/fw_common.h
@@ -45,87 +45,50 @@ extern "C" {
 #define USRP2_UDP_DATA_PORT 49153
 
 typedef enum{
-    USRP2_CTRL_ID_HUH_WHAT,
+    USRP2_CTRL_ID_HUH_WHAT = ' ',
     //USRP2_CTRL_ID_FOR_SURE, //TODO error condition enums
     //USRP2_CTRL_ID_SUX_MAN,
 
-    USRP2_CTRL_ID_GIVE_ME_YOUR_IP_ADDR_BRO,
-    USRP2_CTRL_ID_THIS_IS_MY_IP_ADDR_DUDE,
-    USRP2_CTRL_ID_HERE_IS_A_NEW_IP_ADDR_BRO,
+    USRP2_CTRL_ID_GIVE_ME_YOUR_IP_ADDR_BRO = 'a',
+    USRP2_CTRL_ID_THIS_IS_MY_IP_ADDR_DUDE = 'A',
+    USRP2_CTRL_ID_HERE_IS_A_NEW_IP_ADDR_BRO = 'b',
 
-    USRP2_CTRL_ID_GIVE_ME_YOUR_MAC_ADDR_BRO,
-    USRP2_CTRL_ID_THIS_IS_MY_MAC_ADDR_DUDE,
-    USRP2_CTRL_ID_HERE_IS_A_NEW_MAC_ADDR_BRO,
+    USRP2_CTRL_ID_GIVE_ME_YOUR_MAC_ADDR_BRO = 'm',
+    USRP2_CTRL_ID_THIS_IS_MY_MAC_ADDR_DUDE = 'M',
+    USRP2_CTRL_ID_HERE_IS_A_NEW_MAC_ADDR_BRO = 'n',
 
-    USRP2_CTRL_ID_GIVE_ME_YOUR_DBOARD_IDS_BRO,
-    USRP2_CTRL_ID_THESE_ARE_MY_DBOARD_IDS_DUDE,
+    USRP2_CTRL_ID_GIVE_ME_YOUR_DBOARD_IDS_BRO = 'd',
+    USRP2_CTRL_ID_THESE_ARE_MY_DBOARD_IDS_DUDE = 'D',
 
-    USRP2_CTRL_ID_HERES_A_NEW_CLOCK_CONFIG_BRO,
-    USRP2_CTRL_ID_GOT_THE_NEW_CLOCK_CONFIG_DUDE,
+    USRP2_CTRL_ID_TRANSACT_ME_SOME_SPI_BRO = 's',
+    USRP2_CTRL_ID_OMG_TRANSACTED_SPI_DUDE = 'S',
 
-    USRP2_CTRL_ID_USE_THESE_GPIO_DDR_SETTINGS_BRO,
-    USRP2_CTRL_ID_GOT_THE_GPIO_DDR_SETTINGS_DUDE,
+    USRP2_CTRL_ID_DO_AN_I2C_READ_FOR_ME_BRO = 'i',
+    USRP2_CTRL_ID_HERES_THE_I2C_DATA_DUDE = 'I',
 
-    USRP2_CTRL_ID_SET_YOUR_GPIO_PIN_OUTS_BRO,
-    USRP2_CTRL_ID_I_SET_THE_GPIO_PIN_OUTS_DUDE,
+    USRP2_CTRL_ID_WRITE_THESE_I2C_VALUES_BRO = 'h',
+    USRP2_CTRL_ID_COOL_IM_DONE_I2C_WRITE_DUDE = 'H',
 
-    USRP2_CTRL_ID_GIVE_ME_YOUR_GPIO_PIN_VALS_BRO,
-    USRP2_CTRL_ID_HERE_IS_YOUR_GPIO_PIN_VALS_DUDE,
+    USRP2_CTRL_ID_WRITE_THIS_TO_THE_AUX_DAC_BRO = 'x',
+    USRP2_CTRL_ID_DONE_WITH_THAT_AUX_DAC_DUDE = 'X',
 
-    USRP2_CTRL_ID_USE_THESE_ATR_SETTINGS_BRO,
-    USRP2_CTRL_ID_GOT_THE_ATR_SETTINGS_DUDE,
+    USRP2_CTRL_ID_READ_FROM_THIS_AUX_ADC_BRO = 'y',
+    USRP2_CTRL_ID_DONE_WITH_THAT_AUX_ADC_DUDE = 'Y',
 
-    USRP2_CTRL_ID_TRANSACT_ME_SOME_SPI_BRO,
-    USRP2_CTRL_ID_OMG_TRANSACTED_SPI_DUDE,
+    USRP2_CTRL_ID_SEND_STREAM_COMMAND_FOR_ME_BRO = '{',
+    USRP2_CTRL_ID_GOT_THAT_STREAM_COMMAND_DUDE = '}',
 
-    USRP2_CTRL_ID_DO_AN_I2C_READ_FOR_ME_BRO,
-    USRP2_CTRL_ID_HERES_THE_I2C_DATA_DUDE,
+    USRP2_CTRL_ID_POKE_THIS_REGISTER_FOR_ME_BRO = 'p',
+    USRP2_CTRL_ID_OMG_POKED_REGISTER_SO_BAD_DUDE = 'P',
 
-    USRP2_CTRL_ID_WRITE_THESE_I2C_VALUES_BRO,
-    USRP2_CTRL_ID_COOL_IM_DONE_I2C_WRITE_DUDE,
+    USRP2_CTRL_ID_PEEK_AT_THIS_REGISTER_FOR_ME_BRO = 'r',
+    USRP2_CTRL_ID_WOAH_I_DEFINITELY_PEEKED_IT_DUDE = 'R',
 
-    USRP2_CTRL_ID_WRITE_THIS_TO_THE_AUX_DAC_BRO,
-    USRP2_CTRL_ID_DONE_WITH_THAT_AUX_DAC_DUDE,
-
-    USRP2_CTRL_ID_READ_FROM_THIS_AUX_ADC_BRO,
-    USRP2_CTRL_ID_DONE_WITH_THAT_AUX_ADC_DUDE,
-
-    USRP2_CTRL_ID_SETUP_THIS_DDC_FOR_ME_BRO,
-    USRP2_CTRL_ID_TOTALLY_SETUP_THE_DDC_DUDE,
-
-    USRP2_CTRL_ID_SEND_STREAM_COMMAND_FOR_ME_BRO,
-    USRP2_CTRL_ID_GOT_THAT_STREAM_COMMAND_DUDE,
-
-    USRP2_CTRL_ID_SETUP_THIS_DUC_FOR_ME_BRO,
-    USRP2_CTRL_ID_TOTALLY_SETUP_THE_DUC_DUDE,
-
-    USRP2_CTRL_ID_GOT_A_NEW_TIME_FOR_YOU_BRO,
-    USRP2_CTRL_ID_SWEET_I_GOT_THAT_TIME_DUDE,
-
-    USRP2_CTRL_ID_UPDATE_THOSE_MUX_SETTINGS_BRO,
-    USRP2_CTRL_ID_UPDATED_THE_MUX_SETTINGS_DUDE,
-
-    USRP2_CTRL_ID_PEACE_OUT
+    USRP2_CTRL_ID_PEACE_OUT = '~'
 
 } usrp2_ctrl_id_t;
 
 typedef enum{
-    USRP2_PPS_SOURCE_SMA,
-    USRP2_PPS_SOURCE_MIMO
-} usrp2_pps_source_t;
-
-typedef enum{
-    USRP2_PPS_POLARITY_POS,
-    USRP2_PPS_POLARITY_NEG
-} usrp2_pps_polarity_t;
-
-typedef enum{
-    USRP2_REF_SOURCE_INT,
-    USRP2_REF_SOURCE_SMA,
-    USRP2_REF_SOURCE_MIMO
-} usrp2_ref_source_t;
-
-typedef enum{
     USRP2_DIR_RX,
     USRP2_DIR_TX
 } usrp2_dir_which_t;
@@ -146,28 +109,8 @@ typedef struct{
             _SINS_ uint16_t tx_id;
         } dboard_ids;
         struct {
-            _SINS_ uint8_t pps_source;
-            _SINS_ uint8_t pps_polarity;
-            _SINS_ uint8_t ref_source;
-            _SINS_ uint8_t _pad;
-        } clock_config;
-        struct {
-            _SINS_ uint8_t bank;
-            _SINS_ uint8_t _pad[3];
-            _SINS_ uint16_t value;
-            _SINS_ uint16_t mask;
-        } gpio_config;
-        struct {
-            _SINS_ uint8_t bank;
-            _SINS_ uint8_t _pad[3];
-            _SINS_ uint16_t tx_value;
-            _SINS_ uint16_t rx_value;
-            _SINS_ uint16_t mask;
-        } atr_config;
-        struct {
             _SINS_ uint8_t dev;
-            _SINS_ uint8_t latch;
-            _SINS_ uint8_t push;
+            _SINS_ uint8_t edge;
             _SINS_ uint8_t readback;
             _SINS_ uint8_t bytes;
             _SINS_ uint8_t data[sizeof(_SINS_ uint32_t)];
@@ -184,11 +127,6 @@ typedef struct{
             _SINS_ uint32_t value;
         } aux_args;
         struct {
-            _SINS_ uint32_t freq_word;
-            _SINS_ uint32_t decim;
-            _SINS_ uint32_t scale_iq;
-        } ddc_args;
-        struct {
             _SINS_ uint8_t now; //stream now?
             _SINS_ uint8_t continuous; //auto-reload commmands?
             _SINS_ uint8_t _pad[2];
@@ -197,19 +135,9 @@ typedef struct{
             _SINS_ uint32_t num_samps;
         } stream_cmd;
         struct {
-            _SINS_ uint32_t freq_word;
-            _SINS_ uint32_t interp;
-            _SINS_ uint32_t scale_iq;
-        } duc_args;
-        struct {
-            _SINS_ uint32_t secs;
-            _SINS_ uint32_t ticks;
-            _SINS_ uint8_t now;
-        } time_args;
-        struct {
-            _SINS_ uint32_t rx_mux;
-            _SINS_ uint32_t tx_mux;
-        } mux_args;
+            _SINS_ uint32_t addr;
+            _SINS_ uint32_t data;
+        } poke_args;
     } data;
 } usrp2_ctrl_data_t;
 
diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp
index 35dfd6287..7594c85fa 100644
--- a/host/lib/usrp/usrp2/mboard_impl.cpp
+++ b/host/lib/usrp/usrp2/mboard_impl.cpp
@@ -15,11 +15,15 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
+#include "usrp2_impl.hpp"
+#include "usrp2_regs.hpp"
+#include <uhd/usrp/mboard_props.hpp>
 #include <uhd/utils/assert.hpp>
 #include <uhd/types/mac_addr.hpp>
-#include "usrp2_impl.hpp"
+#include <uhd/types/dict.hpp>
 
 using namespace uhd;
+using namespace uhd::usrp;
 
 /***********************************************************************
  * Helper Methods
@@ -46,55 +50,36 @@ void usrp2_impl::init_clock_config(void){
 }
 
 void usrp2_impl::update_clock_config(void){
-    //setup the out data
-    usrp2_ctrl_data_t out_data;
-    out_data.id = htonl(USRP2_CTRL_ID_HERES_A_NEW_CLOCK_CONFIG_BRO);
-
-    //translate ref source enums
-    switch(_clock_config.ref_source){
-    case clock_config_t::REF_INT:
-        out_data.data.clock_config.ref_source = USRP2_REF_SOURCE_INT; break;
-    case clock_config_t::REF_SMA:
-        out_data.data.clock_config.ref_source = USRP2_REF_SOURCE_SMA; break;
-    case clock_config_t::REF_MIMO:
-        out_data.data.clock_config.ref_source = USRP2_REF_SOURCE_MIMO; break;
-    default: throw std::runtime_error("usrp2: unhandled clock configuration ref source");
-    }
+    boost::uint32_t pps_flags = 0;
 
     //translate pps source enums
     switch(_clock_config.pps_source){
-    case clock_config_t::PPS_SMA:
-        out_data.data.clock_config.pps_source = USRP2_PPS_SOURCE_SMA; break;
-    case clock_config_t::PPS_MIMO:
-        out_data.data.clock_config.pps_source = USRP2_PPS_SOURCE_MIMO; break;
+    case clock_config_t::PPS_SMA:  pps_flags |= FRF_TIME64_PPS_SMA;  break;
+    case clock_config_t::PPS_MIMO: pps_flags |= FRF_TIME64_PPS_MIMO; break;
     default: throw std::runtime_error("usrp2: unhandled clock configuration pps source");
     }
 
     //translate pps polarity enums
     switch(_clock_config.pps_polarity){
-    case clock_config_t::PPS_POS:
-        out_data.data.clock_config.pps_source = USRP2_PPS_POLARITY_POS; break;
-    case clock_config_t::PPS_NEG:
-        out_data.data.clock_config.pps_source = USRP2_PPS_POLARITY_NEG; break;
+    case clock_config_t::PPS_POS: pps_flags |= FRF_TIME64_PPS_POSEDGE; break;
+    case clock_config_t::PPS_NEG: pps_flags |= FRF_TIME64_PPS_NEGEDGE; break;
     default: throw std::runtime_error("usrp2: unhandled clock configuration pps polarity");
     }
 
-    //send and recv
-    usrp2_ctrl_data_t in_data = ctrl_send_and_recv(out_data);
-    ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_GOT_THE_NEW_CLOCK_CONFIG_DUDE);
+    //set the pps flags
+    this->poke(FR_TIME64_FLAGS, pps_flags);
+
+    //TODO clock source ref 10mhz (spi ad9510)
 }
 
 void usrp2_impl::set_time_spec(const time_spec_t &time_spec, bool now){
-    //setup the out data
-    usrp2_ctrl_data_t out_data;
-    out_data.id = htonl(USRP2_CTRL_ID_GOT_A_NEW_TIME_FOR_YOU_BRO);
-    out_data.data.time_args.secs  = htonl(time_spec.secs);
-    out_data.data.time_args.ticks = htonl(time_spec.ticks);
-    out_data.data.time_args.now   = (now)? 1 : 0;
-
-    //send and recv
-    usrp2_ctrl_data_t in_data = ctrl_send_and_recv(out_data);
-    ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_SWEET_I_GOT_THAT_TIME_DUDE);
+    //set ticks and seconds
+    this->poke(FR_TIME64_SECS, time_spec.secs);
+    this->poke(FR_TIME64_TICKS, time_spec.ticks);
+
+    //set the register to latch it all in
+    boost::uint32_t imm_flags = (now)? FRF_TIME64_LATCH_NOW : FRF_TIME64_LATCH_NEXT_PPS;
+    this->poke(FR_TIME64_IMM, imm_flags);
 }
 
 /***********************************************************************
diff --git a/host/lib/usrp/usrp2/usrp2_impl.cpp b/host/lib/usrp/usrp2/usrp2_impl.cpp
index b0ee395fb..b3a22e175 100644
--- a/host/lib/usrp/usrp2/usrp2_impl.cpp
+++ b/host/lib/usrp/usrp2/usrp2_impl.cpp
@@ -16,6 +16,7 @@
 //
 
 #include <uhd/transport/if_addrs.hpp>
+#include <uhd/usrp/device_props.hpp>
 #include <uhd/utils/assert.hpp>
 #include <uhd/utils/static.hpp>
 #include <boost/format.hpp>
@@ -173,6 +174,30 @@ double usrp2_impl::get_master_clock_freq(void){
     return 100e6;
 }
 
+void usrp2_impl::poke(boost::uint32_t addr, boost::uint32_t data){
+    //setup the out data
+    usrp2_ctrl_data_t out_data;
+    out_data.id = htonl(USRP2_CTRL_ID_POKE_THIS_REGISTER_FOR_ME_BRO);
+    out_data.data.poke_args.addr = htonl(addr);
+    out_data.data.poke_args.data = htonl(data);
+
+    //send and recv
+    usrp2_ctrl_data_t in_data = this->ctrl_send_and_recv(out_data);
+    ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_OMG_POKED_REGISTER_SO_BAD_DUDE);
+}
+
+boost::uint32_t usrp2_impl::peek(boost::uint32_t addr){
+    //setup the out data
+    usrp2_ctrl_data_t out_data;
+    out_data.id = htonl(USRP2_CTRL_ID_PEEK_AT_THIS_REGISTER_FOR_ME_BRO);
+    out_data.data.poke_args.addr = htonl(addr);
+
+    //send and recv
+    usrp2_ctrl_data_t in_data = this->ctrl_send_and_recv(out_data);
+    ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_WOAH_I_DEFINITELY_PEEKED_IT_DUDE);
+    return ntohl(out_data.data.poke_args.data);
+}
+
 /***********************************************************************
  * Control Send/Recv
  **********************************************************************/
diff --git a/host/lib/usrp/usrp2/usrp2_impl.hpp b/host/lib/usrp/usrp2/usrp2_impl.hpp
index 3468a0cf1..55be420cd 100644
--- a/host/lib/usrp/usrp2/usrp2_impl.hpp
+++ b/host/lib/usrp/usrp2/usrp2_impl.hpp
@@ -102,6 +102,10 @@ public:
     //performs a control transaction
     usrp2_ctrl_data_t ctrl_send_and_recv(const usrp2_ctrl_data_t &);
 
+    //peek and poke registers
+    void poke(boost::uint32_t addr, boost::uint32_t data);
+    boost::uint32_t peek(boost::uint32_t addr);
+
     //misc access methods
     double get_master_clock_freq(void);
 
@@ -168,7 +172,8 @@ private:
     void tx_dboard_set(const wax::obj &, const wax::obj &);
     uhd::dict<std::string, wax_obj_proxy::sptr> _tx_dboards;
     uhd::prop_names_t _tx_subdevs_in_use;
-    void update_mux_config(void);
+    void update_rx_mux_config(void);
+    void update_tx_mux_config(void);
 
     //methods and shadows for the ddc dsp
     std::vector<size_t> _allowed_decim_and_interp_rates;
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp
new file mode 100644
index 000000000..10545d712
--- /dev/null
+++ b/host/lib/usrp/usrp2/usrp2_regs.hpp
@@ -0,0 +1,199 @@
+//
+// Copyright 2010 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#ifndef INCLUDED_USRP2_REGS_HPP
+#define INCLUDED_USRP2_REGS_HPP
+
+#include <boost/cstdint.hpp>
+
+////////////////////////////////////////////////////
+// Settings Bus, Slave #7, Not Byte Addressable!
+//
+// Output-only from processor point-of-view.
+// 1KB of address space (== 256 32-bit write-only regs)
+
+
+#define MISC_OUTPUT_BASE        0xD400
+//#define TX_PROTOCOL_ENGINE_BASE 0xD480
+//#define RX_PROTOCOL_ENGINE_BASE 0xD4C0
+//#define BUFFER_POOL_CTRL_BASE   0xD500
+//#define LAST_SETTING_REG        0xD7FC  // last valid setting register
+
+#define SR_MISC 0
+#define SR_TX_PROT_ENG 32
+#define SR_RX_PROT_ENG 48
+#define SR_BUFFER_POOL_CTRL 64
+#define SR_UDP_SM 96
+#define SR_TX_DSP 208
+#define SR_TX_CTRL 224
+#define SR_RX_DSP 160
+#define SR_RX_CTRL 176
+#define SR_TIME64 192
+#define SR_SIMTIMER 198
+#define SR_LAST 255
+
+#define _SR_ADDR(sr)    (MISC_OUTPUT_BASE + (sr) * sizeof(boost::uint32_t))
+
+/////////////////////////////////////////////////
+// SPI Slave Constants
+////////////////////////////////////////////////
+// Masks for controlling different peripherals
+#define SPI_SS_AD9510    1
+#define SPI_SS_AD9777    2
+#define SPI_SS_RX_DAC    4
+#define SPI_SS_RX_ADC    8
+#define SPI_SS_RX_DB    16
+#define SPI_SS_TX_DAC   32
+#define SPI_SS_TX_ADC   64
+#define SPI_SS_TX_DB   128
+
+/////////////////////////////////////////////////
+// VITA49 64 bit time (write only)
+////////////////////////////////////////////////
+  /*!
+   * \brief Time 64 flags
+   *
+   * <pre>
+   *
+   *    3                   2                   1                       
+   *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   * +-----------------------------------------------------------+-+-+
+   * |                                                           |S|P|
+   * +-----------------------------------------------------------+-+-+
+   *
+   * P - PPS edge selection (0=negedge, 1=posedge, default=0)
+   * S - Source (0=sma, 1=mimo, 0=default)
+   *
+   * </pre>
+   */
+#define FR_TIME64_SECS  _SR_ADDR(SR_TIME64 + 0)  // value to set absolute secs to on next PPS
+#define FR_TIME64_TICKS _SR_ADDR(SR_TIME64 + 1)  // value to set absolute ticks to on next PPS
+#define FR_TIME64_FLAGS _SR_ADDR(SR_TIME64 + 2)  // flags - see chart above
+#define FR_TIME64_IMM   _SR_ADDR(SR_TIME64 + 3) // set immediate (0=latch on next pps, 1=latch immediate, default=0)
+
+//pps flags (see above)
+#define FRF_TIME64_PPS_NEGEDGE (0 << 0)
+#define FRF_TIME64_PPS_POSEDGE (1 << 0)
+#define FRF_TIME64_PPS_SMA     (0 << 1)
+#define FRF_TIME64_PPS_MIMO    (1 << 1)
+
+#define FRF_TIME64_LATCH_NOW 1
+#define FRF_TIME64_LATCH_NEXT_PPS 0
+
+/////////////////////////////////////////////////
+// DSP TX Regs
+////////////////////////////////////////////////
+#define FR_DSP_TX_FREQ         _SR_ADDR(SR_TX_DSP + 0)
+#define FR_DSP_TX_SCALE_IQ     _SR_ADDR(SR_TX_DSP + 1) // {scale_i,scale_q}
+#define FR_DSP_TX_INTERP_RATE  _SR_ADDR(SR_TX_DSP + 2)
+
+  /*!
+   * \brief output mux configuration.
+   *
+   * <pre>
+   *     3                   2                   1                       
+   *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   *  +-------------------------------+-------+-------+-------+-------+
+   *  |                                               | DAC1  |  DAC0 |
+   *  +-------------------------------+-------+-------+-------+-------+
+   * 
+   *  There are N DUCs (1 now) with complex inputs and outputs.
+   *  There are two DACs.
+   * 
+   *  Each 4-bit DACx field specifies the source for the DAC
+   *  Each subfield is coded like this: 
+   * 
+   *     3 2 1 0
+   *    +-------+
+   *    |   N   |
+   *    +-------+
+   * 
+   *  N specifies which DUC output is connected to this DAC.
+   * 
+   *   N   which interp output
+   *  ---  -------------------
+   *   0   DUC 0 I
+   *   1   DUC 0 Q
+   *   2   DUC 1 I
+   *   3   DUC 1 Q
+   *   F   All Zeros
+   *   
+   * The default value is 0x10
+   * </pre>
+   */
+#define FR_DSP_TX_MUX  _SR_ADDR(SR_TX_DSP + 4)
+
+/////////////////////////////////////////////////
+// DSP RX Regs
+////////////////////////////////////////////////
+#define FR_DSP_RX_FREQ         _SR_ADDR(SR_RX_DSP + 0)
+#define FR_DSP_RX_SCALE_IQ     _SR_ADDR(SR_RX_DSP + 1) // {scale_i,scale_q}
+#define FR_DSP_RX_DECIM_RATE   _SR_ADDR(SR_RX_DSP + 2)
+#define FR_DSP_RX_DCOFFSET_I   _SR_ADDR(SR_RX_DSP + 3) // Bit 31 high sets fixed offset mode, using lower 14 bits,
+                                                       // otherwise it is automatic 
+#define FR_DSP_RX_DCOFFSET_Q   _SR_ADDR(SR_RX_DSP + 4) // Bit 31 high sets fixed offset mode, using lower 14 bits
+  /*!
+   * \brief input mux configuration.
+   *
+   * This determines which ADC (or constant zero) is connected to 
+   * each DDC input.  There are N DDCs (1 now).  Each has two inputs.
+   *
+   * <pre>
+   * Mux value:
+   *
+   *    3                   2                   1                       
+   *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   * +-------+-------+-------+-------+-------+-------+-------+-------+
+   * |                                                       |Q0 |I0 |
+   * +-------+-------+-------+-------+-------+-------+-------+-------+
+   *
+   * Each 2-bit I field is either 00 (A/D A), 01 (A/D B) or 1X (const zero)
+   * Each 2-bit Q field is either 00 (A/D A), 01 (A/D B) or 1X (const zero)
+   *
+   * The default value is 0x4
+   * </pre>
+   */
+#define FR_DSP_RX_MUX  _SR_ADDR(SR_RX_DSP + 5)         // called adc_mux in dsp_core_rx.v
+
+////////////////////////////////////////////////
+// GPIO, Slave 4
+////////////////////////////////////////////////
+//
+// These go to the daughterboard i/o pins
+//
+#define _FR_GPIO_ADDR(off) (0xC800 + (off) * sizeof(boost::uint32_t))
+#define FR_GPIO_IO     _FR_GPIO_ADDR(0)       // tx data in high 16, rx in low 16
+#define FR_GPIO_DDR    _FR_GPIO_ADDR(1)       // 32 bits, 1 means output. tx in high 16, rx in low 16
+#define FR_GPIO_TX_SEL _FR_GPIO_ADDR(2)       // 16 2-bit fields select which source goes to TX DB
+#define FR_GPIO_RX_SEL _FR_GPIO_ADDR(3)       // 16 2-bit fields select which source goes to RX DB
+
+// each 2-bit sel field is layed out this way
+#define FRF_GPIO_SEL_SW        0 // if pin is an output, set by software in the io reg
+#define FRF_GPIO_SEL_ATR       1 // if pin is an output, set by ATR logic
+#define FRF_GPIO_SEL_DEBUG_0   2 // if pin is an output, debug lines from FPGA fabric
+#define FRF_GPIO_SEL_DEBUG_1   3 // if pin is an output, debug lines from FPGA fabric
+
+///////////////////////////////////////////////////
+// ATR Controller, Slave 11
+////////////////////////////////////////////////
+#define _FR_ATR_ADDR(off) (0xE400 + (off) * sizeof(boost::uint32_t))
+#define FR_ATR_IDLE    _FR_ATR_ADDR(0) // tx data in high 16, rx in low 16
+#define FR_ATR_TX      _FR_ATR_ADDR(1)
+#define FR_ATR_RX      _FR_ATR_ADDR(2)
+#define FR_ATR_FULL    _FR_ATR_ADDR(3)
+
+#endif /* INCLUDED_USRP2_REGS_HPP */