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authorJosh Blum <josh@joshknows.com>2011-07-28 14:33:25 -0700
committerJosh Blum <josh@joshknows.com>2011-07-28 14:33:25 -0700
commitabc095773db0eab91804212f0615c0f4a6bc3689 (patch)
tree28751237358749c47e061de43bbac6f84733fe02 /host/lib/usrp/usrp2
parent8b4a7bc8aecfe804de779f3e27fff41082f0446a (diff)
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usrp2: adjusted mimo delay cycles for FPGA changes
Diffstat (limited to 'host/lib/usrp/usrp2')
-rw-r--r--host/lib/usrp/usrp2/usrp2_impl.hpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/host/lib/usrp/usrp2/usrp2_impl.hpp b/host/lib/usrp/usrp2/usrp2_impl.hpp
index cdbcc895f..c0f4b1e6e 100644
--- a/host/lib/usrp/usrp2/usrp2_impl.hpp
+++ b/host/lib/usrp/usrp2/usrp2_impl.hpp
@@ -46,7 +46,7 @@
static const double USRP2_LINK_RATE_BPS = 1000e6/8;
static const double mimo_clock_delay_usrp2_rev4 = 4.18e-9;
static const double mimo_clock_delay_usrp_n2xx = 3.55e-9;
-static const size_t mimo_clock_sync_delay_cycles = 137;
+static const size_t mimo_clock_sync_delay_cycles = 138;
static const size_t USRP2_SRAM_BYTES = size_t(1 << 20);
static const boost::uint32_t USRP2_TX_ASYNC_SID = 2;
static const boost::uint32_t USRP2_RX_SID_BASE = 3;