From abc095773db0eab91804212f0615c0f4a6bc3689 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 28 Jul 2011 14:33:25 -0700 Subject: usrp2: adjusted mimo delay cycles for FPGA changes --- host/lib/usrp/usrp2/usrp2_impl.hpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'host/lib/usrp/usrp2') diff --git a/host/lib/usrp/usrp2/usrp2_impl.hpp b/host/lib/usrp/usrp2/usrp2_impl.hpp index cdbcc895f..c0f4b1e6e 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.hpp +++ b/host/lib/usrp/usrp2/usrp2_impl.hpp @@ -46,7 +46,7 @@ static const double USRP2_LINK_RATE_BPS = 1000e6/8; static const double mimo_clock_delay_usrp2_rev4 = 4.18e-9; static const double mimo_clock_delay_usrp_n2xx = 3.55e-9; -static const size_t mimo_clock_sync_delay_cycles = 137; +static const size_t mimo_clock_sync_delay_cycles = 138; static const size_t USRP2_SRAM_BYTES = size_t(1 << 20); static const boost::uint32_t USRP2_TX_ASYNC_SID = 2; static const boost::uint32_t USRP2_RX_SID_BASE = 3; -- cgit v1.2.3