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authorJosh Blum <josh@joshknows.com>2010-07-04 19:13:59 -0700
committerJosh Blum <josh@joshknows.com>2010-07-05 13:49:03 -0700
commit5e14653f241070791d46893e68e341357e040add (patch)
tree1b4e8da3e0fa3f2a53dd309d9f9ffddfd5c6f953 /host/lib/usrp/usrp2/usrp2_regs.hpp
parent11f2aa1ea0fd6c28a20c6d85f94e41a06b3a6770 (diff)
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usrp2: bug fix for readback registers
added readback for time64 fixed bug for fragment flag in vrt packet handler
Diffstat (limited to 'host/lib/usrp/usrp2/usrp2_regs.hpp')
-rw-r--r--host/lib/usrp/usrp2/usrp2_regs.hpp10
1 files changed, 6 insertions, 4 deletions
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp
index 589fa71a3..c859d3603 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.hpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.hpp
@@ -18,8 +18,6 @@
#ifndef INCLUDED_USRP2_REGS_HPP
#define INCLUDED_USRP2_REGS_HPP
-#include <boost/cstdint.hpp>
-
////////////////////////////////////////////////////
// Settings Bus, Slave #7, Not Byte Addressable!
//
@@ -46,7 +44,7 @@
#define SR_SIMTIMER 198
#define SR_LAST 255
-#define _SR_ADDR(sr) (MISC_OUTPUT_BASE + (sr) * sizeof(boost::uint32_t))
+#define _SR_ADDR(sr) ((MISC_OUTPUT_BASE) + (4*(sr)))
/////////////////////////////////////////////////
// SPI Slave Constants
@@ -104,7 +102,11 @@
#define U2_REG_TIME64_SECS _SR_ADDR(SR_TIME64 + 0) // value to set absolute secs to on next PPS
#define U2_REG_TIME64_TICKS _SR_ADDR(SR_TIME64 + 1) // value to set absolute ticks to on next PPS
#define U2_REG_TIME64_FLAGS _SR_ADDR(SR_TIME64 + 2) // flags - see chart above
-#define U2_REG_TIME64_IMM _SR_ADDR(SR_TIME64 + 3) // set immediate (0=latch on next pps, 1=latch immediate, default=0)
+#define U2_REG_TIME64_IMM _SR_ADDR(SR_TIME64 + 3) // set immediate (0=latch on next pps, 1=latch immediate, default=0)
+#define U2_REG_TIME64_TPS _SR_ADDR(SR_TIME64 + 4) // the ticks per second rollover count
+
+#define U2_REG_TIME64_SECS_RB (0xCC00 + 4*10)
+#define U2_REG_TIME64_TICKS_RB (0xCC00 + 4*11)
//pps flags (see above)
#define U2_FLAG_TIME64_PPS_NEGEDGE (0 << 0)