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authorJosh Blum <josh@joshknows.com>2010-07-26 15:31:03 -0700
committerJosh Blum <josh@joshknows.com>2010-07-26 15:31:03 -0700
commit693929a9e6e9234610e756e6d25da58d2171a565 (patch)
treee796a386d11ec0d081900a99628ac2ee58f473b7 /host/lib/usrp/usrp2/usrp2_regs.hpp
parentf86c25317b457b280c697fc47905c79bdbbc0c93 (diff)
parent19c15883a9054727c13f4eb5471cc961fe54c40d (diff)
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Merge branch 'tx_report'
Conflicts: host/lib/usrp/usrp2/io_impl.cpp
Diffstat (limited to 'host/lib/usrp/usrp2/usrp2_regs.hpp')
-rw-r--r--host/lib/usrp/usrp2/usrp2_regs.hpp9
1 files changed, 8 insertions, 1 deletions
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp
index 1a5864c85..aa8bd860f 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.hpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.hpp
@@ -226,7 +226,7 @@
#define U2_REG_ATR_FULL_RXSIDE U2_REG_ATR_BASE + 14
///////////////////////////////////////////////////
-// VITA RX CTRL regs
+// RX CTRL regs
///////////////////////////////////////////////////
// The following 3 are logically a single command register.
// They are clocked into the underlying fifo when time_ticks is written.
@@ -241,4 +241,11 @@
#define U2_REG_RX_CTRL_NSAMPS_PER_PKT _SR_ADDR(SR_RX_CTRL + 7)
#define U2_REG_RX_CTRL_NCHANNELS _SR_ADDR(SR_RX_CTRL + 8) // 1 in basic case, up to 4 for vector sources
+///////////////////////////////////////////////////
+// TX CTRL regs
+///////////////////////////////////////////////////
+#define U2_REG_TX_CTRL_NUM_CHAN _SR_ADDR(SR_TX_CTRL + 0)
+#define U2_REG_TX_CTRL_CLEAR_STATE _SR_ADDR(SR_TX_CTRL + 1)
+#define U2_REG_TX_CTRL_REPORT_SID _SR_ADDR(SR_TX_CTRL + 2)
+
#endif /* INCLUDED_USRP2_REGS_HPP */