From 20381a1c839ded4eb58728d3a1fd3a952d2444f6 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 19 Jul 2010 18:56:33 -0700 Subject: usrp2: added registers and handling for tx async reports --- host/lib/usrp/usrp2/usrp2_regs.hpp | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'host/lib/usrp/usrp2/usrp2_regs.hpp') diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index 1a5864c85..aa8bd860f 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -226,7 +226,7 @@ #define U2_REG_ATR_FULL_RXSIDE U2_REG_ATR_BASE + 14 /////////////////////////////////////////////////// -// VITA RX CTRL regs +// RX CTRL regs /////////////////////////////////////////////////// // The following 3 are logically a single command register. // They are clocked into the underlying fifo when time_ticks is written. @@ -241,4 +241,11 @@ #define U2_REG_RX_CTRL_NSAMPS_PER_PKT _SR_ADDR(SR_RX_CTRL + 7) #define U2_REG_RX_CTRL_NCHANNELS _SR_ADDR(SR_RX_CTRL + 8) // 1 in basic case, up to 4 for vector sources +/////////////////////////////////////////////////// +// TX CTRL regs +/////////////////////////////////////////////////// +#define U2_REG_TX_CTRL_NUM_CHAN _SR_ADDR(SR_TX_CTRL + 0) +#define U2_REG_TX_CTRL_CLEAR_STATE _SR_ADDR(SR_TX_CTRL + 1) +#define U2_REG_TX_CTRL_REPORT_SID _SR_ADDR(SR_TX_CTRL + 2) + #endif /* INCLUDED_USRP2_REGS_HPP */ -- cgit v1.2.3