usrp2: added indexed regs for rx dsp and ctrl

1 files changed, 12 insertions, 27 deletions

diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp
index 5f3537f1e..a3de8673e 100644
--- a/host/lib/usrp/usrp2/mboard_impl.cpp
+++ b/host/lib/usrp/usrp2/mboard_impl.cpp
@@ -22,7 +22,6 @@
 #include <uhd/usrp/dsp_utils.hpp>
 #include <uhd/usrp/mboard_props.hpp>
 #include <uhd/utils/assert.hpp>
-#include <uhd/utils/byteswap.hpp>
 #include <uhd/utils/algorithm.hpp>
 #include <boost/bind.hpp>
 #include <iostream>
@@ -48,21 +47,6 @@ usrp2_mboard_impl::usrp2_mboard_impl(
     _index(index),
     _iface(usrp2_iface::make(ctrl_transport))
 {
-    //Send a small data packet so the usrp2 knows the udp source port.
-    //This setup must happen before further initialization occurs
-    //or the async update packets will cause ICMP destination unreachable.
-    transport::managed_send_buffer::sptr send_buff;
-    static const boost::uint32_t data[2] = {
-        uhd::htonx(boost::uint32_t(0 /* don't care seq num */)),
-        uhd::htonx(boost::uint32_t(USRP2_INVALID_VRT_HEADER))
-    };
-    send_buff = data_transport->get_send_buff();
-    std::memcpy(send_buff->cast<void*>(), &data, sizeof(data));
-    send_buff->commit(sizeof(data));
-    send_buff = err0_transport->get_send_buff();
-    std::memcpy(send_buff->cast<void*>(), &data, sizeof(data));
-    send_buff->commit(sizeof(data));
-
     //contruct the interfaces to mboard perifs
     _clock_ctrl = usrp2_clock_ctrl::make(_iface);
     _codec_ctrl = usrp2_codec_ctrl::make(_iface);
@@ -87,17 +71,18 @@ usrp2_mboard_impl::usrp2_mboard_impl(
     }
 
     //setup the vrt rx registers
-    _iface->poke32(_iface->regs.rx_ctrl0_clear_overrun, 1); //reset
-    _iface->poke32(_iface->regs.rx_ctrl0_nsamps_per_pkt, recv_samps_per_packet);
-    _iface->poke32(_iface->regs.rx_ctrl0_nchannels, 1);
-    _iface->poke32(_iface->regs.rx_ctrl0_vrt_header, 0
+    //TODO loop for 0, 1, in NUM_RX_DSPS
+    _iface->poke32(_iface->regs.rx_ctrl[0].clear_overrun, 1); //reset
+    _iface->poke32(_iface->regs.rx_ctrl[0].nsamps_per_pkt, recv_samps_per_packet);
+    _iface->poke32(_iface->regs.rx_ctrl[0].nchannels, 1);
+    _iface->poke32(_iface->regs.rx_ctrl[0].vrt_header, 0
         | (0x1 << 28) //if data with stream id
         | (0x1 << 26) //has trailer
         | (0x3 << 22) //integer time other
         | (0x1 << 20) //fractional time sample count
     );
-    _iface->poke32(_iface->regs.rx_ctrl0_vrt_stream_id, usrp2_impl::RECV_SID);
-    _iface->poke32(_iface->regs.rx_ctrl0_vrt_trailer, 0);
+    _iface->poke32(_iface->regs.rx_ctrl[0].vrt_stream_id, usrp2_impl::RECV_SID);
+    _iface->poke32(_iface->regs.rx_ctrl[0].vrt_trailer, 0);
     _iface->poke32(_iface->regs.time64_tps, size_t(get_master_clock_freq()));
 
     //init the tx control registers
@@ -164,7 +149,7 @@ usrp2_mboard_impl::usrp2_mboard_impl(
     this->issue_ddc_stream_cmd(stream_cmd);
     data_transport->get_recv_buff().get(); //recv with timeout for lingering
     data_transport->get_recv_buff().get(); //recv with timeout for expected
-    _iface->poke32(_iface->regs.rx_ctrl0_clear_overrun, 1); //resets sequence
+    _iface->poke32(_iface->regs.rx_ctrl[0].clear_overrun, 1); //resets sequence
 }
 
 usrp2_mboard_impl::~usrp2_mboard_impl(void){
@@ -273,9 +258,9 @@ void usrp2_mboard_impl::handle_overflow(void){
 
 void usrp2_mboard_impl::issue_ddc_stream_cmd(const stream_cmd_t &stream_cmd){
     _continuous_streaming = stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_START_CONTINUOUS;
-    _iface->poke32(_iface->regs.rx_ctrl0_stream_cmd, dsp_type1::calc_stream_cmd_word(stream_cmd));
-    _iface->poke32(_iface->regs.rx_ctrl0_time_secs,  boost::uint32_t(stream_cmd.time_spec.get_full_secs()));
-    _iface->poke32(_iface->regs.rx_ctrl0_time_ticks, stream_cmd.time_spec.get_tick_count(get_master_clock_freq()));
+    _iface->poke32(_iface->regs.rx_ctrl[0].stream_cmd, dsp_type1::calc_stream_cmd_word(stream_cmd));
+    _iface->poke32(_iface->regs.rx_ctrl[0].time_secs,  boost::uint32_t(stream_cmd.time_spec.get_full_secs()));
+    _iface->poke32(_iface->regs.rx_ctrl[0].time_ticks, stream_cmd.time_spec.get_tick_count(get_master_clock_freq()));
 }
 
 /***********************************************************************
@@ -397,7 +382,7 @@ void usrp2_mboard_impl::set(const wax::obj &key, const wax::obj &val){
         //sanity check
         UHD_ASSERT_THROW(_rx_subdev_spec.size() <= 2);
         //set the mux
-        if (_rx_subdev_spec.size() >= 1) _iface->poke32(_iface->regs.dsp0_rx_mux, dsp_type1::calc_rx_mux_word(
+        if (_rx_subdev_spec.size() >= 1) _iface->poke32(_iface->regs.dsp_rx[0].mux, dsp_type1::calc_rx_mux_word(
             _dboard_manager->get_rx_subdev(_rx_subdev_spec[0].sd_name)[SUBDEV_PROP_CONNECTION].as<subdev_conn_t>()
         ));
         //TODO