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author | Josh Blum <josh@joshknows.com> | 2010-07-19 18:56:33 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2010-07-19 18:56:33 -0700 |
commit | 20381a1c839ded4eb58728d3a1fd3a952d2444f6 (patch) | |
tree | 50d1de0b3a05a90ce94fb19e0981478072ca7ebe /host/lib/usrp/usrp2/mboard_impl.cpp | |
parent | ef9a395414acc203cc02e551e1790277cd0ef1f9 (diff) | |
download | uhd-20381a1c839ded4eb58728d3a1fd3a952d2444f6.tar.gz uhd-20381a1c839ded4eb58728d3a1fd3a952d2444f6.tar.bz2 uhd-20381a1c839ded4eb58728d3a1fd3a952d2444f6.zip |
usrp2: added registers and handling for tx async reports
Diffstat (limited to 'host/lib/usrp/usrp2/mboard_impl.cpp')
-rw-r--r-- | host/lib/usrp/usrp2/mboard_impl.cpp | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp index 7518d3114..b3b03c11c 100644 --- a/host/lib/usrp/usrp2/mboard_impl.cpp +++ b/host/lib/usrp/usrp2/mboard_impl.cpp @@ -67,7 +67,7 @@ usrp2_mboard_impl::usrp2_mboard_impl( _allowed_decim_and_interp_rates.push_back(i); } - //setup the vrt rx registers + //init the rx control registers _iface->poke32(U2_REG_RX_CTRL_NSAMPS_PER_PKT, _io_helper.get_max_recv_samps_per_packet()); _iface->poke32(U2_REG_RX_CTRL_NCHANNELS, 1); _iface->poke32(U2_REG_RX_CTRL_CLEAR_OVERRUN, 1); //reset @@ -81,6 +81,11 @@ usrp2_mboard_impl::usrp2_mboard_impl( _iface->poke32(U2_REG_RX_CTRL_VRT_TRAILER, 0); _iface->poke32(U2_REG_TIME64_TPS, size_t(get_master_clock_freq())); + //init the tx control registers + _iface->poke32(U2_REG_TX_CTRL_NUM_CHAN, 0); //1 channel + _iface->poke32(U2_REG_TX_CTRL_CLEAR_STATE, 1); //reset + _iface->poke32(U2_REG_TX_CTRL_REPORT_SID, 1); //sid 1 (different from rx) + //init the ddc init_ddc_config(); |