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authorMartin Braun <martin.braun@ettus.com>2018-03-26 14:48:12 -0700
committerMartin Braun <martin.braun@ettus.com>2018-03-28 14:21:35 -0700
commit18cda8029ff7ab1255579d81b0b27de68dacc88e (patch)
tree7edbad8e0b648a6557daa720d6847cb3f65b5650 /host/lib/usrp/usrp2/codec_ctrl.cpp
parent92a6c10979a2dea341349a44acbed43dc892dffc (diff)
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usrp2: Re-add ability to modulate in the DAC
This partially reverts b29e80cc. That commit fixed a bug with numerical overflows, but also removed the ability to tune using the DAC, effectively reducing the DSP tuning range. This commit allows to tune within +/- 200 MHz using a combination of both the DAC and the DSP tuning in the FPGA. Reviewed-by: Derek Kozek <derek.kozel@ettus.com>
Diffstat (limited to 'host/lib/usrp/usrp2/codec_ctrl.cpp')
-rw-r--r--host/lib/usrp/usrp2/codec_ctrl.cpp5
1 files changed, 5 insertions, 0 deletions
diff --git a/host/lib/usrp/usrp2/codec_ctrl.cpp b/host/lib/usrp/usrp2/codec_ctrl.cpp
index c3e7b332f..5c1c006fb 100644
--- a/host/lib/usrp/usrp2/codec_ctrl.cpp
+++ b/host/lib/usrp/usrp2/codec_ctrl.cpp
@@ -179,6 +179,11 @@ public:
}
}
+ size_t get_tx_interpolation() const
+ {
+ return 4;
+ }
+
private:
ad9777_regs_t _ad9777_regs;
ads62p44_regs_t _ads62p44_regs;