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authorJosh Blum <josh@joshknows.com>2011-05-14 20:25:52 -0700
committerJosh Blum <josh@joshknows.com>2011-05-14 20:25:52 -0700
commit4b772ff4f3b1e388e150402beaf6567f3ea29e1c (patch)
tree968376325d3f9ffae91231e5ef20de96450e2b3f /host/lib/usrp/usrp1/mboard_impl.cpp
parentf991d3dc751e110425d4a0eed722f6de0fef4261 (diff)
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usrp1: correct TX codec rate, it should also read 64e6 when probed
We were using clock_rate*2 to simulate a codec rate of 128MHz. This reflected the old gnuradio API, but the rate between FPGA and codec is really 64MHz for both rx and tx directions.
Diffstat (limited to 'host/lib/usrp/usrp1/mboard_impl.cpp')
-rw-r--r--host/lib/usrp/usrp1/mboard_impl.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/host/lib/usrp/usrp1/mboard_impl.cpp b/host/lib/usrp/usrp1/mboard_impl.cpp
index d6f6832a4..e9108e4f1 100644
--- a/host/lib/usrp/usrp1/mboard_impl.cpp
+++ b/host/lib/usrp/usrp1/mboard_impl.cpp
@@ -214,8 +214,8 @@ void usrp1_impl::mboard_init(void)
// Normal mode with no loopback or Rx counting
_iface->poke32(FR_MODE, 0x00000000);
_iface->poke32(FR_DEBUG_EN, 0x00000000);
- _iface->poke32(FR_RX_SAMPLE_RATE_DIV, 0x00000001);
- _iface->poke32(FR_TX_SAMPLE_RATE_DIV, 0x00000003);
+ _iface->poke32(FR_RX_SAMPLE_RATE_DIV, 0x00000001); //divide by 2
+ _iface->poke32(FR_TX_SAMPLE_RATE_DIV, 0x00000001); //divide by 2
_iface->poke32(FR_DC_OFFSET_CL_EN, 0x0000000f);
// Reset offset correction registers