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| author | Martin Braun <martin.braun@ettus.com> | 2017-04-05 23:18:08 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2017-04-05 23:18:08 -0700 |
| commit | af75b87e51a7c555a61f5f40f0d19f2fde04e43b (patch) | |
| tree | 0f33663855098a165970e3249a9098b3be812371 /host/lib/usrp/e100 | |
| parent | 4ab72eb9991d503d8cd329b31572d966ef0e1ae8 (diff) | |
| download | uhd-af75b87e51a7c555a61f5f40f0d19f2fde04e43b.tar.gz uhd-af75b87e51a7c555a61f5f40f0d19f2fde04e43b.tar.bz2 uhd-af75b87e51a7c555a61f5f40f0d19f2fde04e43b.zip | |
logging: Demoted a number of DEBUG messages to TRACE
Diffstat (limited to 'host/lib/usrp/e100')
| -rw-r--r-- | host/lib/usrp/e100/clock_ctrl.cpp | 2 | ||||
| -rw-r--r-- | host/lib/usrp/e100/codec_ctrl.cpp | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/host/lib/usrp/e100/clock_ctrl.cpp b/host/lib/usrp/e100/clock_ctrl.cpp index 567a4b8fb..a3f630462 100644 --- a/host/lib/usrp/e100/clock_ctrl.cpp +++ b/host/lib/usrp/e100/clock_ctrl.cpp @@ -459,7 +459,7 @@ private: void send_reg(uint16_t addr){ uint32_t reg = _ad9522_regs.get_write_reg(addr); - UHD_LOGGER_DEBUG("E100") << "clock control write reg: " << std::hex << reg ; + UHD_LOGGER_TRACE("E100") << "clock control write reg: " << std::hex << reg ; _iface->write_spi( UE_SPI_SS_AD9522, spi_config_t::EDGE_RISE, diff --git a/host/lib/usrp/e100/codec_ctrl.cpp b/host/lib/usrp/e100/codec_ctrl.cpp index ee26c1990..5bd394fb1 100644 --- a/host/lib/usrp/e100/codec_ctrl.cpp +++ b/host/lib/usrp/e100/codec_ctrl.cpp @@ -260,7 +260,7 @@ void e100_codec_ctrl_impl::write_aux_dac(aux_dac_t which, double volts){ **********************************************************************/ void e100_codec_ctrl_impl::send_reg(uint8_t addr){ uint32_t reg = _ad9862_regs.get_write_reg(addr); - UHD_LOGGER_DEBUG("E100") << "codec control write reg: " << std::hex << reg ; + UHD_LOGGER_TRACE("E100") << "codec control write reg: " << std::hex << reg ; _iface->write_spi( UE_SPI_SS_AD9862, spi_config_t::EDGE_RISE, @@ -270,13 +270,13 @@ void e100_codec_ctrl_impl::send_reg(uint8_t addr){ void e100_codec_ctrl_impl::recv_reg(uint8_t addr){ uint32_t reg = _ad9862_regs.get_read_reg(addr); - UHD_LOGGER_DEBUG("E100") << "codec control read reg: " << std::hex << reg ; + UHD_LOGGER_TRACE("E100") << "codec control read reg: " << std::hex << reg ; uint32_t ret = _iface->read_spi( UE_SPI_SS_AD9862, spi_config_t::EDGE_RISE, reg, 16 ); - UHD_LOGGER_DEBUG("E100") << "codec control read ret: " << std::hex << ret ; + UHD_LOGGER_TRACE("E100") << "codec control read ret: " << std::hex << ret ; _ad9862_regs.set_reg(addr, uint16_t(ret)); } |