uhd: Apply clang-format against all .cpp and .hpp files in host/

Note: template_lvbitx.{cpp,hpp} need to be excluded from the list of
files that clang-format gets applied against.

8 files changed, 1314 insertions, 963 deletions

diff --git a/host/lib/usrp/dboard/twinrx/twinrx_ctrl.cpp b/host/lib/usrp/dboard/twinrx/twinrx_ctrl.cpp
index 85ed3ddb7..3752a2e70 100644
--- a/host/lib/usrp/dboard/twinrx/twinrx_ctrl.cpp
+++ b/host/lib/usrp/dboard/twinrx/twinrx_ctrl.cpp
@@ -7,11 +7,11 @@
 
 #include "twinrx_ctrl.hpp"
 #include "twinrx_ids.hpp"
+#include <uhd/utils/math.hpp>
+#include <uhd/utils/safe_call.hpp>
 #include <uhdlib/usrp/common/adf435x.hpp>
 #include <uhdlib/usrp/common/adf535x.hpp>
 #include <uhdlib/utils/narrow.hpp>
-#include <uhd/utils/math.hpp>
-#include <uhd/utils/safe_call.hpp>
 #include <chrono>
 #include <thread>
 
@@ -20,39 +20,44 @@ using namespace usrp;
 using namespace dboard::twinrx;
 
 namespace {
-  typedef twinrx_cpld_regmap rm;
-
-  typedef enum { LO1, LO2 } lo_t;
+typedef twinrx_cpld_regmap rm;
 
-  inline uint32_t bool2bin(bool x) { return x ? 1 : 0; }
+typedef enum { LO1, LO2 } lo_t;
 
-  const double TWINRX_DESIRED_REFERENCE_FREQ = 50e6;
-  const double TWINRX_REV_AB_PFD_FREQ = 6.25e6;
-  const double TWINRX_REV_C_PFD_FREQ = 12.5e6;
-  const double TWINRX_SPI_CLOCK_FREQ = 3e6;
+inline uint32_t bool2bin(bool x)
+{
+    return x ? 1 : 0;
 }
 
-class twinrx_ctrl_impl : public twinrx_ctrl {
+const double TWINRX_DESIRED_REFERENCE_FREQ = 50e6;
+const double TWINRX_REV_AB_PFD_FREQ        = 6.25e6;
+const double TWINRX_REV_C_PFD_FREQ         = 12.5e6;
+const double TWINRX_SPI_CLOCK_FREQ         = 3e6;
+} // namespace
+
+class twinrx_ctrl_impl : public twinrx_ctrl
+{
 public:
-    twinrx_ctrl_impl(
-        dboard_iface::sptr db_iface,
+    twinrx_ctrl_impl(dboard_iface::sptr db_iface,
         twinrx_gpio::sptr gpio_iface,
         twinrx_cpld_regmap::sptr cpld_regmap,
-        const dboard_id_t rx_id
-    ) : _db_iface(db_iface), _gpio_iface(gpio_iface), _cpld_regs(cpld_regmap)
+        const dboard_id_t rx_id)
+        : _db_iface(db_iface), _gpio_iface(gpio_iface), _cpld_regs(cpld_regmap)
     {
         // SPI configuration
         _spi_config.use_custom_divider = true;
         _spi_config.divider            = uhd::narrow_cast<size_t>(std::ceil(
             _db_iface->get_codec_rate(dboard_iface::UNIT_TX) / TWINRX_SPI_CLOCK_FREQ));
 
-        //Initialize dboard clocks
+        // Initialize dboard clocks
         bool found_rate = false;
-        for(double rate:  _db_iface->get_clock_rates(dboard_iface::UNIT_TX)) {
-            found_rate |= uhd::math::frequencies_are_equal(rate, TWINRX_DESIRED_REFERENCE_FREQ);
+        for (double rate : _db_iface->get_clock_rates(dboard_iface::UNIT_TX)) {
+            found_rate |=
+                uhd::math::frequencies_are_equal(rate, TWINRX_DESIRED_REFERENCE_FREQ);
         }
-        for(double rate:  _db_iface->get_clock_rates(dboard_iface::UNIT_RX)) {
-            found_rate |= uhd::math::frequencies_are_equal(rate, TWINRX_DESIRED_REFERENCE_FREQ);
+        for (double rate : _db_iface->get_clock_rates(dboard_iface::UNIT_RX)) {
+            found_rate |=
+                uhd::math::frequencies_are_equal(rate, TWINRX_DESIRED_REFERENCE_FREQ);
         }
         if (not found_rate) {
             throw uhd::runtime_error("TwinRX not supported on this motherboard");
@@ -63,7 +68,7 @@ public:
         _db_iface->set_clock_enabled(dboard_iface::UNIT_TX, true);
         _db_iface->set_clock_enabled(dboard_iface::UNIT_RX, true);
 
-        //Initialize default switch and attenuator states
+        // Initialize default switch and attenuator states
         set_chan_enabled(BOTH, false, false);
         set_preamp1(BOTH, PREAMP_BYPASS, false);
         set_preamp2(BOTH, false, false);
@@ -82,7 +87,7 @@ public:
         set_crossover_cal_mode(CAL_DISABLED, false);
         _cpld_regs->flush();
 
-        //Turn on power and wait for power good
+        // Turn on power and wait for power good
         _gpio_iface->set_field(twinrx_gpio::FIELD_SWPS_EN, 1);
         size_t timeout_ms = 100;
         while (_gpio_iface->get_field(twinrx_gpio::FIELD_SWPS_PWR_GOOD) == 0) {
@@ -98,7 +103,7 @@ public:
         _gpio_iface->set_field(twinrx_gpio::FIELD_LO2_CE_CH1, 1);
         _gpio_iface->set_field(twinrx_gpio::FIELD_LO2_CE_CH2, 1);
 
-        //Initialize synthesizers
+        // Initialize synthesizers
         for (size_t i = 0; i < NUM_CHANS; i++) {
             // LO1
             if (rx_id == twinrx::TWINRX_REV_C_ID) {
@@ -108,8 +113,7 @@ public:
                     },
                     [this](uint32_t microseconds) {
                         _db_iface->sleep(boost::chrono::microseconds(microseconds));
-                    }
-                );
+                    });
                 _lo1_iface[i]->set_pfd_freq(TWINRX_REV_C_PFD_FREQ);
             } else {
                 _lo1_iface[i] = adf535x_iface::make_adf5355(
@@ -118,8 +122,7 @@ public:
                     },
                     [this](uint32_t microseconds) {
                         _db_iface->sleep(boost::chrono::microseconds(microseconds));
-                    }
-                );
+                    });
                 _lo1_iface[i]->set_pfd_freq(TWINRX_REV_AB_PFD_FREQ);
             }
             _lo1_iface[i]->set_output_power(adf535x_iface::OUTPUT_POWER_5DBM);
@@ -128,11 +131,10 @@ public:
             _lo1_iface[i]->set_frequency(3e9, 1.0e3);
 
             // LO2
-            _lo2_iface[i] = adf435x_iface::make_adf4351(
-                [this](const std::vector<uint32_t>& regs) {
+            _lo2_iface[i] =
+                adf435x_iface::make_adf4351([this](const std::vector<uint32_t>& regs) {
                     _write_lo_spi(dboard_iface::UNIT_RX, regs);
-                }
-            );
+                });
             _lo2_iface[i]->set_feedback_select(adf435x_iface::FB_SEL_DIVIDED);
             _lo2_iface[i]->set_output_power(adf435x_iface::OUTPUT_POWER_5DBM);
             _lo2_iface[i]->set_reference_freq(TWINRX_DESIRED_REFERENCE_FREQ);
@@ -145,10 +147,8 @@ public:
 
     ~twinrx_ctrl_impl()
     {
-        UHD_SAFE_CALL(
-            boost::lock_guard<boost::mutex> lock(_mutex);
-            _gpio_iface->set_field(twinrx_gpio::FIELD_SWPS_EN, 0);
-        )
+        UHD_SAFE_CALL(boost::lock_guard<boost::mutex> lock(_mutex);
+                      _gpio_iface->set_field(twinrx_gpio::FIELD_SWPS_EN, 0);)
     }
 
     void commit()
@@ -171,80 +171,117 @@ public:
             _cpld_regs->if0_reg0.set(rm::if0_reg0_t::AMP_LO2_EN_CH2, bool2bin(enabled));
             _chan_enabled[size_t(CH2)] = enabled;
         }
-        _set_lo1_amp(_chan_enabled[size_t(CH1)], _chan_enabled[size_t(CH2)], _lo1_src[size_t(CH2)]);
-        if (commit) _commit();
+        _set_lo1_amp(_chan_enabled[size_t(CH1)],
+            _chan_enabled[size_t(CH2)],
+            _lo1_src[size_t(CH2)]);
+        if (commit)
+            _commit();
     }
 
     void set_preamp1(channel_t ch, preamp_state_t value, bool commit = true)
     {
         boost::lock_guard<boost::mutex> lock(_mutex);
         if (ch == CH1 or ch == BOTH) {
-            _cpld_regs->rf0_reg1.set(rm::rf0_reg1_t::SWPA1_CTL_CH1, bool2bin(value==PREAMP_HIGHBAND));
-            _cpld_regs->rf2_reg2.set(rm::rf2_reg2_t::SWPA2_CTRL_CH1, bool2bin(value==PREAMP_BYPASS));
-            _cpld_regs->rf0_reg1.set(rm::rf0_reg1_t::HB_PREAMP_EN_CH1, bool2bin(value==PREAMP_HIGHBAND));
-            _cpld_regs->rf0_reg1.set(rm::rf0_reg1_t::LB_PREAMP_EN_CH1, bool2bin(value==PREAMP_LOWBAND));
+            _cpld_regs->rf0_reg1.set(
+                rm::rf0_reg1_t::SWPA1_CTL_CH1, bool2bin(value == PREAMP_HIGHBAND));
+            _cpld_regs->rf2_reg2.set(
+                rm::rf2_reg2_t::SWPA2_CTRL_CH1, bool2bin(value == PREAMP_BYPASS));
+            _cpld_regs->rf0_reg1.set(
+                rm::rf0_reg1_t::HB_PREAMP_EN_CH1, bool2bin(value == PREAMP_HIGHBAND));
+            _cpld_regs->rf0_reg1.set(
+                rm::rf0_reg1_t::LB_PREAMP_EN_CH1, bool2bin(value == PREAMP_LOWBAND));
         }
         if (ch == CH2 or ch == BOTH) {
-            _cpld_regs->rf0_reg7.set(rm::rf0_reg7_t::SWPA1_CTRL_CH2, bool2bin(value==PREAMP_HIGHBAND));
-            _cpld_regs->rf2_reg5.set(rm::rf2_reg5_t::SWPA2_CTRL_CH2, bool2bin(value==PREAMP_BYPASS));
-            _cpld_regs->rf0_reg5.set(rm::rf0_reg5_t::HB_PREAMP_EN_CH2, bool2bin(value==PREAMP_HIGHBAND));
-            _cpld_regs->rf2_reg6.set(rm::rf2_reg6_t::LB_PREAMP_EN_CH2, bool2bin(value==PREAMP_LOWBAND));
-        }
-        if (commit) _commit();
+            _cpld_regs->rf0_reg7.set(
+                rm::rf0_reg7_t::SWPA1_CTRL_CH2, bool2bin(value == PREAMP_HIGHBAND));
+            _cpld_regs->rf2_reg5.set(
+                rm::rf2_reg5_t::SWPA2_CTRL_CH2, bool2bin(value == PREAMP_BYPASS));
+            _cpld_regs->rf0_reg5.set(
+                rm::rf0_reg5_t::HB_PREAMP_EN_CH2, bool2bin(value == PREAMP_HIGHBAND));
+            _cpld_regs->rf2_reg6.set(
+                rm::rf2_reg6_t::LB_PREAMP_EN_CH2, bool2bin(value == PREAMP_LOWBAND));
+        }
+        if (commit)
+            _commit();
     }
 
     void set_preamp2(channel_t ch, bool enabled, bool commit = true)
     {
         boost::lock_guard<boost::mutex> lock(_mutex);
         if (ch == CH1 or ch == BOTH) {
-            _cpld_regs->rf2_reg7.set(rm::rf2_reg7_t::SWPA4_CTRL_CH1, bool2bin(not enabled));
+            _cpld_regs->rf2_reg7.set(
+                rm::rf2_reg7_t::SWPA4_CTRL_CH1, bool2bin(not enabled));
             _cpld_regs->rf2_reg3.set(rm::rf2_reg3_t::PREAMP2_EN_CH1, bool2bin(enabled));
         }
         if (ch == CH2 or ch == BOTH) {
-            _cpld_regs->rf0_reg6.set(rm::rf0_reg6_t::SWPA4_CTRL_CH2, bool2bin(not enabled));
+            _cpld_regs->rf0_reg6.set(
+                rm::rf0_reg6_t::SWPA4_CTRL_CH2, bool2bin(not enabled));
             _cpld_regs->rf1_reg6.set(rm::rf1_reg6_t::PREAMP2_EN_CH2, bool2bin(enabled));
         }
-        if (commit) _commit();
+        if (commit)
+            _commit();
     }
 
     void set_lb_preamp_preselector(channel_t ch, bool enabled, bool commit = true)
     {
         boost::lock_guard<boost::mutex> lock(_mutex);
         if (ch == CH1 or ch == BOTH) {
-            _cpld_regs->rf0_reg7.set(rm::rf0_reg7_t::SWPA3_CTRL_CH1, bool2bin(not enabled));
+            _cpld_regs->rf0_reg7.set(
+                rm::rf0_reg7_t::SWPA3_CTRL_CH1, bool2bin(not enabled));
         }
         if (ch == CH2 or ch == BOTH) {
-            _cpld_regs->rf0_reg1.set(rm::rf0_reg1_t::SWPA3_CTRL_CH2, bool2bin(not enabled));
+            _cpld_regs->rf0_reg1.set(
+                rm::rf0_reg1_t::SWPA3_CTRL_CH2, bool2bin(not enabled));
         }
-        if (commit) _commit();
+        if (commit)
+            _commit();
     }
 
     void set_signal_path(channel_t ch, signal_path_t path, bool commit = true)
     {
         boost::lock_guard<boost::mutex> lock(_mutex);
         if (ch == CH1 or ch == BOTH) {
-            _cpld_regs->rf2_reg2.set(rm::rf2_reg2_t::SW11_CTRL_CH1, bool2bin(path==PATH_LOWBAND));
-            _cpld_regs->rf1_reg2.set(rm::rf1_reg2_t::SW12_CTRL_CH1, bool2bin(path==PATH_LOWBAND));
-            _cpld_regs->rf1_reg6.set(rm::rf1_reg6_t::HB_PRESEL_PGA_EN_CH1, bool2bin(path==PATH_HIGHBAND));
-            _cpld_regs->rf0_reg2.set(rm::rf0_reg2_t::SW6_CTRL_CH1, bool2bin(path==PATH_LOWBAND));
-            _cpld_regs->if0_reg3.set(rm::if0_reg3_t::SW13_CTRL_CH1, bool2bin(path==PATH_LOWBAND));
-            _cpld_regs->if0_reg2.set(rm::if0_reg2_t::AMP_LB_IF1_EN_CH1, bool2bin(path==PATH_LOWBAND));
-            _cpld_regs->if0_reg0.set(rm::if0_reg0_t::AMP_HB_IF1_EN_CH1, bool2bin(path==PATH_HIGHBAND));
-            _cpld_regs->rf1_reg2.set(rm::rf1_reg2_t::AMP_HB_EN_CH1, bool2bin(path==PATH_HIGHBAND));
-            _cpld_regs->rf2_reg2.set(rm::rf2_reg2_t::AMP_LB_EN_CH1, bool2bin(path==PATH_LOWBAND));
+            _cpld_regs->rf2_reg2.set(
+                rm::rf2_reg2_t::SW11_CTRL_CH1, bool2bin(path == PATH_LOWBAND));
+            _cpld_regs->rf1_reg2.set(
+                rm::rf1_reg2_t::SW12_CTRL_CH1, bool2bin(path == PATH_LOWBAND));
+            _cpld_regs->rf1_reg6.set(
+                rm::rf1_reg6_t::HB_PRESEL_PGA_EN_CH1, bool2bin(path == PATH_HIGHBAND));
+            _cpld_regs->rf0_reg2.set(
+                rm::rf0_reg2_t::SW6_CTRL_CH1, bool2bin(path == PATH_LOWBAND));
+            _cpld_regs->if0_reg3.set(
+                rm::if0_reg3_t::SW13_CTRL_CH1, bool2bin(path == PATH_LOWBAND));
+            _cpld_regs->if0_reg2.set(
+                rm::if0_reg2_t::AMP_LB_IF1_EN_CH1, bool2bin(path == PATH_LOWBAND));
+            _cpld_regs->if0_reg0.set(
+                rm::if0_reg0_t::AMP_HB_IF1_EN_CH1, bool2bin(path == PATH_HIGHBAND));
+            _cpld_regs->rf1_reg2.set(
+                rm::rf1_reg2_t::AMP_HB_EN_CH1, bool2bin(path == PATH_HIGHBAND));
+            _cpld_regs->rf2_reg2.set(
+                rm::rf2_reg2_t::AMP_LB_EN_CH1, bool2bin(path == PATH_LOWBAND));
         }
         if (ch == CH2 or ch == BOTH) {
-            _cpld_regs->rf2_reg7.set(rm::rf2_reg7_t::SW11_CTRL_CH2, bool2bin(path==PATH_LOWBAND));
-            _cpld_regs->rf1_reg7.set(rm::rf1_reg7_t::SW12_CTRL_CH2, bool2bin(path==PATH_LOWBAND));
-            _cpld_regs->rf1_reg2.set(rm::rf1_reg2_t::HB_PRESEL_PGA_EN_CH2, bool2bin(path==PATH_HIGHBAND));
-            _cpld_regs->rf0_reg6.set(rm::rf0_reg6_t::SW6_CTRL_CH2, bool2bin(path==PATH_HIGHBAND));
-            _cpld_regs->if0_reg6.set(rm::if0_reg6_t::SW13_CTRL_CH2, bool2bin(path==PATH_HIGHBAND));
-            _cpld_regs->if0_reg2.set(rm::if0_reg2_t::AMP_LB_IF1_EN_CH2, bool2bin(path==PATH_LOWBAND));
-            _cpld_regs->if0_reg6.set(rm::if0_reg6_t::AMP_HB_IF1_EN_CH2, bool2bin(path==PATH_HIGHBAND));
-            _cpld_regs->rf1_reg7.set(rm::rf1_reg7_t::AMP_HB_EN_CH2, bool2bin(path==PATH_HIGHBAND));
-            _cpld_regs->rf2_reg7.set(rm::rf2_reg7_t::AMP_LB_EN_CH2, bool2bin(path==PATH_LOWBAND));
-        }
-        if (commit) _commit();
+            _cpld_regs->rf2_reg7.set(
+                rm::rf2_reg7_t::SW11_CTRL_CH2, bool2bin(path == PATH_LOWBAND));
+            _cpld_regs->rf1_reg7.set(
+                rm::rf1_reg7_t::SW12_CTRL_CH2, bool2bin(path == PATH_LOWBAND));
+            _cpld_regs->rf1_reg2.set(
+                rm::rf1_reg2_t::HB_PRESEL_PGA_EN_CH2, bool2bin(path == PATH_HIGHBAND));
+            _cpld_regs->rf0_reg6.set(
+                rm::rf0_reg6_t::SW6_CTRL_CH2, bool2bin(path == PATH_HIGHBAND));
+            _cpld_regs->if0_reg6.set(
+                rm::if0_reg6_t::SW13_CTRL_CH2, bool2bin(path == PATH_HIGHBAND));
+            _cpld_regs->if0_reg2.set(
+                rm::if0_reg2_t::AMP_LB_IF1_EN_CH2, bool2bin(path == PATH_LOWBAND));
+            _cpld_regs->if0_reg6.set(
+                rm::if0_reg6_t::AMP_HB_IF1_EN_CH2, bool2bin(path == PATH_HIGHBAND));
+            _cpld_regs->rf1_reg7.set(
+                rm::rf1_reg7_t::AMP_HB_EN_CH2, bool2bin(path == PATH_HIGHBAND));
+            _cpld_regs->rf2_reg7.set(
+                rm::rf2_reg7_t::AMP_LB_EN_CH2, bool2bin(path == PATH_LOWBAND));
+        }
+        if (commit)
+            _commit();
     }
 
     void set_lb_preselector(channel_t ch, preselector_path_t path, bool commit = true)
@@ -252,11 +289,24 @@ public:
         boost::lock_guard<boost::mutex> lock(_mutex);
         uint32_t sw7val = 0, sw8val = 0;
         switch (path) {
-            case PRESEL_PATH1: sw7val = 3; sw8val = 1; break;
-            case PRESEL_PATH2: sw7val = 2; sw8val = 0; break;
-            case PRESEL_PATH3: sw7val = 0; sw8val = 2; break;
-            case PRESEL_PATH4: sw7val = 1; sw8val = 3; break;
-            default: UHD_THROW_INVALID_CODE_PATH();
+            case PRESEL_PATH1:
+                sw7val = 3;
+                sw8val = 1;
+                break;
+            case PRESEL_PATH2:
+                sw7val = 2;
+                sw8val = 0;
+                break;
+            case PRESEL_PATH3:
+                sw7val = 0;
+                sw8val = 2;
+                break;
+            case PRESEL_PATH4:
+                sw7val = 1;
+                sw8val = 3;
+                break;
+            default:
+                UHD_THROW_INVALID_CODE_PATH();
         }
         if (ch == CH1 or ch == BOTH) {
             _cpld_regs->rf0_reg3.set(rm::rf0_reg3_t::SW7_CTRL_CH1, sw7val);
@@ -266,7 +316,8 @@ public:
             _cpld_regs->rf0_reg7.set(rm::rf0_reg7_t::SW7_CTRL_CH2, sw7val);
             _cpld_regs->rf2_reg7.set(rm::rf2_reg7_t::SW8_CTRL_CH2, sw8val);
         }
-        if (commit) _commit();
+        if (commit)
+            _commit();
     }
 
     void set_hb_preselector(channel_t ch, preselector_path_t path, bool commit = true)
@@ -274,11 +325,32 @@ public:
         boost::lock_guard<boost::mutex> lock(_mutex);
         uint32_t sw9ch1val = 0, sw10ch1val = 0, sw9ch2val = 0, sw10ch2val = 0;
         switch (path) {
-            case PRESEL_PATH1: sw9ch1val = 3; sw10ch1val = 0; sw9ch2val = 0; sw10ch2val = 3; break;
-            case PRESEL_PATH2: sw9ch1val = 1; sw10ch1val = 2; sw9ch2val = 1; sw10ch2val = 1; break;
-            case PRESEL_PATH3: sw9ch1val = 2; sw10ch1val = 1; sw9ch2val = 2; sw10ch2val = 2; break;
-            case PRESEL_PATH4: sw9ch1val = 0; sw10ch1val = 3; sw9ch2val = 3; sw10ch2val = 0; break;
-            default: UHD_THROW_INVALID_CODE_PATH();
+            case PRESEL_PATH1:
+                sw9ch1val  = 3;
+                sw10ch1val = 0;
+                sw9ch2val  = 0;
+                sw10ch2val = 3;
+                break;
+            case PRESEL_PATH2:
+                sw9ch1val  = 1;
+                sw10ch1val = 2;
+                sw9ch2val  = 1;
+                sw10ch2val = 1;
+                break;
+            case PRESEL_PATH3:
+                sw9ch1val  = 2;
+                sw10ch1val = 1;
+                sw9ch2val  = 2;
+                sw10ch2val = 2;
+                break;
+            case PRESEL_PATH4:
+                sw9ch1val  = 0;
+                sw10ch1val = 3;
+                sw9ch2val  = 3;
+                sw10ch2val = 0;
+                break;
+            default:
+                UHD_THROW_INVALID_CODE_PATH();
         }
         if (ch == CH1 or ch == BOTH) {
             _cpld_regs->rf0_reg5.set(rm::rf0_reg5_t::SW9_CTRL_CH1, sw9ch1val);
@@ -288,104 +360,129 @@ public:
             _cpld_regs->rf0_reg3.set(rm::rf0_reg3_t::SW9_CTRL_CH2, sw9ch2val);
             _cpld_regs->rf1_reg7.set(rm::rf1_reg7_t::SW10_CTRL_CH2, sw10ch2val);
         }
-        if (commit) _commit();
-
+        if (commit)
+            _commit();
     }
 
     void set_input_atten(channel_t ch, uint8_t atten, bool commit = true)
     {
         boost::lock_guard<boost::mutex> lock(_mutex);
         if (ch == CH1 or ch == BOTH) {
-            _cpld_regs->rf0_reg0.set(rm::rf0_reg0_t::ATTEN_IN_CH1, atten&0x1F);
+            _cpld_regs->rf0_reg0.set(rm::rf0_reg0_t::ATTEN_IN_CH1, atten & 0x1F);
         }
         if (ch == CH2 or ch == BOTH) {
-            _cpld_regs->rf0_reg4.set(rm::rf0_reg4_t::ATTEN_IN_CH2, atten&0x1F);
+            _cpld_regs->rf0_reg4.set(rm::rf0_reg4_t::ATTEN_IN_CH2, atten & 0x1F);
         }
-        if (commit) _commit();
+        if (commit)
+            _commit();
     }
 
     void set_lb_atten(channel_t ch, uint8_t atten, bool commit = true)
     {
         boost::lock_guard<boost::mutex> lock(_mutex);
         if (ch == CH1 or ch == BOTH) {
-            _cpld_regs->rf2_reg0.set(rm::rf2_reg0_t::ATTEN_LB_CH1, atten&0x1F);
+            _cpld_regs->rf2_reg0.set(rm::rf2_reg0_t::ATTEN_LB_CH1, atten & 0x1F);
         }
         if (ch == CH2 or ch == BOTH) {
-            _cpld_regs->rf2_reg4.set(rm::rf2_reg4_t::ATTEN_LB_CH2, atten&0x1F);
+            _cpld_regs->rf2_reg4.set(rm::rf2_reg4_t::ATTEN_LB_CH2, atten & 0x1F);
         }
-        if (commit) _commit();
+        if (commit)
+            _commit();
     }
 
     void set_hb_atten(channel_t ch, uint8_t atten, bool commit = true)
     {
         boost::lock_guard<boost::mutex> lock(_mutex);
         if (ch == CH1 or ch == BOTH) {
-            _cpld_regs->rf1_reg0.set(rm::rf1_reg0_t::ATTEN_HB_CH1, atten&0x1F);
+            _cpld_regs->rf1_reg0.set(rm::rf1_reg0_t::ATTEN_HB_CH1, atten & 0x1F);
         }
         if (ch == CH2 or ch == BOTH) {
-            _cpld_regs->rf1_reg4.set(rm::rf1_reg4_t::ATTEN_HB_CH2, atten&0x1F);
+            _cpld_regs->rf1_reg4.set(rm::rf1_reg4_t::ATTEN_HB_CH2, atten & 0x1F);
         }
-        if (commit) _commit();
+        if (commit)
+            _commit();
     }
 
     void set_lo1_source(channel_t ch, lo_source_t source, bool commit = true)
     {
         boost::lock_guard<boost::mutex> lock(_mutex);
         if (ch == CH1 or ch == BOTH) {
-            _cpld_regs->rf1_reg5.set(rm::rf1_reg5_t::SW14_CTRL_CH2, bool2bin(source!=LO_COMPANION));
-            _cpld_regs->rf1_reg1.set(rm::rf1_reg1_t::SW15_CTRL_CH1, bool2bin(source==LO_EXTERNAL||source==LO_REIMPORT));
-            _cpld_regs->rf1_reg1.set(rm::rf1_reg1_t::SW16_CTRL_CH1, bool2bin(source!=LO_INTERNAL));
+            _cpld_regs->rf1_reg5.set(
+                rm::rf1_reg5_t::SW14_CTRL_CH2, bool2bin(source != LO_COMPANION));
+            _cpld_regs->rf1_reg1.set(rm::rf1_reg1_t::SW15_CTRL_CH1,
+                bool2bin(source == LO_EXTERNAL || source == LO_REIMPORT));
+            _cpld_regs->rf1_reg1.set(
+                rm::rf1_reg1_t::SW16_CTRL_CH1, bool2bin(source != LO_INTERNAL));
             _lo1_src[size_t(CH1)] = source;
         }
         if (ch == CH2 or ch == BOTH) {
-            _cpld_regs->rf1_reg1.set(rm::rf1_reg1_t::SW14_CTRL_CH1, bool2bin(source==LO_COMPANION));
-            _cpld_regs->rf1_reg5.set(rm::rf1_reg5_t::SW15_CTRL_CH2, bool2bin(source!=LO_INTERNAL));
-            _cpld_regs->rf1_reg6.set(rm::rf1_reg6_t::SW16_CTRL_CH2, bool2bin(source==LO_INTERNAL));
+            _cpld_regs->rf1_reg1.set(
+                rm::rf1_reg1_t::SW14_CTRL_CH1, bool2bin(source == LO_COMPANION));
+            _cpld_regs->rf1_reg5.set(
+                rm::rf1_reg5_t::SW15_CTRL_CH2, bool2bin(source != LO_INTERNAL));
+            _cpld_regs->rf1_reg6.set(
+                rm::rf1_reg6_t::SW16_CTRL_CH2, bool2bin(source == LO_INTERNAL));
             _lo1_src[size_t(CH2)] = source;
-            _set_lo1_amp(_chan_enabled[size_t(CH1)], _chan_enabled[size_t(CH2)], _lo1_src[size_t(CH2)]);
+            _set_lo1_amp(_chan_enabled[size_t(CH1)],
+                _chan_enabled[size_t(CH2)],
+                _lo1_src[size_t(CH2)]);
         }
-        if (commit) _commit();
+        if (commit)
+            _commit();
     }
 
     void set_lo2_source(channel_t ch, lo_source_t source, bool commit = true)
     {
         boost::lock_guard<boost::mutex> lock(_mutex);
         if (ch == CH1 or ch == BOTH) {
-            _cpld_regs->if0_reg0.set(rm::if0_reg0_t::SW19_CTRL_CH2, bool2bin(source==LO_COMPANION));
-            _cpld_regs->if0_reg1.set(rm::if0_reg1_t::SW20_CTRL_CH1, bool2bin(source==LO_COMPANION));
-            _cpld_regs->if0_reg4.set(rm::if0_reg4_t::SW21_CTRL_CH1, bool2bin(source==LO_INTERNAL));
+            _cpld_regs->if0_reg0.set(
+                rm::if0_reg0_t::SW19_CTRL_CH2, bool2bin(source == LO_COMPANION));
+            _cpld_regs->if0_reg1.set(
+                rm::if0_reg1_t::SW20_CTRL_CH1, bool2bin(source == LO_COMPANION));
+            _cpld_regs->if0_reg4.set(
+                rm::if0_reg4_t::SW21_CTRL_CH1, bool2bin(source == LO_INTERNAL));
             _lo2_src[size_t(CH1)] = source;
         }
         if (ch == CH2 or ch == BOTH) {
-            _cpld_regs->if0_reg4.set(rm::if0_reg4_t::SW19_CTRL_CH1, bool2bin(source==LO_EXTERNAL||source==LO_REIMPORT));
-            _cpld_regs->if0_reg0.set(rm::if0_reg0_t::SW20_CTRL_CH2, bool2bin(source==LO_INTERNAL||source==LO_DISABLED));
-            _cpld_regs->if0_reg4.set(rm::if0_reg4_t::SW21_CTRL_CH2, bool2bin(source==LO_INTERNAL));
+            _cpld_regs->if0_reg4.set(rm::if0_reg4_t::SW19_CTRL_CH1,
+                bool2bin(source == LO_EXTERNAL || source == LO_REIMPORT));
+            _cpld_regs->if0_reg0.set(rm::if0_reg0_t::SW20_CTRL_CH2,
+                bool2bin(source == LO_INTERNAL || source == LO_DISABLED));
+            _cpld_regs->if0_reg4.set(
+                rm::if0_reg4_t::SW21_CTRL_CH2, bool2bin(source == LO_INTERNAL));
             _lo2_src[size_t(CH2)] = source;
         }
-        if (commit) _commit();
+        if (commit)
+            _commit();
     }
 
     void set_lo1_export_source(lo_export_source_t source, bool commit = true)
     {
         boost::lock_guard<boost::mutex> lock(_mutex);
-        //SW22 may conflict with the cal switch but this attr takes priority and we assume
-        //that the cal switch is disabled (by disabling it!)
+        // SW22 may conflict with the cal switch but this attr takes priority and we
+        // assume that the cal switch is disabled (by disabling it!)
         _set_cal_mode(CAL_DISABLED, source);
-        _cpld_regs->rf1_reg3.set(rm::rf1_reg3_t::SW23_CTRL, bool2bin(source!=LO_CH1_SYNTH));
+        _cpld_regs->rf1_reg3.set(
+            rm::rf1_reg3_t::SW23_CTRL, bool2bin(source != LO_CH1_SYNTH));
         _lo1_export = source;
 
-        if (commit) _commit();
+        if (commit)
+            _commit();
     }
 
     void set_lo2_export_source(lo_export_source_t source, bool commit = true)
     {
         boost::lock_guard<boost::mutex> lock(_mutex);
-        _cpld_regs->if0_reg7.set(rm::if0_reg7_t::SW24_CTRL_CH2, bool2bin(source==LO_CH2_SYNTH));
-        _cpld_regs->if0_reg4.set(rm::if0_reg4_t::SW25_CTRL, bool2bin(source!=LO_CH1_SYNTH));
-        _cpld_regs->if0_reg3.set(rm::if0_reg3_t::SW24_CTRL_CH1, bool2bin(source!=LO_CH1_SYNTH));
+        _cpld_regs->if0_reg7.set(
+            rm::if0_reg7_t::SW24_CTRL_CH2, bool2bin(source == LO_CH2_SYNTH));
+        _cpld_regs->if0_reg4.set(
+            rm::if0_reg4_t::SW25_CTRL, bool2bin(source != LO_CH1_SYNTH));
+        _cpld_regs->if0_reg3.set(
+            rm::if0_reg3_t::SW24_CTRL_CH1, bool2bin(source != LO_CH1_SYNTH));
         _lo2_export = source;
 
-        if (commit) _commit();
+        if (commit)
+            _commit();
     }
 
     void set_antenna_mapping(antenna_mapping_t mapping, bool commit = true)
@@ -396,40 +493,60 @@ public:
         switch_path_t path1, path2;
 
         switch (mapping) {
-        case ANTX_NATIVE:
-            path1 = CONNECT; path2 = CONNECT; break;
-        case ANT1_SHARED:
-            path1 = EXPORT;  path2 = IMPORT;  break;
-        case ANT2_SHARED:
-            path1 = IMPORT;  path2 = EXPORT;  break;
-        case ANTX_SWAPPED:
-            path1 = SWAP;    path2 = SWAP;    break;
-        default:
-            path1 = TERM;    path2 = TERM;    break;
-        }
-
-        _cpld_regs->rf0_reg5.set(rm::rf0_reg5_t::SW3_CTRL_CH1, bool2bin(path1==EXPORT||path1==SWAP));
-        _cpld_regs->rf0_reg2.set(rm::rf0_reg2_t::SW4_CTRL_CH1, bool2bin(!(path1==IMPORT||path1==SWAP)));
-        _cpld_regs->rf0_reg2.set(rm::rf0_reg2_t::SW5_CTRL_CH1, bool2bin(path1==CONNECT));
-        _cpld_regs->rf0_reg7.set(rm::rf0_reg7_t::SW3_CTRL_CH2, bool2bin(path2==EXPORT||path2==SWAP));
-        _cpld_regs->rf0_reg6.set(rm::rf0_reg6_t::SW4_CTRL_CH2, bool2bin(path2==IMPORT||path2==SWAP));
-        _cpld_regs->rf0_reg6.set(rm::rf0_reg6_t::SW5_CTRL_CH2, bool2bin(path2==CONNECT));
-
-        if (commit) _commit();
+            case ANTX_NATIVE:
+                path1 = CONNECT;
+                path2 = CONNECT;
+                break;
+            case ANT1_SHARED:
+                path1 = EXPORT;
+                path2 = IMPORT;
+                break;
+            case ANT2_SHARED:
+                path1 = IMPORT;
+                path2 = EXPORT;
+                break;
+            case ANTX_SWAPPED:
+                path1 = SWAP;
+                path2 = SWAP;
+                break;
+            default:
+                path1 = TERM;
+                path2 = TERM;
+                break;
+        }
+
+        _cpld_regs->rf0_reg5.set(
+            rm::rf0_reg5_t::SW3_CTRL_CH1, bool2bin(path1 == EXPORT || path1 == SWAP));
+        _cpld_regs->rf0_reg2.set(
+            rm::rf0_reg2_t::SW4_CTRL_CH1, bool2bin(!(path1 == IMPORT || path1 == SWAP)));
+        _cpld_regs->rf0_reg2.set(
+            rm::rf0_reg2_t::SW5_CTRL_CH1, bool2bin(path1 == CONNECT));
+        _cpld_regs->rf0_reg7.set(
+            rm::rf0_reg7_t::SW3_CTRL_CH2, bool2bin(path2 == EXPORT || path2 == SWAP));
+        _cpld_regs->rf0_reg6.set(
+            rm::rf0_reg6_t::SW4_CTRL_CH2, bool2bin(path2 == IMPORT || path2 == SWAP));
+        _cpld_regs->rf0_reg6.set(
+            rm::rf0_reg6_t::SW5_CTRL_CH2, bool2bin(path2 == CONNECT));
+
+        if (commit)
+            _commit();
     }
 
     void set_crossover_cal_mode(cal_mode_t cal_mode, bool commit = true)
     {
         boost::lock_guard<boost::mutex> lock(_mutex);
         if (_lo1_export == LO_CH1_SYNTH && cal_mode == CAL_CH2) {
-            throw uhd::runtime_error("cannot enable cal crossover on CH2 when LO1 in CH1 is exported");
+            throw uhd::runtime_error(
+                "cannot enable cal crossover on CH2 when LO1 in CH1 is exported");
         }
         if (_lo1_export == LO_CH2_SYNTH && cal_mode == CAL_CH1) {
-            throw uhd::runtime_error("cannot enable cal crossover on CH1 when LO1 in CH2 is exported");
+            throw uhd::runtime_error(
+                "cannot enable cal crossover on CH1 when LO1 in CH2 is exported");
         }
         _set_cal_mode(cal_mode, _lo1_export);
 
-        if (commit) _commit();
+        if (commit)
+            _commit();
     }
 
     double set_lo1_synth_freq(channel_t ch, double freq, bool commit = true)
@@ -439,15 +556,18 @@ public:
 
         double coerced_freq = 0.0;
         if (ch == CH1 or ch == BOTH) {
-            coerced_freq = _lo1_iface[size_t(CH1)]->set_frequency(freq, RESOLUTION, false);
+            coerced_freq =
+                _lo1_iface[size_t(CH1)]->set_frequency(freq, RESOLUTION, false);
             _lo1_freq[size_t(CH1)] = tune_freq_t(freq);
         }
         if (ch == CH2 or ch == BOTH) {
-            coerced_freq = _lo1_iface[size_t(CH2)]->set_frequency(freq, RESOLUTION, false);
+            coerced_freq =
+                _lo1_iface[size_t(CH2)]->set_frequency(freq, RESOLUTION, false);
             _lo1_freq[size_t(CH2)] = tune_freq_t(freq);
         }
 
-        if (commit) _commit();
+        if (commit)
+            _commit();
         return coerced_freq;
     }
 
@@ -465,7 +585,8 @@ public:
             _lo2_freq[size_t(CH2)] = tune_freq_t(freq);
         }
 
-        if (commit) _commit();
+        if (commit)
+            _commit();
         return coerced_freq;
     }
 
@@ -525,10 +646,12 @@ public:
 
         bool locked = true;
         if (ch == CH1 or ch == BOTH) {
-            locked = locked && (_gpio_iface->get_field(twinrx_gpio::FIELD_LO1_MUXOUT_CH1) == 1);
+            locked = locked
+                     && (_gpio_iface->get_field(twinrx_gpio::FIELD_LO1_MUXOUT_CH1) == 1);
         }
         if (ch == CH2 or ch == BOTH) {
-            locked = locked && (_gpio_iface->get_field(twinrx_gpio::FIELD_LO1_MUXOUT_CH2) == 1);
+            locked = locked
+                     && (_gpio_iface->get_field(twinrx_gpio::FIELD_LO1_MUXOUT_CH2) == 1);
         }
         return locked;
     }
@@ -539,102 +662,124 @@ public:
 
         bool locked = true;
         if (ch == CH1 or ch == BOTH) {
-            locked = locked && (_gpio_iface->get_field(twinrx_gpio::FIELD_LO2_MUXOUT_CH1) == 1);
+            locked = locked
+                     && (_gpio_iface->get_field(twinrx_gpio::FIELD_LO2_MUXOUT_CH1) == 1);
         }
         if (ch == CH2 or ch == BOTH) {
-            locked = locked && (_gpio_iface->get_field(twinrx_gpio::FIELD_LO2_MUXOUT_CH2) == 1);
+            locked = locked
+                     && (_gpio_iface->get_field(twinrx_gpio::FIELD_LO2_MUXOUT_CH2) == 1);
         }
         return locked;
     }
 
-private:    //Functions
+private: // Functions
     void _set_cal_mode(cal_mode_t cal_mode, lo_export_source_t lo1_export_src)
     {
-        _cpld_regs->rf1_reg1.set(rm::rf1_reg1_t::SW17_CTRL_CH1, bool2bin(cal_mode!=CAL_CH1));
-        _cpld_regs->rf1_reg6.set(rm::rf1_reg6_t::SW17_CTRL_CH2, bool2bin(cal_mode!=CAL_CH2));
-        _cpld_regs->rf1_reg5.set(rm::rf1_reg5_t::SW18_CTRL_CH1, bool2bin(cal_mode!=CAL_CH1));
-        _cpld_regs->rf2_reg3.set(rm::rf2_reg3_t::SW18_CTRL_CH2, bool2bin(cal_mode!=CAL_CH2));
-        _cpld_regs->rf1_reg3.set(rm::rf1_reg3_t::SW22_CTRL_CH1, bool2bin((lo1_export_src!=LO_CH1_SYNTH)||(cal_mode==CAL_CH1)));
-        _cpld_regs->rf1_reg7.set(rm::rf1_reg7_t::SW22_CTRL_CH2, bool2bin((lo1_export_src!=LO_CH2_SYNTH)||(cal_mode==CAL_CH2)));
+        _cpld_regs->rf1_reg1.set(
+            rm::rf1_reg1_t::SW17_CTRL_CH1, bool2bin(cal_mode != CAL_CH1));
+        _cpld_regs->rf1_reg6.set(
+            rm::rf1_reg6_t::SW17_CTRL_CH2, bool2bin(cal_mode != CAL_CH2));
+        _cpld_regs->rf1_reg5.set(
+            rm::rf1_reg5_t::SW18_CTRL_CH1, bool2bin(cal_mode != CAL_CH1));
+        _cpld_regs->rf2_reg3.set(
+            rm::rf2_reg3_t::SW18_CTRL_CH2, bool2bin(cal_mode != CAL_CH2));
+        _cpld_regs->rf1_reg3.set(rm::rf1_reg3_t::SW22_CTRL_CH1,
+            bool2bin((lo1_export_src != LO_CH1_SYNTH) || (cal_mode == CAL_CH1)));
+        _cpld_regs->rf1_reg7.set(rm::rf1_reg7_t::SW22_CTRL_CH2,
+            bool2bin((lo1_export_src != LO_CH2_SYNTH) || (cal_mode == CAL_CH2)));
     }
 
     void _set_lo1_amp(bool ch1_enabled, bool ch2_enabled, lo_source_t ch2_lo1_src)
     {
         // AMP_LO1_EN_CH1 also controls the amp for the external LO1 port,
         // which could be in use by ch2
-        _cpld_regs->rf1_reg1.set(rm::rf1_reg1_t::AMP_LO1_EN_CH1, bool2bin(
-            ch1_enabled || (ch2_enabled && (ch2_lo1_src == LO_EXTERNAL || ch2_lo1_src == LO_REIMPORT))));
+        _cpld_regs->rf1_reg1.set(rm::rf1_reg1_t::AMP_LO1_EN_CH1,
+            bool2bin(
+                ch1_enabled
+                || (ch2_enabled
+                       && (ch2_lo1_src == LO_EXTERNAL || ch2_lo1_src == LO_REIMPORT))));
     }
 
     void _config_lo_route(lo_t lo, channel_t channel)
     {
-        //Route SPI LEs through CPLD (will not assert them)
-        _cpld_regs->rf0_reg2.set(rm::rf0_reg2_t::LO1_LE_CH1, bool2bin(lo == LO1 and (channel == CH1 or channel == BOTH)));
-        _cpld_regs->rf0_reg2.set(rm::rf0_reg2_t::LO1_LE_CH2, bool2bin(lo == LO1 and (channel == CH2 or channel == BOTH)));
+        // Route SPI LEs through CPLD (will not assert them)
+        _cpld_regs->rf0_reg2.set(rm::rf0_reg2_t::LO1_LE_CH1,
+            bool2bin(lo == LO1 and (channel == CH1 or channel == BOTH)));
+        _cpld_regs->rf0_reg2.set(rm::rf0_reg2_t::LO1_LE_CH2,
+            bool2bin(lo == LO1 and (channel == CH2 or channel == BOTH)));
         _cpld_regs->rf0_reg2.flush();
-        _cpld_regs->if0_reg2.set(rm::if0_reg2_t::LO2_LE_CH1, bool2bin(lo == LO2 and (channel == CH1 or channel == BOTH)));
-        _cpld_regs->if0_reg2.set(rm::if0_reg2_t::LO2_LE_CH2, bool2bin(lo == LO2 and (channel == CH2 or channel == BOTH)));
+        _cpld_regs->if0_reg2.set(rm::if0_reg2_t::LO2_LE_CH1,
+            bool2bin(lo == LO2 and (channel == CH1 or channel == BOTH)));
+        _cpld_regs->if0_reg2.set(rm::if0_reg2_t::LO2_LE_CH2,
+            bool2bin(lo == LO2 and (channel == CH2 or channel == BOTH)));
         _cpld_regs->if0_reg2.flush();
     }
 
-    void _write_lo_spi(dboard_iface::unit_t unit, const std::vector<uint32_t> &regs)
+    void _write_lo_spi(dboard_iface::unit_t unit, const std::vector<uint32_t>& regs)
     {
-        for(uint32_t reg:  regs) {
+        for (uint32_t reg : regs) {
             _db_iface->write_spi(unit, _spi_config, reg, 32);
         }
     }
 
     void _commit()
     {
-        //Commit everything except the LO synthesizers
+        // Commit everything except the LO synthesizers
         _cpld_regs->flush();
 
         // Disable unused LO synthesizers
-        _lo1_enable[size_t(CH1)] = _lo1_src[size_t(CH1)] == LO_INTERNAL  ||
-                                   _lo1_src[size_t(CH2)] == LO_COMPANION ||
-                                   _lo1_export == LO_CH1_SYNTH;
-
-        _lo1_enable[size_t(CH2)] = _lo1_src[size_t(CH2)] == LO_INTERNAL  ||
-                                   _lo1_src[size_t(CH1)] == LO_COMPANION ||
-                                   _lo1_export == LO_CH2_SYNTH;
-        _lo2_enable[size_t(CH1)] = _lo2_src[size_t(CH1)] == LO_INTERNAL  ||
-                                   _lo2_src[size_t(CH2)] == LO_COMPANION ||
-                                   _lo2_export == LO_CH1_SYNTH;
-
-        _lo2_enable[size_t(CH2)] = _lo2_src[size_t(CH2)] == LO_INTERNAL  ||
-                                   _lo2_src[size_t(CH1)] == LO_COMPANION ||
-                                   _lo2_export == LO_CH2_SYNTH;
-
-        _lo1_iface[size_t(CH1)]->set_output_enable(adf535x_iface::RF_OUTPUT_A, _lo1_enable[size_t(CH1)].get());
-        _lo1_iface[size_t(CH2)]->set_output_enable(adf535x_iface::RF_OUTPUT_A, _lo1_enable[size_t(CH2)].get());
-
-        _lo2_iface[size_t(CH1)]->set_output_enable(adf435x_iface::RF_OUTPUT_A, _lo2_enable[size_t(CH1)].get());
-        _lo2_iface[size_t(CH2)]->set_output_enable(adf435x_iface::RF_OUTPUT_A, _lo2_enable[size_t(CH2)].get());
-
-        //Commit LO1 frequency
-        // Commit Channel 1's settings to both channels simultaneously if the frequency is the same.
-        bool simultaneous_commit_lo1 = _lo1_freq[size_t(CH1)].is_dirty() and
-                                       _lo1_freq[size_t(CH2)].is_dirty() and
-                                       _lo1_freq[size_t(CH1)].get() == _lo1_freq[size_t(CH2)].get() and
-                                       _lo1_enable[size_t(CH1)].get() == _lo1_enable[size_t(CH2)].get();
+        _lo1_enable[size_t(CH1)] = _lo1_src[size_t(CH1)] == LO_INTERNAL
+                                   || _lo1_src[size_t(CH2)] == LO_COMPANION
+                                   || _lo1_export == LO_CH1_SYNTH;
+
+        _lo1_enable[size_t(CH2)] = _lo1_src[size_t(CH2)] == LO_INTERNAL
+                                   || _lo1_src[size_t(CH1)] == LO_COMPANION
+                                   || _lo1_export == LO_CH2_SYNTH;
+        _lo2_enable[size_t(CH1)] = _lo2_src[size_t(CH1)] == LO_INTERNAL
+                                   || _lo2_src[size_t(CH2)] == LO_COMPANION
+                                   || _lo2_export == LO_CH1_SYNTH;
+
+        _lo2_enable[size_t(CH2)] = _lo2_src[size_t(CH2)] == LO_INTERNAL
+                                   || _lo2_src[size_t(CH1)] == LO_COMPANION
+                                   || _lo2_export == LO_CH2_SYNTH;
+
+        _lo1_iface[size_t(CH1)]->set_output_enable(
+            adf535x_iface::RF_OUTPUT_A, _lo1_enable[size_t(CH1)].get());
+        _lo1_iface[size_t(CH2)]->set_output_enable(
+            adf535x_iface::RF_OUTPUT_A, _lo1_enable[size_t(CH2)].get());
+
+        _lo2_iface[size_t(CH1)]->set_output_enable(
+            adf435x_iface::RF_OUTPUT_A, _lo2_enable[size_t(CH1)].get());
+        _lo2_iface[size_t(CH2)]->set_output_enable(
+            adf435x_iface::RF_OUTPUT_A, _lo2_enable[size_t(CH2)].get());
+
+        // Commit LO1 frequency
+        // Commit Channel 1's settings to both channels simultaneously if the frequency is
+        // the same.
+        bool simultaneous_commit_lo1 =
+            _lo1_freq[size_t(CH1)].is_dirty() and _lo1_freq[size_t(CH2)].is_dirty()
+            and _lo1_freq[size_t(CH1)].get() == _lo1_freq[size_t(CH2)].get()
+            and _lo1_enable[size_t(CH1)].get() == _lo1_enable[size_t(CH2)].get();
 
         if (simultaneous_commit_lo1) {
             _config_lo_route(LO1, BOTH);
-            //Only commit one of the channels. The route LO_CONFIG_BOTH
-            //will ensure that the LEs for both channels are enabled
+            // Only commit one of the channels. The route LO_CONFIG_BOTH
+            // will ensure that the LEs for both channels are enabled
             _lo1_iface[size_t(CH1)]->commit();
             _lo1_freq[size_t(CH1)].mark_clean();
             _lo1_freq[size_t(CH2)].mark_clean();
             _lo1_enable[size_t(CH1)].mark_clean();
             _lo1_enable[size_t(CH2)].mark_clean();
         } else {
-            if (_lo1_freq[size_t(CH1)].is_dirty() || _lo1_enable[size_t(CH1)].is_dirty()) {
+            if (_lo1_freq[size_t(CH1)].is_dirty()
+                || _lo1_enable[size_t(CH1)].is_dirty()) {
                 _config_lo_route(LO1, CH1);
                 _lo1_iface[size_t(CH1)]->commit();
                 _lo1_freq[size_t(CH1)].mark_clean();
                 _lo1_enable[size_t(CH1)].mark_clean();
             }
-            if (_lo1_freq[size_t(CH2)].is_dirty() || _lo1_enable[size_t(CH2)].is_dirty()) {
+            if (_lo1_freq[size_t(CH2)].is_dirty()
+                || _lo1_enable[size_t(CH2)].is_dirty()) {
                 _config_lo_route(LO1, CH2);
                 _lo1_iface[size_t(CH2)]->commit();
                 _lo1_freq[size_t(CH2)].mark_clean();
@@ -642,29 +787,31 @@ private:    //Functions
             }
         }
 
-        //Commit LO2 frequency
-        bool simultaneous_commit_lo2 = _lo2_freq[size_t(CH1)].is_dirty() and
-                                       _lo2_freq[size_t(CH2)].is_dirty() and
-                                       _lo2_freq[size_t(CH1)].get() == _lo2_freq[size_t(CH2)].get() and
-                                       _lo2_enable[size_t(CH1)].get() == _lo2_enable[size_t(CH2)].get();
+        // Commit LO2 frequency
+        bool simultaneous_commit_lo2 =
+            _lo2_freq[size_t(CH1)].is_dirty() and _lo2_freq[size_t(CH2)].is_dirty()
+            and _lo2_freq[size_t(CH1)].get() == _lo2_freq[size_t(CH2)].get()
+            and _lo2_enable[size_t(CH1)].get() == _lo2_enable[size_t(CH2)].get();
 
         if (simultaneous_commit_lo2) {
             _config_lo_route(LO2, BOTH);
-            //Only commit one of the channels. The route LO_CONFIG_BOTH
-            //will ensure that the LEs for both channels are enabled
+            // Only commit one of the channels. The route LO_CONFIG_BOTH
+            // will ensure that the LEs for both channels are enabled
             _lo2_iface[size_t(CH1)]->commit();
             _lo2_freq[size_t(CH1)].mark_clean();
             _lo2_freq[size_t(CH2)].mark_clean();
             _lo2_enable[size_t(CH1)].mark_clean();
             _lo2_enable[size_t(CH2)].mark_clean();
         } else {
-            if (_lo2_freq[size_t(CH1)].is_dirty() || _lo2_enable[size_t(CH1)].is_dirty()) {
+            if (_lo2_freq[size_t(CH1)].is_dirty()
+                || _lo2_enable[size_t(CH1)].is_dirty()) {
                 _config_lo_route(LO2, CH1);
                 _lo2_iface[size_t(CH1)]->commit();
                 _lo2_freq[size_t(CH1)].mark_clean();
                 _lo2_enable[size_t(CH1)].mark_clean();
             }
-            if (_lo2_freq[size_t(CH2)].is_dirty() || _lo2_enable[size_t(CH2)].is_dirty()) {
+            if (_lo2_freq[size_t(CH2)].is_dirty()
+                || _lo2_enable[size_t(CH2)].is_dirty()) {
                 _config_lo_route(LO2, CH2);
                 _lo2_iface[size_t(CH2)]->commit();
                 _lo2_freq[size_t(CH2)].mark_clean();
@@ -673,40 +820,46 @@ private:    //Functions
         }
     }
 
-private:    //Members
+private: // Members
     static const size_t NUM_CHANS = 2;
 
-    struct tune_freq_t : public uhd::math::fp_compare::fp_compare_delta<double> {
-        tune_freq_t() : uhd::math::fp_compare::fp_compare_delta<double>(
-            0.0, uhd::math::FREQ_COMPARISON_DELTA_HZ) {}
+    struct tune_freq_t : public uhd::math::fp_compare::fp_compare_delta<double>
+    {
+        tune_freq_t()
+            : uhd::math::fp_compare::fp_compare_delta<double>(
+                  0.0, uhd::math::FREQ_COMPARISON_DELTA_HZ)
+        {
+        }
 
-        tune_freq_t(double freq) : uhd::math::fp_compare::fp_compare_delta<double>(
-            freq, uhd::math::FREQ_COMPARISON_DELTA_HZ) {}
+        tune_freq_t(double freq)
+            : uhd::math::fp_compare::fp_compare_delta<double>(
+                  freq, uhd::math::FREQ_COMPARISON_DELTA_HZ)
+        {
+        }
     };
 
-    boost::mutex                _mutex;
-    dboard_iface::sptr          _db_iface;
-    twinrx_gpio::sptr           _gpio_iface;
-    twinrx_cpld_regmap::sptr    _cpld_regs;
-    spi_config_t                _spi_config;
-    adf535x_iface::sptr         _lo1_iface[NUM_CHANS];
-    adf435x_iface::sptr         _lo2_iface[NUM_CHANS];
-    lo_source_t                 _lo1_src[NUM_CHANS];
-    lo_source_t                 _lo2_src[NUM_CHANS];
-    dirty_tracked<tune_freq_t>  _lo1_freq[NUM_CHANS];
-    dirty_tracked<tune_freq_t>  _lo2_freq[NUM_CHANS];
-    dirty_tracked<bool>         _lo1_enable[NUM_CHANS];
-    dirty_tracked<bool>         _lo2_enable[NUM_CHANS];
-    lo_export_source_t          _lo1_export;
-    lo_export_source_t          _lo2_export;
-    bool                        _chan_enabled[NUM_CHANS];
+    boost::mutex _mutex;
+    dboard_iface::sptr _db_iface;
+    twinrx_gpio::sptr _gpio_iface;
+    twinrx_cpld_regmap::sptr _cpld_regs;
+    spi_config_t _spi_config;
+    adf535x_iface::sptr _lo1_iface[NUM_CHANS];
+    adf435x_iface::sptr _lo2_iface[NUM_CHANS];
+    lo_source_t _lo1_src[NUM_CHANS];
+    lo_source_t _lo2_src[NUM_CHANS];
+    dirty_tracked<tune_freq_t> _lo1_freq[NUM_CHANS];
+    dirty_tracked<tune_freq_t> _lo2_freq[NUM_CHANS];
+    dirty_tracked<bool> _lo1_enable[NUM_CHANS];
+    dirty_tracked<bool> _lo2_enable[NUM_CHANS];
+    lo_export_source_t _lo1_export;
+    lo_export_source_t _lo2_export;
+    bool _chan_enabled[NUM_CHANS];
 };
 
-twinrx_ctrl::sptr twinrx_ctrl::make(
-    dboard_iface::sptr db_iface,
+twinrx_ctrl::sptr twinrx_ctrl::make(dboard_iface::sptr db_iface,
     twinrx_gpio::sptr gpio_iface,
     twinrx_cpld_regmap::sptr cpld_regmap,
-    const dboard_id_t rx_id
-) {
+    const dboard_id_t rx_id)
+{
     return std::make_shared<twinrx_ctrl_impl>(db_iface, gpio_iface, cpld_regmap, rx_id);
 }
diff --git a/host/lib/usrp/dboard/twinrx/twinrx_ctrl.hpp b/host/lib/usrp/dboard/twinrx/twinrx_ctrl.hpp
index dfdacde11..2f4d84ed5 100644
--- a/host/lib/usrp/dboard/twinrx/twinrx_ctrl.hpp
+++ b/host/lib/usrp/dboard/twinrx/twinrx_ctrl.hpp
@@ -9,22 +9,21 @@
 #define INCLUDED_DBOARD_TWINRX_CTRL_HPP
 
 #include "twinrx_io.hpp"
+#include <uhd/types/ranges.hpp>
 #include <uhd/types/wb_iface.hpp>
 #include <uhd/utils/noncopyable.hpp>
-#include <uhd/types/ranges.hpp>
 
 namespace uhd { namespace usrp { namespace dboard { namespace twinrx {
 
-class twinrx_ctrl : public uhd::noncopyable {
+class twinrx_ctrl : public uhd::noncopyable
+{
 public:
     typedef std::shared_ptr<twinrx_ctrl> sptr;
 
-    static sptr make(
-        dboard_iface::sptr db_iface,
+    static sptr make(dboard_iface::sptr db_iface,
         twinrx_gpio::sptr gpio_iface,
         twinrx_cpld_regmap::sptr cpld_regmap,
-        dboard_id_t rx_id
-    );
+        dboard_id_t rx_id);
 
     virtual ~twinrx_ctrl() {}
 
@@ -40,7 +39,13 @@ public:
 
     enum lo_export_source_t { LO_CH1_SYNTH, LO_CH2_SYNTH, LO_EXPORT_DISABLED };
 
-    enum antenna_mapping_t { ANTX_NATIVE, ANT1_SHARED, ANT2_SHARED, ANTX_SWAPPED, ANTX_DISABLED };
+    enum antenna_mapping_t {
+        ANTX_NATIVE,
+        ANT1_SHARED,
+        ANT2_SHARED,
+        ANTX_SWAPPED,
+        ANTX_DISABLED
+    };
 
     enum cal_mode_t { CAL_DISABLED, CAL_CH1, CAL_CH2 };
 
@@ -52,13 +57,17 @@ public:
 
     virtual void set_preamp2(channel_t ch, bool enabled, bool commit = true) = 0;
 
-    virtual void set_lb_preamp_preselector(channel_t ch, bool enabled, bool commit = true) = 0;
+    virtual void set_lb_preamp_preselector(
+        channel_t ch, bool enabled, bool commit = true) = 0;
 
-    virtual void set_signal_path(channel_t ch, signal_path_t path, bool commit = true) = 0;
+    virtual void set_signal_path(
+        channel_t ch, signal_path_t path, bool commit = true) = 0;
 
-    virtual void set_lb_preselector(channel_t ch, preselector_path_t path, bool commit = true) = 0;
+    virtual void set_lb_preselector(
+        channel_t ch, preselector_path_t path, bool commit = true) = 0;
 
-    virtual void set_hb_preselector(channel_t ch, preselector_path_t path, bool commit = true) = 0;
+    virtual void set_hb_preselector(
+        channel_t ch, preselector_path_t path, bool commit = true) = 0;
 
     virtual void set_input_atten(channel_t ch, uint8_t atten, bool commit = true) = 0;
 
@@ -82,9 +91,11 @@ public:
 
     virtual double set_lo2_synth_freq(channel_t ch, double freq, bool commit = true) = 0;
 
-    virtual double set_lo1_charge_pump(channel_t ch, double current, bool commit = true) = 0;
+    virtual double set_lo1_charge_pump(
+        channel_t ch, double current, bool commit = true) = 0;
 
-    virtual double set_lo2_charge_pump(channel_t ch, double current, bool commit = true) = 0;
+    virtual double set_lo2_charge_pump(
+        channel_t ch, double current, bool commit = true) = 0;
 
     virtual uhd::meta_range_t get_lo1_charge_pump_range() = 0;
 
@@ -95,6 +106,6 @@ public:
     virtual bool read_lo2_locked(channel_t ch) = 0;
 };
 
-}}}} //namespaces
+}}}} // namespace uhd::usrp::dboard::twinrx
 
 #endif /* INCLUDED_DBOARD_TWINRX_CTRL_HPP */
diff --git a/host/lib/usrp/dboard/twinrx/twinrx_experts.cpp b/host/lib/usrp/dboard/twinrx/twinrx_experts.cpp
index f98521cc9..36bcc1863 100644
--- a/host/lib/usrp/dboard/twinrx/twinrx_experts.cpp
+++ b/host/lib/usrp/dboard/twinrx/twinrx_experts.cpp
@@ -7,12 +7,11 @@
 
 #include "twinrx_experts.hpp"
 #include "twinrx_gain_tables.hpp"
-#include <uhd/utils/math.hpp>
-#include <uhd/utils/log.hpp>
 #include <uhd/exception.hpp>
 #include <uhd/types/dict.hpp>
 #include <uhd/types/ranges.hpp>
-#include <uhd/types/dict.hpp>
+#include <uhd/utils/log.hpp>
+#include <uhd/utils/math.hpp>
 #include <boost/assign/list_of.hpp>
 #include <boost/math/special_functions/round.hpp>
 
@@ -37,15 +36,15 @@ void twinrx_scheduling_expert::resolve()
  */
 void twinrx_freq_path_expert::resolve()
 {
-    //Lowband/highband switch point
+    // Lowband/highband switch point
     static const double LB_HB_THRESHOLD_FREQ    = 1.8e9;
     static const double LB_TARGET_IF1_FREQ      = 2.345e9;
     static const double HB_TARGET_IF1_FREQ      = 1.25e9;
     static const double INJ_SIDE_THRESHOLD_FREQ = 5.1e9;
 
-    static const double FIXED_LO1_THRESHOLD_FREQ= 50e6;
+    static const double FIXED_LO1_THRESHOLD_FREQ = 50e6;
 
-    //Preselector filter switch point
+    // Preselector filter switch point
     static const double LB_FILT1_THRESHOLD_FREQ = 0.5e9;
     static const double LB_FILT2_THRESHOLD_FREQ = 0.8e9;
     static const double LB_FILT3_THRESHOLD_FREQ = 1.2e9;
@@ -57,7 +56,7 @@ void twinrx_freq_path_expert::resolve()
 
     static const double LB_PREAMP_PRESEL_THRESHOLD_FREQ = 0.8e9;
 
-    //Misc
+    // Misc
     static const double INST_BANDWIDTH           = 80e6;
     static const double MANUAL_LO_HYSTERESIS_PPM = 1.0;
 
@@ -65,8 +64,8 @@ void twinrx_freq_path_expert::resolve()
     rf_freq_abs_t rf_freq(FREQ_RANGE.clip(_rf_freq_d));
 
     // Choose low-band vs high-band depending on frequency
-    _signal_path = (rf_freq > LB_HB_THRESHOLD_FREQ) ?
-        twinrx_ctrl::PATH_HIGHBAND : twinrx_ctrl::PATH_LOWBAND;
+    _signal_path = (rf_freq > LB_HB_THRESHOLD_FREQ) ? twinrx_ctrl::PATH_HIGHBAND
+                                                    : twinrx_ctrl::PATH_LOWBAND;
     if (_signal_path == twinrx_ctrl::PATH_LOWBAND) {
         // Choose low-band preselector filter
         if (rf_freq < LB_FILT1_THRESHOLD_FREQ) {
@@ -97,41 +96,43 @@ void twinrx_freq_path_expert::resolve()
         UHD_THROW_INVALID_CODE_PATH();
     }
 
-    //Choose low-band preamp preselector
+    // Choose low-band preamp preselector
     _lb_preamp_presel = (rf_freq > LB_PREAMP_PRESEL_THRESHOLD_FREQ);
 
-    //Choose LO frequencies
-    const double target_if1_freq = (_signal_path == twinrx_ctrl::PATH_HIGHBAND) ?
-        HB_TARGET_IF1_FREQ : LB_TARGET_IF1_FREQ;
+    // Choose LO frequencies
+    const double target_if1_freq = (_signal_path == twinrx_ctrl::PATH_HIGHBAND)
+                                       ? HB_TARGET_IF1_FREQ
+                                       : LB_TARGET_IF1_FREQ;
     const double target_if2_freq = _if_freq_d;
 
     // LO1
     double lo1_freq_ideal = 0.0, lo2_freq_ideal = 0.0;
     if (rf_freq <= FIXED_LO1_THRESHOLD_FREQ) {
-        //LO1 Freq static
+        // LO1 Freq static
         lo1_freq_ideal = target_if1_freq + FIXED_LO1_THRESHOLD_FREQ;
     } else if (rf_freq <= INJ_SIDE_THRESHOLD_FREQ) {
-        //High-side LO1 Injection
+        // High-side LO1 Injection
         lo1_freq_ideal = rf_freq.get() + target_if1_freq;
     } else {
-        //Low-side LO1 Injection
+        // Low-side LO1 Injection
         lo1_freq_ideal = rf_freq.get() - target_if1_freq;
     }
 
     if (_lo1_freq_d.get_author() == experts::AUTHOR_USER) {
-        if (_lo1_freq_d.is_dirty()) { //Are we here because the LO frequency was set?
+        if (_lo1_freq_d.is_dirty()) { // Are we here because the LO frequency was set?
             // The user explicitly requested to set the LO freq so don't touch it!
         } else {
             // Something else changed which may cause the LO frequency to update.
             // Only commit if the frequency is stale. If the user's value is stale
             // reset the author to expert.
-            if (rf_freq_ppm_t(lo1_freq_ideal, MANUAL_LO_HYSTERESIS_PPM) != _lo1_freq_d.get()) {
-                _lo1_freq_d = lo1_freq_ideal;    //Reset author
+            if (rf_freq_ppm_t(lo1_freq_ideal, MANUAL_LO_HYSTERESIS_PPM)
+                != _lo1_freq_d.get()) {
+                _lo1_freq_d = lo1_freq_ideal; // Reset author
             }
         }
     } else {
         // The LO frequency was never set by the user. Let the expert take care of it
-        _lo1_freq_d = lo1_freq_ideal;    //Reset author
+        _lo1_freq_d = lo1_freq_ideal; // Reset author
     }
 
     // LO2
@@ -144,37 +145,40 @@ void twinrx_freq_path_expert::resolve()
     }
 
     if (_lo2_freq_d.get_author() == experts::AUTHOR_USER) {
-        if (_lo2_freq_d.is_dirty()) { //Are we here because the LO frequency was set?
+        if (_lo2_freq_d.is_dirty()) { // Are we here because the LO frequency was set?
             // The user explicitly requested to set the LO freq so don't touch it!
         } else {
             // Something else changed which may cause the LO frequency to update.
             // Only commit if the frequency is stale. If the user's value is stale
             // reset the author to expert.
-            if (rf_freq_ppm_t(lo2_freq_ideal, MANUAL_LO_HYSTERESIS_PPM) != _lo2_freq_d.get()) {
-                _lo2_freq_d = lo2_freq_ideal;    //Reset author
+            if (rf_freq_ppm_t(lo2_freq_ideal, MANUAL_LO_HYSTERESIS_PPM)
+                != _lo2_freq_d.get()) {
+                _lo2_freq_d = lo2_freq_ideal; // Reset author
             }
         }
     } else {
         // The LO frequency was never set by the user. Let the expert take care of it
-        _lo2_freq_d = lo2_freq_ideal;    //Reset author
+        _lo2_freq_d = lo2_freq_ideal; // Reset author
     }
 
     // Determine injection side using the final LO frequency
-    _lo1_inj_side = (_lo1_freq_d > rf_freq.get())   ? INJ_HIGH_SIDE : INJ_LOW_SIDE;
+    _lo1_inj_side = (_lo1_freq_d > rf_freq.get()) ? INJ_HIGH_SIDE : INJ_LOW_SIDE;
     _lo2_inj_side = (_lo2_freq_d > target_if1_freq) ? INJ_HIGH_SIDE : INJ_LOW_SIDE;
 }
 
 lo_inj_side_t twinrx_freq_path_expert::_compute_lo2_inj_side(
-    double lo1_freq, double if1_freq,  double if2_freq, double bandwidth
-) {
+    double lo1_freq, double if1_freq, double if2_freq, double bandwidth)
+{
     static const int MAX_SPUR_ORDER = 5;
     for (int ord = MAX_SPUR_ORDER; ord >= 1; ord--) {
         // Check high-side injection first
-        if (not _has_mixer_spurs(lo1_freq, if1_freq + if2_freq, if2_freq, bandwidth, ord)) {
+        if (not _has_mixer_spurs(
+                lo1_freq, if1_freq + if2_freq, if2_freq, bandwidth, ord)) {
             return INJ_HIGH_SIDE;
         }
         // Check low-side injection second
-        if (not _has_mixer_spurs(lo1_freq, if1_freq - if2_freq, if2_freq, bandwidth, ord)) {
+        if (not _has_mixer_spurs(
+                lo1_freq, if1_freq - if2_freq, if2_freq, bandwidth, ord)) {
             return INJ_LOW_SIDE;
         }
     }
@@ -183,19 +187,18 @@ lo_inj_side_t twinrx_freq_path_expert::_compute_lo2_inj_side(
 }
 
 bool twinrx_freq_path_expert::_has_mixer_spurs(
-    double lo1_freq, double lo2_freq, double if2_freq,
-    double bandwidth, int spur_order
-) {
+    double lo1_freq, double lo2_freq, double if2_freq, double bandwidth, int spur_order)
+{
     // Iterate through all N-th order harmomic combinations
     // of LOs...
     for (int lo1h_i = 1; lo1h_i <= spur_order; lo1h_i++) {
         double lo1harm_freq = lo1_freq * lo1h_i;
         for (int lo2h_i = 1; lo2h_i <= spur_order; lo2h_i++) {
             double lo2harm_freq = lo2_freq * lo2h_i;
-            double hdelta = lo1harm_freq - lo2harm_freq;
+            double hdelta       = lo1harm_freq - lo2harm_freq;
             // .. and check if there is a mixer spur in the IF band
-            if (std::abs(hdelta + if2_freq) < bandwidth/2 or
-                std::abs(hdelta - if2_freq) < bandwidth/2) {
+            if (std::abs(hdelta + if2_freq) < bandwidth / 2
+                or std::abs(hdelta - if2_freq) < bandwidth / 2) {
                 return true;
             }
         }
@@ -211,11 +214,12 @@ bool twinrx_freq_path_expert::_has_mixer_spurs(
 void twinrx_freq_coercion_expert::resolve()
 {
     const double actual_if2_freq = _if_freq_d;
-    const double actual_if1_freq = (_lo2_inj_side == INJ_LOW_SIDE) ?
-        (_lo2_freq_c + actual_if2_freq) : (_lo2_freq_c - actual_if2_freq);
+    const double actual_if1_freq = (_lo2_inj_side == INJ_LOW_SIDE)
+                                       ? (_lo2_freq_c + actual_if2_freq)
+                                       : (_lo2_freq_c - actual_if2_freq);
 
-    _rf_freq_c = (_lo1_inj_side == INJ_LOW_SIDE) ?
-        (_lo1_freq_c + actual_if1_freq) : (_lo1_freq_c - actual_if1_freq);
+    _rf_freq_c = (_lo1_inj_side == INJ_LOW_SIDE) ? (_lo1_freq_c + actual_if1_freq)
+                                                 : (_lo1_freq_c - actual_if1_freq);
 }
 
 /*!---------------------------------------------------------
@@ -238,12 +242,14 @@ void twinrx_nyquist_expert::resolve()
     _cached_cmd_time = _rx_frontend_time;
 
     double if_freq_sign = 1.0;
-    if (_lo1_inj_side == INJ_HIGH_SIDE) if_freq_sign *= -1.0;
-    if (_lo2_inj_side == INJ_HIGH_SIDE) if_freq_sign *= -1.0;
+    if (_lo1_inj_side == INJ_HIGH_SIDE)
+        if_freq_sign *= -1.0;
+    if (_lo2_inj_side == INJ_HIGH_SIDE)
+        if_freq_sign *= -1.0;
     _if_freq_c = _if_freq_d * if_freq_sign;
 
-    _db_iface->set_fe_connection(dboard_iface::UNIT_RX, _channel,
-        usrp::fe_connection_t(_codec_conn, _if_freq_c));
+    _db_iface->set_fe_connection(
+        dboard_iface::UNIT_RX, _channel, usrp::fe_connection_t(_codec_conn, _if_freq_c));
 }
 
 /*!---------------------------------------------------------
@@ -253,22 +259,22 @@ void twinrx_nyquist_expert::resolve()
 void twinrx_chan_gain_expert::resolve()
 {
     if (_gain_profile != "default") {
-        //TODO: Implement me!
+        // TODO: Implement me!
         throw uhd::not_implemented_error("custom gain strategies not implemeted yet");
     }
 
-    //Lookup table using settings
-    const twinrx_gain_table table = twinrx_gain_table::lookup_table(
-        _signal_path,
-        (_signal_path==twinrx_ctrl::PATH_HIGHBAND) ? _hb_presel : _lb_presel,
+    // Lookup table using settings
+    const twinrx_gain_table table = twinrx_gain_table::lookup_table(_signal_path,
+        (_signal_path == twinrx_ctrl::PATH_HIGHBAND) ? _hb_presel : _lb_presel,
         _gain_profile);
 
-    //Compute minimum gain. The user-specified gain value will be interpreted as
-    //the gain applied on top of the minimum gain state.
-    //If antennas are shared or swapped, the switch has 6dB of loss
-    size_t gain_index = std::min(static_cast<size_t>(boost::math::round(_gain.get())), table.get_num_entries()-1);
+    // Compute minimum gain. The user-specified gain value will be interpreted as
+    // the gain applied on top of the minimum gain state.
+    // If antennas are shared or swapped, the switch has 6dB of loss
+    size_t gain_index = std::min(static_cast<size_t>(boost::math::round(_gain.get())),
+        table.get_num_entries() - 1);
 
-    //Translate gain to an index in the gain table
+    // Translate gain to an index in the gain table
     const twinrx_gain_config_t& config = table.find_by_index(gain_index);
 
     _input_atten = config.atten1;
@@ -279,8 +285,10 @@ void twinrx_chan_gain_expert::resolve()
     }
 
     // Preamp 1 should use the Highband amp for frequencies above 3 GHz
-    if (_signal_path == twinrx_ctrl::PATH_HIGHBAND && _hb_presel != twinrx_ctrl::PRESEL_PATH1) {
-        _preamp1 = config.amp1 ? twinrx_ctrl::PREAMP_HIGHBAND : twinrx_ctrl::PREAMP_BYPASS;
+    if (_signal_path == twinrx_ctrl::PATH_HIGHBAND
+        && _hb_presel != twinrx_ctrl::PRESEL_PATH1) {
+        _preamp1 = config.amp1 ? twinrx_ctrl::PREAMP_HIGHBAND
+                               : twinrx_ctrl::PREAMP_BYPASS;
     } else {
         _preamp1 = config.amp1 ? twinrx_ctrl::PREAMP_LOWBAND : twinrx_ctrl::PREAMP_BYPASS;
     }
@@ -295,22 +303,21 @@ void twinrx_chan_gain_expert::resolve()
 void twinrx_lo_config_expert::resolve()
 {
     static const uhd::dict<std::string, twinrx_ctrl::lo_source_t> src_lookup =
-        boost::assign::map_list_of
-        ("internal",  twinrx_ctrl::LO_INTERNAL)
-        ("external",  twinrx_ctrl::LO_EXTERNAL)
-        ("companion", twinrx_ctrl::LO_COMPANION)
-        ("disabled",  twinrx_ctrl::LO_DISABLED)
-        ("reimport",  twinrx_ctrl::LO_REIMPORT);
+        boost::assign::map_list_of("internal", twinrx_ctrl::LO_INTERNAL)(
+            "external", twinrx_ctrl::LO_EXTERNAL)("companion", twinrx_ctrl::LO_COMPANION)(
+            "disabled", twinrx_ctrl::LO_DISABLED)("reimport", twinrx_ctrl::LO_REIMPORT);
 
     if (src_lookup.has_key(_lo_source_ch0)) {
         _lo1_src_ch0 = _lo2_src_ch0 = src_lookup[_lo_source_ch0];
     } else {
-        throw uhd::value_error("Invalid LO source for channel 0.Choose from {internal, external, companion, reimport}");
+        throw uhd::value_error("Invalid LO source for channel 0.Choose from {internal, "
+                               "external, companion, reimport}");
     }
     if (src_lookup.has_key(_lo_source_ch1)) {
         _lo1_src_ch1 = _lo2_src_ch1 = src_lookup[_lo_source_ch1];
     } else {
-        throw uhd::value_error("Invalid LO source for channel 1.Choose from {internal, external, companion, reimport}");
+        throw uhd::value_error("Invalid LO source for channel 1.Choose from {internal, "
+                               "external, companion, reimport}");
     }
 
     twinrx_ctrl::lo_export_source_t export_src = twinrx_ctrl::LO_EXPORT_DISABLED;
@@ -325,11 +332,13 @@ void twinrx_lo_config_expert::resolve()
     if (_lo_export_ch0 and _lo_export_ch1) {
         throw uhd::value_error("Cannot export LOs for both channels");
     } else if (_lo_export_ch0) {
-        export_src = (_lo1_src_ch0 == twinrx_ctrl::LO_COMPANION) ?
-            twinrx_ctrl::LO_CH2_SYNTH : twinrx_ctrl::LO_CH1_SYNTH;
+        export_src = (_lo1_src_ch0 == twinrx_ctrl::LO_COMPANION)
+                         ? twinrx_ctrl::LO_CH2_SYNTH
+                         : twinrx_ctrl::LO_CH1_SYNTH;
     } else if (_lo_export_ch1) {
-        export_src = (_lo1_src_ch1 == twinrx_ctrl::LO_COMPANION) ?
-            twinrx_ctrl::LO_CH1_SYNTH : twinrx_ctrl::LO_CH2_SYNTH;
+        export_src = (_lo1_src_ch1 == twinrx_ctrl::LO_COMPANION)
+                         ? twinrx_ctrl::LO_CH1_SYNTH
+                         : twinrx_ctrl::LO_CH2_SYNTH;
     }
     _lo1_export_src = _lo2_export_src = export_src;
 }
@@ -348,12 +357,14 @@ void twinrx_lo_mapping_expert::resolve()
     // "internal" or "reimport" -> this channel
     // "companion" -> other channel
     size_t synth_map[] = {0, 0};
-    if (_lox_src_ch0 == twinrx_ctrl::LO_INTERNAL or _lox_src_ch0 == twinrx_ctrl::LO_REIMPORT) {
+    if (_lox_src_ch0 == twinrx_ctrl::LO_INTERNAL
+        or _lox_src_ch0 == twinrx_ctrl::LO_REIMPORT) {
         synth_map[0] = synth_map[0] | CH0_MSK;
     } else if (_lox_src_ch0 == twinrx_ctrl::LO_COMPANION) {
         synth_map[1] = synth_map[1] | CH0_MSK;
     }
-    if (_lox_src_ch1 == twinrx_ctrl::LO_INTERNAL or _lox_src_ch1 == twinrx_ctrl::LO_REIMPORT) {
+    if (_lox_src_ch1 == twinrx_ctrl::LO_INTERNAL
+        or _lox_src_ch1 == twinrx_ctrl::LO_REIMPORT) {
         synth_map[1] = synth_map[1] | CH1_MSK;
     } else if (_lox_src_ch1 == twinrx_ctrl::LO_COMPANION) {
         synth_map[0] = synth_map[0] | CH1_MSK;
@@ -365,20 +376,22 @@ void twinrx_lo_mapping_expert::resolve()
     // to overlap tuning with signal dwell time.
     bool hopping_enabled = false;
     if (_lox_src_ch0 == twinrx_ctrl::LO_DISABLED) {
-        if (_lox_src_ch1 == twinrx_ctrl::LO_INTERNAL or _lox_src_ch1 == twinrx_ctrl::LO_REIMPORT) {
-            synth_map[0] = synth_map[0] | CH0_MSK;
+        if (_lox_src_ch1 == twinrx_ctrl::LO_INTERNAL
+            or _lox_src_ch1 == twinrx_ctrl::LO_REIMPORT) {
+            synth_map[0]    = synth_map[0] | CH0_MSK;
             hopping_enabled = true;
         } else if (_lox_src_ch1 == twinrx_ctrl::LO_COMPANION) {
-            synth_map[1] = synth_map[1] | CH0_MSK;
+            synth_map[1]    = synth_map[1] | CH0_MSK;
             hopping_enabled = true;
         }
     }
     if (_lox_src_ch1 == twinrx_ctrl::LO_DISABLED) {
-        if (_lox_src_ch0 == twinrx_ctrl::LO_INTERNAL or _lox_src_ch0 == twinrx_ctrl::LO_REIMPORT) {
-            synth_map[1] = synth_map[1] | CH1_MSK;
+        if (_lox_src_ch0 == twinrx_ctrl::LO_INTERNAL
+            or _lox_src_ch0 == twinrx_ctrl::LO_REIMPORT) {
+            synth_map[1]    = synth_map[1] | CH1_MSK;
             hopping_enabled = true;
         } else if (_lox_src_ch0 == twinrx_ctrl::LO_COMPANION) {
-            synth_map[0] = synth_map[0] | CH1_MSK;
+            synth_map[0]    = synth_map[0] | CH1_MSK;
             hopping_enabled = true;
         }
     }
@@ -387,7 +400,7 @@ void twinrx_lo_mapping_expert::resolve()
     for (size_t synth = 0; synth < 2; synth++) {
         experts::data_writer_t<lo_synth_mapping_t>& lox_mapping =
             (synth == 0) ? _lox_mapping_synth0 : _lox_mapping_synth1;
-        if (synth_map[synth] == (CH0_MSK|CH1_MSK)) {
+        if (synth_map[synth] == (CH0_MSK | CH1_MSK)) {
             lox_mapping = MAPPING_SHARED;
         } else if (synth_map[synth] == CH0_MSK) {
             lox_mapping = MAPPING_CH0;
@@ -429,18 +442,22 @@ void twinrx_antenna_expert::resolve()
     } else if (_antenna_ch0 == ANT1 and _antenna_ch1 == ANT0) {
         _ant_mapping = twinrx_ctrl::ANTX_SWAPPED;
     } else if (_antenna_ch0 != ANT0 and _antenna_ch0 != ANT1) {
-        throw uhd::value_error("Invalid antenna selection " + _antenna_ch0.get() + " for channel 0. Must be " + ANT0 + " or " + ANT1);
+        throw uhd::value_error("Invalid antenna selection " + _antenna_ch0.get()
+                               + " for channel 0. Must be " + ANT0 + " or " + ANT1);
     } else if (_antenna_ch1 != ANT0 and _antenna_ch1 != ANT1) {
-        throw uhd::value_error("Invalid antenna selection " + _antenna_ch1.get() + " for channel 1. Must be " + ANT0 + " or " + ANT1);
+        throw uhd::value_error("Invalid antenna selection " + _antenna_ch1.get()
+                               + " for channel 1. Must be " + ANT0 + " or " + ANT1);
     }
 
-    //TODO: Implement hooks for the calibration switch
+    // TODO: Implement hooks for the calibration switch
     _cal_mode = twinrx_ctrl::CAL_DISABLED;
 
     if (_cal_mode == twinrx_ctrl::CAL_CH1 and _lo_export_ch1) {
-        throw uhd::value_error("Cannot calibrate channel 0 and export the LO for channel 1.");
+        throw uhd::value_error(
+            "Cannot calibrate channel 0 and export the LO for channel 1.");
     } else if (_cal_mode == twinrx_ctrl::CAL_CH2 and _lo_export_ch0) {
-        throw uhd::value_error("Cannot calibrate channel 1 and export the LO for channel 0.");
+        throw uhd::value_error(
+            "Cannot calibrate channel 1 and export the LO for channel 0.");
     }
 }
 
@@ -451,72 +468,72 @@ void twinrx_antenna_expert::resolve()
 void twinrx_ant_gain_expert::resolve()
 {
     switch (_ant_mapping) {
-    case twinrx_ctrl::ANTX_NATIVE:
-        _ant0_input_atten       = _ch0_input_atten;
-        _ant0_preamp1           = _ch0_preamp1;
-        _ant0_preamp2           = _ch0_preamp2;
-        _ant0_lb_preamp_presel  = _ch0_lb_preamp_presel;
-        _ant1_input_atten       = _ch1_input_atten;
-        _ant1_preamp1           = _ch1_preamp1;
-        _ant1_preamp2           = _ch1_preamp2;
-        _ant1_lb_preamp_presel  = _ch1_lb_preamp_presel;
-        break;
-    case twinrx_ctrl::ANTX_SWAPPED:
-        _ant0_input_atten       = _ch1_input_atten;
-        _ant0_preamp1           = _ch1_preamp1;
-        _ant0_preamp2           = _ch1_preamp2;
-        _ant0_lb_preamp_presel  = _ch1_lb_preamp_presel;
-        _ant1_input_atten       = _ch0_input_atten;
-        _ant1_preamp1           = _ch0_preamp1;
-        _ant1_preamp2           = _ch0_preamp2;
-        _ant1_lb_preamp_presel  = _ch0_lb_preamp_presel;
-        break;
-    case twinrx_ctrl::ANT1_SHARED:
-        if ((_ch0_input_atten != _ch1_input_atten) or
-            (_ch0_preamp1 != _ch1_preamp1) or
-            (_ch0_preamp2 != _ch1_preamp2) or
-            (_ch0_lb_preamp_presel != _ch1_lb_preamp_presel))
-        {
-            UHD_LOGGER_WARNING("TWINRX") << "incompatible gain settings for antenna sharing. temporarily using Ch0 settings for Ch1.";
-        }
-        _ant0_input_atten       = _ch0_input_atten;
-        _ant0_preamp1           = _ch0_preamp1;
-        _ant0_preamp2           = _ch0_preamp2;
-        _ant0_lb_preamp_presel  = _ch0_lb_preamp_presel;
-
-        _ant1_input_atten       = 0;
-        _ant1_preamp1           = twinrx_ctrl::PREAMP_BYPASS;
-        _ant1_preamp2           = false;
-        _ant1_lb_preamp_presel  = false;
-        break;
-    case twinrx_ctrl::ANT2_SHARED:
-        if ((_ch0_input_atten != _ch1_input_atten) or
-            (_ch0_preamp1 != _ch1_preamp1) or
-            (_ch0_preamp2 != _ch1_preamp2) or
-            (_ch0_lb_preamp_presel != _ch1_lb_preamp_presel))
-        {
-            UHD_LOGGER_WARNING("TWINRX") << "incompatible gain settings for antenna sharing. temporarily using Ch0 settings for Ch1.";
-        }
-        _ant1_input_atten       = _ch0_input_atten;
-        _ant1_preamp1           = _ch0_preamp1;
-        _ant1_preamp2           = _ch0_preamp2;
-        _ant1_lb_preamp_presel  = _ch0_lb_preamp_presel;
-
-        _ant0_input_atten       = 0;
-        _ant0_preamp1           = twinrx_ctrl::PREAMP_BYPASS;
-        _ant0_preamp2           = false;
-        _ant0_lb_preamp_presel  = false;
-        break;
-    default:
-        _ant0_input_atten       = 0;
-        _ant0_preamp1           = twinrx_ctrl::PREAMP_BYPASS;
-        _ant0_preamp2           = false;
-        _ant0_lb_preamp_presel  = false;
-        _ant1_input_atten       = 0;
-        _ant1_preamp1           = twinrx_ctrl::PREAMP_BYPASS;
-        _ant1_preamp2           = false;
-        _ant1_lb_preamp_presel  = false;
-        break;
+        case twinrx_ctrl::ANTX_NATIVE:
+            _ant0_input_atten      = _ch0_input_atten;
+            _ant0_preamp1          = _ch0_preamp1;
+            _ant0_preamp2          = _ch0_preamp2;
+            _ant0_lb_preamp_presel = _ch0_lb_preamp_presel;
+            _ant1_input_atten      = _ch1_input_atten;
+            _ant1_preamp1          = _ch1_preamp1;
+            _ant1_preamp2          = _ch1_preamp2;
+            _ant1_lb_preamp_presel = _ch1_lb_preamp_presel;
+            break;
+        case twinrx_ctrl::ANTX_SWAPPED:
+            _ant0_input_atten      = _ch1_input_atten;
+            _ant0_preamp1          = _ch1_preamp1;
+            _ant0_preamp2          = _ch1_preamp2;
+            _ant0_lb_preamp_presel = _ch1_lb_preamp_presel;
+            _ant1_input_atten      = _ch0_input_atten;
+            _ant1_preamp1          = _ch0_preamp1;
+            _ant1_preamp2          = _ch0_preamp2;
+            _ant1_lb_preamp_presel = _ch0_lb_preamp_presel;
+            break;
+        case twinrx_ctrl::ANT1_SHARED:
+            if ((_ch0_input_atten != _ch1_input_atten) or (_ch0_preamp1 != _ch1_preamp1)
+                or (_ch0_preamp2 != _ch1_preamp2)
+                or (_ch0_lb_preamp_presel != _ch1_lb_preamp_presel)) {
+                UHD_LOGGER_WARNING("TWINRX")
+                    << "incompatible gain settings for antenna sharing. temporarily "
+                       "using Ch0 settings for Ch1.";
+            }
+            _ant0_input_atten      = _ch0_input_atten;
+            _ant0_preamp1          = _ch0_preamp1;
+            _ant0_preamp2          = _ch0_preamp2;
+            _ant0_lb_preamp_presel = _ch0_lb_preamp_presel;
+
+            _ant1_input_atten      = 0;
+            _ant1_preamp1          = twinrx_ctrl::PREAMP_BYPASS;
+            _ant1_preamp2          = false;
+            _ant1_lb_preamp_presel = false;
+            break;
+        case twinrx_ctrl::ANT2_SHARED:
+            if ((_ch0_input_atten != _ch1_input_atten) or (_ch0_preamp1 != _ch1_preamp1)
+                or (_ch0_preamp2 != _ch1_preamp2)
+                or (_ch0_lb_preamp_presel != _ch1_lb_preamp_presel)) {
+                UHD_LOGGER_WARNING("TWINRX")
+                    << "incompatible gain settings for antenna sharing. temporarily "
+                       "using Ch0 settings for Ch1.";
+            }
+            _ant1_input_atten      = _ch0_input_atten;
+            _ant1_preamp1          = _ch0_preamp1;
+            _ant1_preamp2          = _ch0_preamp2;
+            _ant1_lb_preamp_presel = _ch0_lb_preamp_presel;
+
+            _ant0_input_atten      = 0;
+            _ant0_preamp1          = twinrx_ctrl::PREAMP_BYPASS;
+            _ant0_preamp2          = false;
+            _ant0_lb_preamp_presel = false;
+            break;
+        default:
+            _ant0_input_atten      = 0;
+            _ant0_preamp1          = twinrx_ctrl::PREAMP_BYPASS;
+            _ant0_preamp2          = false;
+            _ant0_lb_preamp_presel = false;
+            _ant1_input_atten      = 0;
+            _ant1_preamp1          = twinrx_ctrl::PREAMP_BYPASS;
+            _ant1_preamp2          = false;
+            _ant1_lb_preamp_presel = false;
+            break;
     }
 }
 
@@ -529,7 +546,7 @@ const bool twinrx_settings_expert::FORCE_COMMIT = false;
 void twinrx_settings_expert::resolve()
 {
     for (size_t i = 0; i < 2; i++) {
-        ch_settings& ch_set = (i == 1) ? _ch1 : _ch0;
+        ch_settings& ch_set       = (i == 1) ? _ch1 : _ch0;
         twinrx_ctrl::channel_t ch = (i == 1) ? twinrx_ctrl::CH2 : twinrx_ctrl::CH1;
         _ctrl->set_chan_enabled(ch, ch_set.chan_enabled, FORCE_COMMIT);
         _ctrl->set_preamp1(ch, ch_set.preamp1, FORCE_COMMIT);
@@ -550,34 +567,45 @@ void twinrx_settings_expert::resolve()
     }
 
     _resolve_lox_freq(STAGE_LO1,
-        _ch0.lo1_freq_d, _ch1.lo1_freq_d, _ch0.lo1_freq_c, _ch1.lo1_freq_c,
-        _ch0.lo1_source, _ch1.lo1_source, _lo1_synth0_mapping, _lo1_synth1_mapping,
+        _ch0.lo1_freq_d,
+        _ch1.lo1_freq_d,
+        _ch0.lo1_freq_c,
+        _ch1.lo1_freq_c,
+        _ch0.lo1_source,
+        _ch1.lo1_source,
+        _lo1_synth0_mapping,
+        _lo1_synth1_mapping,
         _lo1_hopping_enabled);
     _resolve_lox_freq(STAGE_LO2,
-        _ch0.lo2_freq_d, _ch1.lo2_freq_d, _ch0.lo2_freq_c, _ch1.lo2_freq_c,
-        _ch0.lo2_source, _ch1.lo2_source, _lo2_synth0_mapping, _lo2_synth1_mapping,
+        _ch0.lo2_freq_d,
+        _ch1.lo2_freq_d,
+        _ch0.lo2_freq_c,
+        _ch1.lo2_freq_c,
+        _ch0.lo2_source,
+        _ch1.lo2_source,
+        _lo2_synth0_mapping,
+        _lo2_synth1_mapping,
         _lo2_hopping_enabled);
 
     _ctrl->set_lo1_export_source(_lo1_export_src, FORCE_COMMIT);
     _ctrl->set_lo2_export_source(_lo2_export_src, FORCE_COMMIT);
     _ctrl->set_antenna_mapping(_ant_mapping, FORCE_COMMIT);
-    //TODO: Re-enable this when we support this mode
+    // TODO: Re-enable this when we support this mode
     //_ctrl->set_crossover_cal_mode(_cal_mode, FORCE_COMMIT);
 
     _ctrl->commit();
 }
 
-void twinrx_settings_expert::_resolve_lox_freq(
-    lo_stage_t                           lo_stage,
+void twinrx_settings_expert::_resolve_lox_freq(lo_stage_t lo_stage,
     uhd::experts::data_reader_t<double>& ch0_freq_d,
     uhd::experts::data_reader_t<double>& ch1_freq_d,
     uhd::experts::data_writer_t<double>& ch0_freq_c,
     uhd::experts::data_writer_t<double>& ch1_freq_c,
-    twinrx_ctrl::lo_source_t             ch0_lo_source,
-    twinrx_ctrl::lo_source_t             ch1_lo_source,
-    lo_synth_mapping_t                   synth0_mapping,
-    lo_synth_mapping_t                   synth1_mapping,
-    bool                                 hopping_enabled)
+    twinrx_ctrl::lo_source_t ch0_lo_source,
+    twinrx_ctrl::lo_source_t ch1_lo_source,
+    lo_synth_mapping_t synth0_mapping,
+    lo_synth_mapping_t synth1_mapping,
+    bool hopping_enabled)
 {
     if (ch0_lo_source == twinrx_ctrl::LO_EXTERNAL) {
         // If the LO is external then we don't need to program any synthesizers
@@ -594,7 +622,8 @@ void twinrx_settings_expert::_resolve_lox_freq(
             ch0_freq_c = _set_lox_synth_freq(lo_stage, twinrx_ctrl::CH2, ch0_freq_d);
         } else if (synth0_mapping == MAPPING_SHARED or synth1_mapping == MAPPING_SHARED) {
             // If any synthesizer is being shared then we are not in hopping mode
-            twinrx_ctrl::channel_t ch = (synth0_mapping == MAPPING_SHARED) ? twinrx_ctrl::CH1 : twinrx_ctrl::CH2;
+            twinrx_ctrl::channel_t ch =
+                (synth0_mapping == MAPPING_SHARED) ? twinrx_ctrl::CH1 : twinrx_ctrl::CH2;
             ch0_freq_c = _set_lox_synth_freq(lo_stage, ch, ch0_freq_d);
             ch1_freq_c = ch0_freq_c;
         }
@@ -609,28 +638,32 @@ void twinrx_settings_expert::_resolve_lox_freq(
         // hopping, then always write the frequency because other inputs might require
         // an LO re-commit
         const bool freq_update_request = (not hopping_enabled) or ch1_freq_d.is_dirty();
-        // As an additional layer of protection from unnecessarily committing the LO, check
-        // if the frequency has actually changed.
+        // As an additional layer of protection from unnecessarily committing the LO,
+        // check if the frequency has actually changed.
         if (synth0_mapping == MAPPING_CH1 and freq_update_request) {
             ch1_freq_c = _set_lox_synth_freq(lo_stage, twinrx_ctrl::CH1, ch1_freq_d);
         } else if (synth1_mapping == MAPPING_CH1 and freq_update_request) {
             ch1_freq_c = _set_lox_synth_freq(lo_stage, twinrx_ctrl::CH2, ch1_freq_d);
         } else if (synth0_mapping == MAPPING_SHARED or synth1_mapping == MAPPING_SHARED) {
             // If any synthesizer is being shared then we are not in hopping mode
-            twinrx_ctrl::channel_t ch = (synth0_mapping == MAPPING_SHARED) ? twinrx_ctrl::CH1 : twinrx_ctrl::CH2;
+            twinrx_ctrl::channel_t ch =
+                (synth0_mapping == MAPPING_SHARED) ? twinrx_ctrl::CH1 : twinrx_ctrl::CH2;
             ch0_freq_c = _set_lox_synth_freq(lo_stage, ch, ch0_freq_d);
             ch1_freq_c = ch0_freq_c;
         }
     }
 }
 
-double twinrx_settings_expert::_set_lox_synth_freq(lo_stage_t stage, twinrx_ctrl::channel_t ch, double freq)
+double twinrx_settings_expert::_set_lox_synth_freq(
+    lo_stage_t stage, twinrx_ctrl::channel_t ch, double freq)
 {
     lo_freq_cache_t* freq_cache = NULL;
     if (stage == STAGE_LO1) {
-        freq_cache = (ch == twinrx_ctrl::CH1) ? &_cached_lo1_synth0_freq : &_cached_lo1_synth1_freq;
+        freq_cache = (ch == twinrx_ctrl::CH1) ? &_cached_lo1_synth0_freq
+                                              : &_cached_lo1_synth1_freq;
     } else if (stage == STAGE_LO2) {
-        freq_cache = (ch == twinrx_ctrl::CH1) ? &_cached_lo2_synth0_freq : &_cached_lo2_synth1_freq;
+        freq_cache = (ch == twinrx_ctrl::CH1) ? &_cached_lo2_synth0_freq
+                                              : &_cached_lo2_synth1_freq;
     } else {
         throw uhd::assertion_error("Invalid LO stage");
     }
@@ -650,4 +683,3 @@ double twinrx_settings_expert::_set_lox_synth_freq(lo_stage_t stage, twinrx_ctrl
     }
     return coerced_freq;
 }
-
diff --git a/host/lib/usrp/dboard/twinrx/twinrx_experts.hpp b/host/lib/usrp/dboard/twinrx/twinrx_experts.hpp
index 16569849c..c7e021a90 100644
--- a/host/lib/usrp/dboard/twinrx/twinrx_experts.hpp
+++ b/host/lib/usrp/dboard/twinrx/twinrx_experts.hpp
@@ -9,8 +9,8 @@
 #define INCLUDED_DBOARD_TWINRX_EXPERTS_HPP
 
 #include "twinrx_ctrl.hpp"
-#include <uhdlib/experts/expert_nodes.hpp>
 #include <uhd/utils/math.hpp>
+#include <uhdlib/experts/expert_nodes.hpp>
 
 namespace uhd { namespace usrp { namespace dboard { namespace twinrx {
 
@@ -18,26 +18,37 @@ namespace uhd { namespace usrp { namespace dboard { namespace twinrx {
 // Misc types and definitions
 //---------------------------------------------------------
 
-struct rf_freq_abs_t : public uhd::math::fp_compare::fp_compare_delta<double> {
-    rf_freq_abs_t(double freq = 0.0, double epsilon = 1.0 /* 1Hz epsilon */) :
-        uhd::math::fp_compare::fp_compare_delta<double>(freq, epsilon) {}
-    inline double get() const { return _value; }
+struct rf_freq_abs_t : public uhd::math::fp_compare::fp_compare_delta<double>
+{
+    rf_freq_abs_t(double freq = 0.0, double epsilon = 1.0 /* 1Hz epsilon */)
+        : uhd::math::fp_compare::fp_compare_delta<double>(freq, epsilon)
+    {
+    }
+    inline double get() const
+    {
+        return _value;
+    }
 };
 
-struct rf_freq_ppm_t : public rf_freq_abs_t {
-    rf_freq_ppm_t(double freq = 0.0, double epsilon_ppm = 0.1  /* 1PPM epsilon */) :
-        rf_freq_abs_t(freq, 1e-6 * freq * epsilon_ppm) {}
+struct rf_freq_ppm_t : public rf_freq_abs_t
+{
+    rf_freq_ppm_t(double freq = 0.0, double epsilon_ppm = 0.1 /* 1PPM epsilon */)
+        : rf_freq_abs_t(freq, 1e-6 * freq * epsilon_ppm)
+    {
+    }
 };
 
 enum lo_stage_t { STAGE_LO1, STAGE_LO2 };
 enum lo_inj_side_t { INJ_LOW_SIDE, INJ_HIGH_SIDE };
 enum lo_synth_mapping_t { MAPPING_NONE, MAPPING_CH0, MAPPING_CH1, MAPPING_SHARED };
 
-static const std::string prepend_ch(std::string name, const std::string& ch) {
+static const std::string prepend_ch(std::string name, const std::string& ch)
+{
     return ch + "/" + name;
 }
 
-static const std::string lo_stage_str(lo_stage_t stage, bool lower = false) {
+static const std::string lo_stage_str(lo_stage_t stage, bool lower = false)
+{
     std::string prefix = lower ? "lo" : "LO";
     return prefix + ((stage == STAGE_LO1) ? "1" : "2");
 }
@@ -53,12 +64,13 @@ static const std::string lo_stage_str(lo_stage_t stage, bool lower = false) {
  *
  * ---------------------------------------------------------
  */
-class twinrx_scheduling_expert : public experts::worker_node_t {
+class twinrx_scheduling_expert : public experts::worker_node_t
+{
 public:
     twinrx_scheduling_expert(const experts::node_retriever_t& db, std::string ch)
-    : experts::worker_node_t(prepend_ch("twinrx_scheduling_expert", ch)),
-      _command_time     (db, prepend_ch("time/cmd", ch)),
-      _rx_frontend_time (db, prepend_ch("time/rx_frontend", ch))
+        : experts::worker_node_t(prepend_ch("twinrx_scheduling_expert", ch))
+        , _command_time(db, prepend_ch("time/cmd", ch))
+        , _rx_frontend_time(db, prepend_ch("time/rx_frontend", ch))
     {
         bind_accessor(_command_time);
         bind_accessor(_rx_frontend_time);
@@ -67,11 +79,11 @@ public:
 private:
     virtual void resolve();
 
-    //Inputs
-    experts::data_reader_t<time_spec_t>    _command_time;
+    // Inputs
+    experts::data_reader_t<time_spec_t> _command_time;
 
-    //Outputs
-    experts::data_writer_t<time_spec_t>    _rx_frontend_time;
+    // Outputs
+    experts::data_writer_t<time_spec_t> _rx_frontend_time;
 };
 
 /*!---------------------------------------------------------
@@ -85,20 +97,21 @@ private:
  * One instance of this expert is required for each channel
  * ---------------------------------------------------------
  */
-class twinrx_freq_path_expert : public experts::worker_node_t {
+class twinrx_freq_path_expert : public experts::worker_node_t
+{
 public:
     twinrx_freq_path_expert(const experts::node_retriever_t& db, std::string ch)
-    : experts::worker_node_t(prepend_ch("twinrx_freq_path_expert", ch)),
-      _rf_freq_d        (db, prepend_ch("freq/desired", ch)),
-      _if_freq_d        (db, prepend_ch("if_freq/desired", ch)),
-      _signal_path      (db, prepend_ch("ch/signal_path", ch)),
-      _lb_presel        (db, prepend_ch("ch/lb_presel", ch)),
-      _hb_presel        (db, prepend_ch("ch/hb_presel", ch)),
-      _lb_preamp_presel (db, prepend_ch("ch/lb_preamp_presel", ch)),
-      _lo1_freq_d       (db, prepend_ch("los/LO1/freq/desired", ch)),
-      _lo2_freq_d       (db, prepend_ch("los/LO2/freq/desired", ch)),
-      _lo1_inj_side     (db, prepend_ch("ch/LO1/inj_side", ch)),
-      _lo2_inj_side     (db, prepend_ch("ch/LO2/inj_side", ch))
+        : experts::worker_node_t(prepend_ch("twinrx_freq_path_expert", ch))
+        , _rf_freq_d(db, prepend_ch("freq/desired", ch))
+        , _if_freq_d(db, prepend_ch("if_freq/desired", ch))
+        , _signal_path(db, prepend_ch("ch/signal_path", ch))
+        , _lb_presel(db, prepend_ch("ch/lb_presel", ch))
+        , _hb_presel(db, prepend_ch("ch/hb_presel", ch))
+        , _lb_preamp_presel(db, prepend_ch("ch/lb_preamp_presel", ch))
+        , _lo1_freq_d(db, prepend_ch("los/LO1/freq/desired", ch))
+        , _lo2_freq_d(db, prepend_ch("los/LO2/freq/desired", ch))
+        , _lo1_inj_side(db, prepend_ch("ch/LO1/inj_side", ch))
+        , _lo2_inj_side(db, prepend_ch("ch/LO2/inj_side", ch))
     {
         bind_accessor(_rf_freq_d);
         bind_accessor(_if_freq_d);
@@ -115,23 +128,25 @@ public:
 private:
     virtual void resolve();
     static lo_inj_side_t _compute_lo2_inj_side(
-        double lo1_freq, double if1_freq,  double if2_freq, double bandwidth);
-    static bool _has_mixer_spurs(
-        double lo1_freq, double lo2_freq, double if2_freq,
-        double bandwidth, int spur_order);
-
-    //Inputs
-    experts::data_reader_t<double>                          _rf_freq_d;
-    experts::data_reader_t<double>                          _if_freq_d;
-    //Outputs
-    experts::data_writer_t<twinrx_ctrl::signal_path_t>      _signal_path;
+        double lo1_freq, double if1_freq, double if2_freq, double bandwidth);
+    static bool _has_mixer_spurs(double lo1_freq,
+        double lo2_freq,
+        double if2_freq,
+        double bandwidth,
+        int spur_order);
+
+    // Inputs
+    experts::data_reader_t<double> _rf_freq_d;
+    experts::data_reader_t<double> _if_freq_d;
+    // Outputs
+    experts::data_writer_t<twinrx_ctrl::signal_path_t> _signal_path;
     experts::data_writer_t<twinrx_ctrl::preselector_path_t> _lb_presel;
     experts::data_writer_t<twinrx_ctrl::preselector_path_t> _hb_presel;
-    experts::data_writer_t<bool>                            _lb_preamp_presel;
-    experts::data_writer_t<double>                          _lo1_freq_d;
-    experts::data_writer_t<double>                          _lo2_freq_d;
-    experts::data_writer_t<lo_inj_side_t>                   _lo1_inj_side;
-    experts::data_writer_t<lo_inj_side_t>                   _lo2_inj_side;
+    experts::data_writer_t<bool> _lb_preamp_presel;
+    experts::data_writer_t<double> _lo1_freq_d;
+    experts::data_writer_t<double> _lo2_freq_d;
+    experts::data_writer_t<lo_inj_side_t> _lo1_inj_side;
+    experts::data_writer_t<lo_inj_side_t> _lo2_inj_side;
 };
 
 /*!---------------------------------------------------------
@@ -145,20 +160,21 @@ private:
  * One instance of this expert is required for all channels
  * ---------------------------------------------------------
  */
-class twinrx_lo_config_expert : public experts::worker_node_t {
+class twinrx_lo_config_expert : public experts::worker_node_t
+{
 public:
     twinrx_lo_config_expert(const experts::node_retriever_t& db)
-    : experts::worker_node_t("twinrx_lo_config_expert"),
-      _lo_source_ch0    (db, prepend_ch("los/all/source", "0")),
-      _lo_source_ch1    (db, prepend_ch("los/all/source", "1")),
-      _lo_export_ch0    (db, prepend_ch("los/all/export", "0")),
-      _lo_export_ch1    (db, prepend_ch("los/all/export", "1")),
-      _lo1_src_ch0      (db, prepend_ch("ch/LO1/source", "0")),
-      _lo1_src_ch1      (db, prepend_ch("ch/LO1/source", "1")),
-      _lo2_src_ch0      (db, prepend_ch("ch/LO2/source", "0")),
-      _lo2_src_ch1      (db, prepend_ch("ch/LO2/source", "1")),
-      _lo1_export_src   (db, "com/LO1/export_source"),
-      _lo2_export_src   (db, "com/LO2/export_source")
+        : experts::worker_node_t("twinrx_lo_config_expert")
+        , _lo_source_ch0(db, prepend_ch("los/all/source", "0"))
+        , _lo_source_ch1(db, prepend_ch("los/all/source", "1"))
+        , _lo_export_ch0(db, prepend_ch("los/all/export", "0"))
+        , _lo_export_ch1(db, prepend_ch("los/all/export", "1"))
+        , _lo1_src_ch0(db, prepend_ch("ch/LO1/source", "0"))
+        , _lo1_src_ch1(db, prepend_ch("ch/LO1/source", "1"))
+        , _lo2_src_ch0(db, prepend_ch("ch/LO2/source", "0"))
+        , _lo2_src_ch1(db, prepend_ch("ch/LO2/source", "1"))
+        , _lo1_export_src(db, "com/LO1/export_source")
+        , _lo2_export_src(db, "com/LO2/export_source")
     {
         bind_accessor(_lo_source_ch0);
         bind_accessor(_lo_source_ch1);
@@ -175,16 +191,16 @@ public:
 private:
     virtual void resolve();
 
-    //Inputs
-    experts::data_reader_t<std::string>                     _lo_source_ch0;
-    experts::data_reader_t<std::string>                     _lo_source_ch1;
-    experts::data_reader_t<bool>                            _lo_export_ch0;
-    experts::data_reader_t<bool>                            _lo_export_ch1;
-    //Outputs
-    experts::data_writer_t<twinrx_ctrl::lo_source_t>        _lo1_src_ch0;
-    experts::data_writer_t<twinrx_ctrl::lo_source_t>        _lo1_src_ch1;
-    experts::data_writer_t<twinrx_ctrl::lo_source_t>        _lo2_src_ch0;
-    experts::data_writer_t<twinrx_ctrl::lo_source_t>        _lo2_src_ch1;
+    // Inputs
+    experts::data_reader_t<std::string> _lo_source_ch0;
+    experts::data_reader_t<std::string> _lo_source_ch1;
+    experts::data_reader_t<bool> _lo_export_ch0;
+    experts::data_reader_t<bool> _lo_export_ch1;
+    // Outputs
+    experts::data_writer_t<twinrx_ctrl::lo_source_t> _lo1_src_ch0;
+    experts::data_writer_t<twinrx_ctrl::lo_source_t> _lo1_src_ch1;
+    experts::data_writer_t<twinrx_ctrl::lo_source_t> _lo2_src_ch0;
+    experts::data_writer_t<twinrx_ctrl::lo_source_t> _lo2_src_ch1;
     experts::data_writer_t<twinrx_ctrl::lo_export_source_t> _lo1_export_src;
     experts::data_writer_t<twinrx_ctrl::lo_export_source_t> _lo2_export_src;
 };
@@ -201,15 +217,20 @@ private:
  * One instance of this expert is required for each LO stage
  * ---------------------------------------------------------
  */
-class twinrx_lo_mapping_expert : public experts::worker_node_t {
+class twinrx_lo_mapping_expert : public experts::worker_node_t
+{
 public:
     twinrx_lo_mapping_expert(const experts::node_retriever_t& db, lo_stage_t stage)
-    : experts::worker_node_t("twinrx_" + lo_stage_str(stage, true) + "_mapping_expert"),
-      _lox_src_ch0          (db, prepend_ch("ch/" + lo_stage_str(stage) + "/source", "0")),
-      _lox_src_ch1          (db, prepend_ch("ch/" + lo_stage_str(stage) + "/source", "1")),
-      _lox_mapping_synth0   (db, prepend_ch("synth/" + lo_stage_str(stage) + "/mapping", "0")),
-      _lox_mapping_synth1   (db, prepend_ch("synth/" + lo_stage_str(stage) + "/mapping", "1")),
-      _lox_hopping_enabled  (db, "com/synth/" + lo_stage_str(stage) + "/hopping_enabled")
+        : experts::worker_node_t(
+              "twinrx_" + lo_stage_str(stage, true) + "_mapping_expert")
+        , _lox_src_ch0(db, prepend_ch("ch/" + lo_stage_str(stage) + "/source", "0"))
+        , _lox_src_ch1(db, prepend_ch("ch/" + lo_stage_str(stage) + "/source", "1"))
+        , _lox_mapping_synth0(
+              db, prepend_ch("synth/" + lo_stage_str(stage) + "/mapping", "0"))
+        , _lox_mapping_synth1(
+              db, prepend_ch("synth/" + lo_stage_str(stage) + "/mapping", "1"))
+        , _lox_hopping_enabled(
+              db, "com/synth/" + lo_stage_str(stage) + "/hopping_enabled")
     {
         bind_accessor(_lox_src_ch0);
         bind_accessor(_lox_src_ch1);
@@ -221,13 +242,13 @@ public:
 private:
     virtual void resolve();
 
-    //Inputs
-    experts::data_reader_t<twinrx_ctrl::lo_source_t>    _lox_src_ch0;
-    experts::data_reader_t<twinrx_ctrl::lo_source_t>    _lox_src_ch1;
-    //Outputs
-    experts::data_writer_t<lo_synth_mapping_t>          _lox_mapping_synth0;
-    experts::data_writer_t<lo_synth_mapping_t>          _lox_mapping_synth1;
-    experts::data_writer_t<bool>                        _lox_hopping_enabled;
+    // Inputs
+    experts::data_reader_t<twinrx_ctrl::lo_source_t> _lox_src_ch0;
+    experts::data_reader_t<twinrx_ctrl::lo_source_t> _lox_src_ch1;
+    // Outputs
+    experts::data_writer_t<lo_synth_mapping_t> _lox_mapping_synth0;
+    experts::data_writer_t<lo_synth_mapping_t> _lox_mapping_synth1;
+    experts::data_writer_t<bool> _lox_hopping_enabled;
 };
 
 /*!---------------------------------------------------------
@@ -240,16 +261,17 @@ private:
  * One instance of this expert is required for each channel
  * ---------------------------------------------------------
  */
-class twinrx_freq_coercion_expert : public experts::worker_node_t {
+class twinrx_freq_coercion_expert : public experts::worker_node_t
+{
 public:
     twinrx_freq_coercion_expert(const experts::node_retriever_t& db, std::string ch)
-    : experts::worker_node_t(prepend_ch("twinrx_freq_coercion_expert", ch)),
-      _lo1_freq_c       (db, prepend_ch("los/LO1/freq/coerced", ch)),
-      _lo2_freq_c       (db, prepend_ch("los/LO2/freq/coerced", ch)),
-      _if_freq_d        (db, prepend_ch("if_freq/desired", ch)),
-      _lo1_inj_side     (db, prepend_ch("ch/LO1/inj_side", ch)),
-      _lo2_inj_side     (db, prepend_ch("ch/LO2/inj_side", ch)),
-      _rf_freq_c        (db, prepend_ch("freq/coerced", ch))
+        : experts::worker_node_t(prepend_ch("twinrx_freq_coercion_expert", ch))
+        , _lo1_freq_c(db, prepend_ch("los/LO1/freq/coerced", ch))
+        , _lo2_freq_c(db, prepend_ch("los/LO2/freq/coerced", ch))
+        , _if_freq_d(db, prepend_ch("if_freq/desired", ch))
+        , _lo1_inj_side(db, prepend_ch("ch/LO1/inj_side", ch))
+        , _lo2_inj_side(db, prepend_ch("ch/LO2/inj_side", ch))
+        , _rf_freq_c(db, prepend_ch("freq/coerced", ch))
     {
         bind_accessor(_lo1_freq_c);
         bind_accessor(_lo2_freq_c);
@@ -262,14 +284,14 @@ public:
 private:
     virtual void resolve();
 
-    //Inputs
-    experts::data_reader_t<double>          _lo1_freq_c;
-    experts::data_reader_t<double>          _lo2_freq_c;
-    experts::data_reader_t<double>          _if_freq_d;
-    experts::data_reader_t<lo_inj_side_t>   _lo1_inj_side;
-    experts::data_reader_t<lo_inj_side_t>   _lo2_inj_side;
-    //Outputs
-    experts::data_writer_t<double>          _rf_freq_c;
+    // Inputs
+    experts::data_reader_t<double> _lo1_freq_c;
+    experts::data_reader_t<double> _lo2_freq_c;
+    experts::data_reader_t<double> _if_freq_d;
+    experts::data_reader_t<lo_inj_side_t> _lo1_inj_side;
+    experts::data_reader_t<lo_inj_side_t> _lo2_inj_side;
+    // Outputs
+    experts::data_writer_t<double> _rf_freq_c;
 };
 
 /*!---------------------------------------------------------
@@ -281,21 +303,23 @@ private:
  * One instance of this expert is required for each channel
  * ---------------------------------------------------------
  */
-class twinrx_nyquist_expert : public experts::worker_node_t {
+class twinrx_nyquist_expert : public experts::worker_node_t
+{
 public:
-    twinrx_nyquist_expert(const experts::node_retriever_t& db, std::string ch,
-                          dboard_iface::sptr db_iface)
-    : experts::worker_node_t(prepend_ch("twinrx_nyquist_expert", ch)),
-      _channel          (ch),
-      _codec_conn       (ch=="0"?"II":"QQ"),    //Ch->ADC Port mapping
-      _lo1_freq_d       (db, prepend_ch("los/LO1/freq/desired", ch)),
-      _lo2_freq_d       (db, prepend_ch("los/LO2/freq/desired", ch)),
-      _if_freq_d        (db, prepend_ch("if_freq/desired", ch)),
-      _lo1_inj_side     (db, prepend_ch("ch/LO1/inj_side", ch)),
-      _lo2_inj_side     (db, prepend_ch("ch/LO2/inj_side", ch)),
-      _rx_frontend_time (db, prepend_ch("time/rx_frontend", ch)),
-      _if_freq_c        (db, prepend_ch("if_freq/coerced", ch)),
-      _db_iface         (db_iface)
+    twinrx_nyquist_expert(
+        const experts::node_retriever_t& db, std::string ch, dboard_iface::sptr db_iface)
+        : experts::worker_node_t(prepend_ch("twinrx_nyquist_expert", ch))
+        , _channel(ch)
+        , _codec_conn(ch == "0" ? "II" : "QQ")
+        , // Ch->ADC Port mapping
+        _lo1_freq_d(db, prepend_ch("los/LO1/freq/desired", ch))
+        , _lo2_freq_d(db, prepend_ch("los/LO2/freq/desired", ch))
+        , _if_freq_d(db, prepend_ch("if_freq/desired", ch))
+        , _lo1_inj_side(db, prepend_ch("ch/LO1/inj_side", ch))
+        , _lo2_inj_side(db, prepend_ch("ch/LO2/inj_side", ch))
+        , _rx_frontend_time(db, prepend_ch("time/rx_frontend", ch))
+        , _if_freq_c(db, prepend_ch("if_freq/coerced", ch))
+        , _db_iface(db_iface)
     {
         bind_accessor(_lo1_freq_d);
         bind_accessor(_lo2_freq_d);
@@ -309,22 +333,22 @@ public:
 private:
     virtual void resolve();
 
-    //Inputs
-    const std::string                                       _channel;
-    const std::string                                       _codec_conn;
-    experts::data_reader_t<double>                          _lo1_freq_d;
-    experts::data_reader_t<double>                          _lo2_freq_d;
-    experts::data_reader_t<double>                          _if_freq_d;
-    experts::data_reader_t<lo_inj_side_t>                   _lo1_inj_side;
-    experts::data_reader_t<lo_inj_side_t>                   _lo2_inj_side;
-    experts::data_reader_t<time_spec_t>                     _rx_frontend_time;
-
-    //Outputs
-    experts::data_writer_t<double>                          _if_freq_c;
-    dboard_iface::sptr                                      _db_iface;
-
-    //Misc
-    time_spec_t  _cached_cmd_time;
+    // Inputs
+    const std::string _channel;
+    const std::string _codec_conn;
+    experts::data_reader_t<double> _lo1_freq_d;
+    experts::data_reader_t<double> _lo2_freq_d;
+    experts::data_reader_t<double> _if_freq_d;
+    experts::data_reader_t<lo_inj_side_t> _lo1_inj_side;
+    experts::data_reader_t<lo_inj_side_t> _lo2_inj_side;
+    experts::data_reader_t<time_spec_t> _rx_frontend_time;
+
+    // Outputs
+    experts::data_writer_t<double> _if_freq_c;
+    dboard_iface::sptr _db_iface;
+
+    // Misc
+    time_spec_t _cached_cmd_time;
 };
 
 /*!---------------------------------------------------------
@@ -337,18 +361,19 @@ private:
  * One instance of this expert is required for all channels
  * ---------------------------------------------------------
  */
-class twinrx_antenna_expert : public experts::worker_node_t {
+class twinrx_antenna_expert : public experts::worker_node_t
+{
 public:
     twinrx_antenna_expert(const experts::node_retriever_t& db)
-    : experts::worker_node_t("twinrx_antenna_expert"),
-      _antenna_ch0      (db, prepend_ch("antenna", "0")),
-      _antenna_ch1      (db, prepend_ch("antenna", "1")),
-      _enabled_ch0      (db, prepend_ch("enabled", "0")),
-      _enabled_ch1      (db, prepend_ch("enabled", "1")),
-      _lo_export_ch0    (db, prepend_ch("los/all/export", "0")),
-      _lo_export_ch1    (db, prepend_ch("los/all/export", "1")),
-      _ant_mapping      (db, "com/ant_mapping"),
-      _cal_mode         (db, "com/cal_mode")
+        : experts::worker_node_t("twinrx_antenna_expert")
+        , _antenna_ch0(db, prepend_ch("antenna", "0"))
+        , _antenna_ch1(db, prepend_ch("antenna", "1"))
+        , _enabled_ch0(db, prepend_ch("enabled", "0"))
+        , _enabled_ch1(db, prepend_ch("enabled", "1"))
+        , _lo_export_ch0(db, prepend_ch("los/all/export", "0"))
+        , _lo_export_ch1(db, prepend_ch("los/all/export", "1"))
+        , _ant_mapping(db, "com/ant_mapping")
+        , _cal_mode(db, "com/cal_mode")
     {
         bind_accessor(_antenna_ch0);
         bind_accessor(_antenna_ch1);
@@ -363,16 +388,16 @@ public:
 private:
     virtual void resolve();
 
-    //Inputs
-    experts::data_reader_t<std::string>                     _antenna_ch0;
-    experts::data_reader_t<std::string>                     _antenna_ch1;
-    experts::data_reader_t<bool>                            _enabled_ch0;
-    experts::data_reader_t<bool>                            _enabled_ch1;
-    experts::data_reader_t<bool>                            _lo_export_ch0;
-    experts::data_reader_t<bool>                            _lo_export_ch1;
-    //Outputs
-    experts::data_writer_t<twinrx_ctrl::antenna_mapping_t>  _ant_mapping;
-    experts::data_writer_t<twinrx_ctrl::cal_mode_t>         _cal_mode;
+    // Inputs
+    experts::data_reader_t<std::string> _antenna_ch0;
+    experts::data_reader_t<std::string> _antenna_ch1;
+    experts::data_reader_t<bool> _enabled_ch0;
+    experts::data_reader_t<bool> _enabled_ch1;
+    experts::data_reader_t<bool> _lo_export_ch0;
+    experts::data_reader_t<bool> _lo_export_ch1;
+    // Outputs
+    experts::data_writer_t<twinrx_ctrl::antenna_mapping_t> _ant_mapping;
+    experts::data_writer_t<twinrx_ctrl::cal_mode_t> _cal_mode;
 };
 
 /*!---------------------------------------------------------
@@ -386,21 +411,22 @@ private:
  * One instance of this expert is required for each channel
  * ---------------------------------------------------------
  */
-class twinrx_chan_gain_expert : public experts::worker_node_t {
+class twinrx_chan_gain_expert : public experts::worker_node_t
+{
 public:
     twinrx_chan_gain_expert(const experts::node_retriever_t& db, std::string ch)
-    : experts::worker_node_t(prepend_ch("twinrx_chan_gain_expert", ch)),
-      _gain         (db, prepend_ch("gain", ch)),
-      _gain_profile (db, prepend_ch("gain_profile", ch)),
-      _signal_path  (db, prepend_ch("ch/signal_path", ch)),
-      _lb_presel    (db, prepend_ch("ch/lb_presel", ch)),
-      _hb_presel    (db, prepend_ch("ch/hb_presel", ch)),
-      _ant_mapping  (db, "com/ant_mapping"),
-      _input_atten  (db, prepend_ch("ch/input_atten", ch)),
-      _lb_atten     (db, prepend_ch("ch/lb_atten", ch)),
-      _hb_atten     (db, prepend_ch("ch/hb_atten", ch)),
-      _preamp1      (db, prepend_ch("ch/preamp1", ch)),
-      _preamp2      (db, prepend_ch("ch/preamp2", ch))
+        : experts::worker_node_t(prepend_ch("twinrx_chan_gain_expert", ch))
+        , _gain(db, prepend_ch("gain", ch))
+        , _gain_profile(db, prepend_ch("gain_profile", ch))
+        , _signal_path(db, prepend_ch("ch/signal_path", ch))
+        , _lb_presel(db, prepend_ch("ch/lb_presel", ch))
+        , _hb_presel(db, prepend_ch("ch/hb_presel", ch))
+        , _ant_mapping(db, "com/ant_mapping")
+        , _input_atten(db, prepend_ch("ch/input_atten", ch))
+        , _lb_atten(db, prepend_ch("ch/lb_atten", ch))
+        , _hb_atten(db, prepend_ch("ch/hb_atten", ch))
+        , _preamp1(db, prepend_ch("ch/preamp1", ch))
+        , _preamp2(db, prepend_ch("ch/preamp2", ch))
     {
         bind_accessor(_gain);
         bind_accessor(_gain_profile);
@@ -418,19 +444,19 @@ public:
 private:
     virtual void resolve();
 
-    //Inputs
-    experts::data_reader_t<double>                          _gain;
-    experts::data_reader_t<std::string>                     _gain_profile;
-    experts::data_reader_t<twinrx_ctrl::signal_path_t>      _signal_path;
+    // Inputs
+    experts::data_reader_t<double> _gain;
+    experts::data_reader_t<std::string> _gain_profile;
+    experts::data_reader_t<twinrx_ctrl::signal_path_t> _signal_path;
     experts::data_reader_t<twinrx_ctrl::preselector_path_t> _lb_presel;
     experts::data_reader_t<twinrx_ctrl::preselector_path_t> _hb_presel;
-    experts::data_reader_t<twinrx_ctrl::antenna_mapping_t>  _ant_mapping;
-    //Outputs
-    experts::data_writer_t<uint8_t>                  _input_atten;
-    experts::data_writer_t<uint8_t>                  _lb_atten;
-    experts::data_writer_t<uint8_t>                  _hb_atten;
-    experts::data_writer_t<twinrx_ctrl::preamp_state_t>     _preamp1;
-    experts::data_writer_t<bool>                            _preamp2;
+    experts::data_reader_t<twinrx_ctrl::antenna_mapping_t> _ant_mapping;
+    // Outputs
+    experts::data_writer_t<uint8_t> _input_atten;
+    experts::data_writer_t<uint8_t> _lb_atten;
+    experts::data_writer_t<uint8_t> _hb_atten;
+    experts::data_writer_t<twinrx_ctrl::preamp_state_t> _preamp1;
+    experts::data_writer_t<bool> _preamp2;
 };
 
 /*!---------------------------------------------------------
@@ -443,27 +469,28 @@ private:
  * One instance of this expert is required for all channels
  * ---------------------------------------------------------
  */
-class twinrx_ant_gain_expert : public experts::worker_node_t {
+class twinrx_ant_gain_expert : public experts::worker_node_t
+{
 public:
     twinrx_ant_gain_expert(const experts::node_retriever_t& db)
-    : experts::worker_node_t("twinrx_ant_gain_expert"),
-      _ant_mapping          (db, "com/ant_mapping"),
-      _ch0_input_atten      (db, prepend_ch("ch/input_atten", "0")),
-      _ch0_preamp1          (db, prepend_ch("ch/preamp1", "0")),
-      _ch0_preamp2          (db, prepend_ch("ch/preamp2", "0")),
-      _ch0_lb_preamp_presel (db, prepend_ch("ch/lb_preamp_presel", "0")),
-      _ch1_input_atten      (db, prepend_ch("ch/input_atten", "1")),
-      _ch1_preamp1          (db, prepend_ch("ch/preamp1", "1")),
-      _ch1_preamp2          (db, prepend_ch("ch/preamp2", "1")),
-      _ch1_lb_preamp_presel (db, prepend_ch("ch/lb_preamp_presel", "1")),
-      _ant0_input_atten     (db, prepend_ch("ant/input_atten", "0")),
-      _ant0_preamp1         (db, prepend_ch("ant/preamp1", "0")),
-      _ant0_preamp2         (db, prepend_ch("ant/preamp2", "0")),
-      _ant0_lb_preamp_presel(db, prepend_ch("ant/lb_preamp_presel", "0")),
-      _ant1_input_atten     (db, prepend_ch("ant/input_atten", "1")),
-      _ant1_preamp1         (db, prepend_ch("ant/preamp1", "1")),
-      _ant1_preamp2         (db, prepend_ch("ant/preamp2", "1")),
-      _ant1_lb_preamp_presel(db, prepend_ch("ant/lb_preamp_presel", "1"))
+        : experts::worker_node_t("twinrx_ant_gain_expert")
+        , _ant_mapping(db, "com/ant_mapping")
+        , _ch0_input_atten(db, prepend_ch("ch/input_atten", "0"))
+        , _ch0_preamp1(db, prepend_ch("ch/preamp1", "0"))
+        , _ch0_preamp2(db, prepend_ch("ch/preamp2", "0"))
+        , _ch0_lb_preamp_presel(db, prepend_ch("ch/lb_preamp_presel", "0"))
+        , _ch1_input_atten(db, prepend_ch("ch/input_atten", "1"))
+        , _ch1_preamp1(db, prepend_ch("ch/preamp1", "1"))
+        , _ch1_preamp2(db, prepend_ch("ch/preamp2", "1"))
+        , _ch1_lb_preamp_presel(db, prepend_ch("ch/lb_preamp_presel", "1"))
+        , _ant0_input_atten(db, prepend_ch("ant/input_atten", "0"))
+        , _ant0_preamp1(db, prepend_ch("ant/preamp1", "0"))
+        , _ant0_preamp2(db, prepend_ch("ant/preamp2", "0"))
+        , _ant0_lb_preamp_presel(db, prepend_ch("ant/lb_preamp_presel", "0"))
+        , _ant1_input_atten(db, prepend_ch("ant/input_atten", "1"))
+        , _ant1_preamp1(db, prepend_ch("ant/preamp1", "1"))
+        , _ant1_preamp2(db, prepend_ch("ant/preamp2", "1"))
+        , _ant1_lb_preamp_presel(db, prepend_ch("ant/lb_preamp_presel", "1"))
     {
         bind_accessor(_ant_mapping);
         bind_accessor(_ch0_input_atten);
@@ -487,26 +514,26 @@ public:
 private:
     virtual void resolve();
 
-    //Inputs
-    experts::data_reader_t<twinrx_ctrl::antenna_mapping_t>  _ant_mapping;
-    experts::data_reader_t<uint8_t>                  _ch0_input_atten;
-    experts::data_reader_t<twinrx_ctrl::preamp_state_t>     _ch0_preamp1;
-    experts::data_reader_t<bool>                            _ch0_preamp2;
-    experts::data_reader_t<bool>                            _ch0_lb_preamp_presel;
-    experts::data_reader_t<uint8_t>                  _ch1_input_atten;
-    experts::data_reader_t<twinrx_ctrl::preamp_state_t>     _ch1_preamp1;
-    experts::data_reader_t<bool>                            _ch1_preamp2;
-    experts::data_reader_t<bool>                            _ch1_lb_preamp_presel;
-
-    //Outputs
-    experts::data_writer_t<uint8_t>                  _ant0_input_atten;
-    experts::data_writer_t<twinrx_ctrl::preamp_state_t>     _ant0_preamp1;
-    experts::data_writer_t<bool>                            _ant0_preamp2;
-    experts::data_writer_t<bool>                            _ant0_lb_preamp_presel;
-    experts::data_writer_t<uint8_t>                  _ant1_input_atten;
-    experts::data_writer_t<twinrx_ctrl::preamp_state_t>     _ant1_preamp1;
-    experts::data_writer_t<bool>                            _ant1_preamp2;
-    experts::data_writer_t<bool>                            _ant1_lb_preamp_presel;
+    // Inputs
+    experts::data_reader_t<twinrx_ctrl::antenna_mapping_t> _ant_mapping;
+    experts::data_reader_t<uint8_t> _ch0_input_atten;
+    experts::data_reader_t<twinrx_ctrl::preamp_state_t> _ch0_preamp1;
+    experts::data_reader_t<bool> _ch0_preamp2;
+    experts::data_reader_t<bool> _ch0_lb_preamp_presel;
+    experts::data_reader_t<uint8_t> _ch1_input_atten;
+    experts::data_reader_t<twinrx_ctrl::preamp_state_t> _ch1_preamp1;
+    experts::data_reader_t<bool> _ch1_preamp2;
+    experts::data_reader_t<bool> _ch1_lb_preamp_presel;
+
+    // Outputs
+    experts::data_writer_t<uint8_t> _ant0_input_atten;
+    experts::data_writer_t<twinrx_ctrl::preamp_state_t> _ant0_preamp1;
+    experts::data_writer_t<bool> _ant0_preamp2;
+    experts::data_writer_t<bool> _ant0_lb_preamp_presel;
+    experts::data_writer_t<uint8_t> _ant1_input_atten;
+    experts::data_writer_t<twinrx_ctrl::preamp_state_t> _ant1_preamp1;
+    experts::data_writer_t<bool> _ant1_preamp2;
+    experts::data_writer_t<bool> _ant1_lb_preamp_presel;
 };
 
 /*!---------------------------------------------------------
@@ -521,25 +548,27 @@ private:
  * One instance of this expert is required for all channels
  * ---------------------------------------------------------
  */
-class twinrx_settings_expert : public experts::worker_node_t {
+class twinrx_settings_expert : public experts::worker_node_t
+{
 public:
     twinrx_settings_expert(const experts::node_retriever_t& db, twinrx_ctrl::sptr ctrl)
-    : experts::worker_node_t("twinrx_settings_expert"), _ctrl(ctrl),
-      _ch0              (db, "0"),
-      _ch1              (db, "1"),
-      _lo1_synth0_mapping(db, "0/synth/LO1/mapping"),
-      _lo1_synth1_mapping(db, "1/synth/LO1/mapping"),
-      _lo2_synth0_mapping(db, "0/synth/LO2/mapping"),
-      _lo2_synth1_mapping(db, "1/synth/LO2/mapping"),
-      _lo1_hopping_enabled(db, "com/synth/LO1/hopping_enabled"),
-      _lo2_hopping_enabled(db, "com/synth/LO2/hopping_enabled"),
-      _lo1_export_src   (db, "com/LO1/export_source"),
-      _lo2_export_src   (db, "com/LO2/export_source"),
-      _ant_mapping      (db, "com/ant_mapping"),
-      _cal_mode         (db, "com/cal_mode")
+        : experts::worker_node_t("twinrx_settings_expert")
+        , _ctrl(ctrl)
+        , _ch0(db, "0")
+        , _ch1(db, "1")
+        , _lo1_synth0_mapping(db, "0/synth/LO1/mapping")
+        , _lo1_synth1_mapping(db, "1/synth/LO1/mapping")
+        , _lo2_synth0_mapping(db, "0/synth/LO2/mapping")
+        , _lo2_synth1_mapping(db, "1/synth/LO2/mapping")
+        , _lo1_hopping_enabled(db, "com/synth/LO1/hopping_enabled")
+        , _lo2_hopping_enabled(db, "com/synth/LO2/hopping_enabled")
+        , _lo1_export_src(db, "com/LO1/export_source")
+        , _lo2_export_src(db, "com/LO2/export_source")
+        , _ant_mapping(db, "com/ant_mapping")
+        , _cal_mode(db, "com/cal_mode")
     {
         for (size_t i = 0; i < 2; i++) {
-            ch_settings& ch = (i==1) ? _ch1 : _ch0;
+            ch_settings& ch = (i == 1) ? _ch1 : _ch0;
             bind_accessor(ch.chan_enabled);
             bind_accessor(ch.preamp1);
             bind_accessor(ch.preamp2);
@@ -575,103 +604,105 @@ public:
 
 private:
     virtual void resolve();
-    void _resolve_lox_freq(
-        lo_stage_t                      lo_stage,
+    void _resolve_lox_freq(lo_stage_t lo_stage,
         experts::data_reader_t<double>& ch0_freq_d,
         experts::data_reader_t<double>& ch1_freq_d,
         experts::data_writer_t<double>& ch0_freq_c,
         experts::data_writer_t<double>& ch1_freq_c,
-        twinrx_ctrl::lo_source_t        ch0_lo_source,
-        twinrx_ctrl::lo_source_t        ch1_lo_source,
-        lo_synth_mapping_t              synth0_mapping,
-        lo_synth_mapping_t              synth1_mapping,
-        bool                            hopping_enabled);
+        twinrx_ctrl::lo_source_t ch0_lo_source,
+        twinrx_ctrl::lo_source_t ch1_lo_source,
+        lo_synth_mapping_t synth0_mapping,
+        lo_synth_mapping_t synth1_mapping,
+        bool hopping_enabled);
     double _set_lox_synth_freq(lo_stage_t stage, twinrx_ctrl::channel_t ch, double freq);
 
-    class ch_settings {
+    class ch_settings
+    {
     public:
-        ch_settings(const experts::node_retriever_t& db, const std::string& ch) :
-            chan_enabled         (db, prepend_ch("enabled", ch)),
-            preamp1              (db, prepend_ch("ant/preamp1", ch)),
-            preamp2              (db, prepend_ch("ant/preamp2", ch)),
-            lb_preamp_presel     (db, prepend_ch("ant/lb_preamp_presel", ch)),
-            signal_path          (db, prepend_ch("ch/signal_path", ch)),
-            lb_presel            (db, prepend_ch("ch/lb_presel", ch)),
-            hb_presel            (db, prepend_ch("ch/hb_presel", ch)),
-            input_atten          (db, prepend_ch("ant/input_atten", ch)),
-            lb_atten             (db, prepend_ch("ch/lb_atten", ch)),
-            hb_atten             (db, prepend_ch("ch/hb_atten", ch)),
-            lo1_source           (db, prepend_ch("ch/LO1/source", ch)),
-            lo2_source           (db, prepend_ch("ch/LO2/source", ch)),
-            lo1_freq_d           (db, prepend_ch("los/LO1/freq/desired", ch)),
-            lo2_freq_d           (db, prepend_ch("los/LO2/freq/desired", ch)),
-            lo1_charge_pump_d    (db, prepend_ch("los/LO1/charge_pump/desired", ch)),
-            lo2_charge_pump_d    (db, prepend_ch("los/LO2/charge_pump/desired", ch)),
-            lo1_freq_c           (db, prepend_ch("los/LO1/freq/coerced", ch)),
-            lo2_freq_c           (db, prepend_ch("los/LO2/freq/coerced", ch)),
-            lo1_charge_pump_c    (db, prepend_ch("los/LO1/charge_pump/coerced", ch)),
-            lo2_charge_pump_c    (db, prepend_ch("los/LO2/charge_pump/coerced", ch))
-        {}
-
-        //Inputs (channel specific)
-        experts::data_reader_t<bool>                            chan_enabled;
-        experts::data_reader_t<twinrx_ctrl::preamp_state_t>     preamp1;
-        experts::data_reader_t<bool>                            preamp2;
-        experts::data_reader_t<bool>                            lb_preamp_presel;
-        experts::data_reader_t<twinrx_ctrl::signal_path_t>      signal_path;
+        ch_settings(const experts::node_retriever_t& db, const std::string& ch)
+            : chan_enabled(db, prepend_ch("enabled", ch))
+            , preamp1(db, prepend_ch("ant/preamp1", ch))
+            , preamp2(db, prepend_ch("ant/preamp2", ch))
+            , lb_preamp_presel(db, prepend_ch("ant/lb_preamp_presel", ch))
+            , signal_path(db, prepend_ch("ch/signal_path", ch))
+            , lb_presel(db, prepend_ch("ch/lb_presel", ch))
+            , hb_presel(db, prepend_ch("ch/hb_presel", ch))
+            , input_atten(db, prepend_ch("ant/input_atten", ch))
+            , lb_atten(db, prepend_ch("ch/lb_atten", ch))
+            , hb_atten(db, prepend_ch("ch/hb_atten", ch))
+            , lo1_source(db, prepend_ch("ch/LO1/source", ch))
+            , lo2_source(db, prepend_ch("ch/LO2/source", ch))
+            , lo1_freq_d(db, prepend_ch("los/LO1/freq/desired", ch))
+            , lo2_freq_d(db, prepend_ch("los/LO2/freq/desired", ch))
+            , lo1_charge_pump_d(db, prepend_ch("los/LO1/charge_pump/desired", ch))
+            , lo2_charge_pump_d(db, prepend_ch("los/LO2/charge_pump/desired", ch))
+            , lo1_freq_c(db, prepend_ch("los/LO1/freq/coerced", ch))
+            , lo2_freq_c(db, prepend_ch("los/LO2/freq/coerced", ch))
+            , lo1_charge_pump_c(db, prepend_ch("los/LO1/charge_pump/coerced", ch))
+            , lo2_charge_pump_c(db, prepend_ch("los/LO2/charge_pump/coerced", ch))
+        {
+        }
+
+        // Inputs (channel specific)
+        experts::data_reader_t<bool> chan_enabled;
+        experts::data_reader_t<twinrx_ctrl::preamp_state_t> preamp1;
+        experts::data_reader_t<bool> preamp2;
+        experts::data_reader_t<bool> lb_preamp_presel;
+        experts::data_reader_t<twinrx_ctrl::signal_path_t> signal_path;
         experts::data_reader_t<twinrx_ctrl::preselector_path_t> lb_presel;
         experts::data_reader_t<twinrx_ctrl::preselector_path_t> hb_presel;
-        experts::data_reader_t<uint8_t>                         input_atten;
-        experts::data_reader_t<uint8_t>                         lb_atten;
-        experts::data_reader_t<uint8_t>                         hb_atten;
-        experts::data_reader_t<twinrx_ctrl::lo_source_t>        lo1_source;
-        experts::data_reader_t<twinrx_ctrl::lo_source_t>        lo2_source;
-        experts::data_reader_t<double>                          lo1_freq_d;
-        experts::data_reader_t<double>                          lo2_freq_d;
-        experts::data_reader_t<double>                          lo1_charge_pump_d;
-        experts::data_reader_t<double>                          lo2_charge_pump_d;
-
-        //Output (channel specific)
-        experts::data_writer_t<double>                          lo1_freq_c;
-        experts::data_writer_t<double>                          lo2_freq_c;
-        experts::data_writer_t<double>                          lo1_charge_pump_c;
-        experts::data_writer_t<double>                          lo2_charge_pump_c;
+        experts::data_reader_t<uint8_t> input_atten;
+        experts::data_reader_t<uint8_t> lb_atten;
+        experts::data_reader_t<uint8_t> hb_atten;
+        experts::data_reader_t<twinrx_ctrl::lo_source_t> lo1_source;
+        experts::data_reader_t<twinrx_ctrl::lo_source_t> lo2_source;
+        experts::data_reader_t<double> lo1_freq_d;
+        experts::data_reader_t<double> lo2_freq_d;
+        experts::data_reader_t<double> lo1_charge_pump_d;
+        experts::data_reader_t<double> lo2_charge_pump_d;
+
+        // Output (channel specific)
+        experts::data_writer_t<double> lo1_freq_c;
+        experts::data_writer_t<double> lo2_freq_c;
+        experts::data_writer_t<double> lo1_charge_pump_c;
+        experts::data_writer_t<double> lo2_charge_pump_c;
     };
 
-    //External interface
-    twinrx_ctrl::sptr                                       _ctrl;
-
-    //Inputs (channel agnostic)
-    ch_settings                                             _ch0;
-    ch_settings                                             _ch1;
-    experts::data_reader_t<lo_synth_mapping_t>              _lo1_synth0_mapping;
-    experts::data_reader_t<lo_synth_mapping_t>              _lo1_synth1_mapping;
-    experts::data_reader_t<lo_synth_mapping_t>              _lo2_synth0_mapping;
-    experts::data_reader_t<lo_synth_mapping_t>              _lo2_synth1_mapping;
-    experts::data_reader_t<bool>                            _lo1_hopping_enabled;
-    experts::data_reader_t<bool>                            _lo2_hopping_enabled;
+    // External interface
+    twinrx_ctrl::sptr _ctrl;
+
+    // Inputs (channel agnostic)
+    ch_settings _ch0;
+    ch_settings _ch1;
+    experts::data_reader_t<lo_synth_mapping_t> _lo1_synth0_mapping;
+    experts::data_reader_t<lo_synth_mapping_t> _lo1_synth1_mapping;
+    experts::data_reader_t<lo_synth_mapping_t> _lo2_synth0_mapping;
+    experts::data_reader_t<lo_synth_mapping_t> _lo2_synth1_mapping;
+    experts::data_reader_t<bool> _lo1_hopping_enabled;
+    experts::data_reader_t<bool> _lo2_hopping_enabled;
     experts::data_reader_t<twinrx_ctrl::lo_export_source_t> _lo1_export_src;
     experts::data_reader_t<twinrx_ctrl::lo_export_source_t> _lo2_export_src;
-    experts::data_reader_t<twinrx_ctrl::antenna_mapping_t>  _ant_mapping;
-    experts::data_reader_t<twinrx_ctrl::cal_mode_t>         _cal_mode;
+    experts::data_reader_t<twinrx_ctrl::antenna_mapping_t> _ant_mapping;
+    experts::data_reader_t<twinrx_ctrl::cal_mode_t> _cal_mode;
 
-    //Outputs (channel agnostic)
-    //None
+    // Outputs (channel agnostic)
+    // None
 
-    //Misc
-    struct lo_freq_cache_t {
+    // Misc
+    struct lo_freq_cache_t
+    {
         rf_freq_ppm_t desired;
-        double        coerced;
+        double coerced;
     };
-    lo_freq_cache_t  _cached_lo1_synth0_freq;
-    lo_freq_cache_t  _cached_lo2_synth0_freq;
-    lo_freq_cache_t  _cached_lo1_synth1_freq;
-    lo_freq_cache_t  _cached_lo2_synth1_freq;
+    lo_freq_cache_t _cached_lo1_synth0_freq;
+    lo_freq_cache_t _cached_lo2_synth0_freq;
+    lo_freq_cache_t _cached_lo1_synth1_freq;
+    lo_freq_cache_t _cached_lo2_synth1_freq;
 
     static const bool FORCE_COMMIT;
 };
 
 
-}}}} //namespaces
+}}}} // namespace uhd::usrp::dboard::twinrx
 
 #endif /* INCLUDED_DBOARD_TWINRX_EXPERTS_HPP */
diff --git a/host/lib/usrp/dboard/twinrx/twinrx_gain_tables.cpp b/host/lib/usrp/dboard/twinrx/twinrx_gain_tables.cpp
index cc9336f2a..729141b35 100644
--- a/host/lib/usrp/dboard/twinrx/twinrx_gain_tables.cpp
+++ b/host/lib/usrp/dboard/twinrx/twinrx_gain_tables.cpp
@@ -796,13 +796,11 @@ static const std::vector<twinrx_gain_config_t> LOWBAND4_TABLE{
 };
 // clang-format on
 
-const twinrx_gain_table twinrx_gain_table::lookup_table
-(
+const twinrx_gain_table twinrx_gain_table::lookup_table(
     twinrx_ctrl::signal_path_t signal_path,
     twinrx_ctrl::preselector_path_t preselector_path,
-    std::string
-) {
-
+    std::string)
+{
     if (signal_path == twinrx_ctrl::PATH_HIGHBAND) {
         switch (preselector_path) {
             case twinrx_ctrl::PRESEL_PATH1:
@@ -829,12 +827,15 @@ const twinrx_gain_table twinrx_gain_table::lookup_table
     throw runtime_error("NO GAIN TABLE SELECTED");
 }
 
-const twinrx_gain_config_t& twinrx_gain_table::find_by_index(size_t index) const {
-    if (index >= get_num_entries()) throw uhd::value_error("invalid gain table index");
+const twinrx_gain_config_t& twinrx_gain_table::find_by_index(size_t index) const
+{
+    if (index >= get_num_entries())
+        throw uhd::value_error("invalid gain table index");
     return _tbl.at(index);
 }
 
-uhd::gain_range_t twinrx_gain_table::get_gain_range() const {
+uhd::gain_range_t twinrx_gain_table::get_gain_range() const
+{
     double max = std::numeric_limits<double>::min();
     double min = std::numeric_limits<double>::max();
     for (size_t i = 0; i < get_num_entries(); i++) {
diff --git a/host/lib/usrp/dboard/twinrx/twinrx_gain_tables.hpp b/host/lib/usrp/dboard/twinrx/twinrx_gain_tables.hpp
index 94469ab0b..f02241745 100644
--- a/host/lib/usrp/dboard/twinrx/twinrx_gain_tables.hpp
+++ b/host/lib/usrp/dboard/twinrx/twinrx_gain_tables.hpp
@@ -8,56 +8,65 @@
 #ifndef INCLUDED_DBOARD_TWINRX_GAIN_TABLES_HPP
 #define INCLUDED_DBOARD_TWINRX_GAIN_TABLES_HPP
 
+#include "twinrx_ctrl.hpp"
 #include <uhd/config.hpp>
-#include <stdint.h>
 #include <uhd/types/ranges.hpp>
-#include "twinrx_ctrl.hpp"
+#include <stdint.h>
 
 namespace uhd { namespace usrp { namespace dboard { namespace twinrx {
 
-class twinrx_gain_config_t {
+class twinrx_gain_config_t
+{
 public:
-    twinrx_gain_config_t(
-        size_t index_, double sys_gain_,
-        uint8_t atten1_, uint8_t atten2_,
-        bool amp1_, bool amp2_
-    ): index(index_), sys_gain(sys_gain_), atten1(atten1_), atten2(atten2_),
-       amp1(amp1_), amp2(amp2_)
-    {}
+    twinrx_gain_config_t(size_t index_,
+        double sys_gain_,
+        uint8_t atten1_,
+        uint8_t atten2_,
+        bool amp1_,
+        bool amp2_)
+        : index(index_)
+        , sys_gain(sys_gain_)
+        , atten1(atten1_)
+        , atten2(atten2_)
+        , amp1(amp1_)
+        , amp2(amp2_)
+    {
+    }
 
-    twinrx_gain_config_t& operator=(const twinrx_gain_config_t& src) {
+    twinrx_gain_config_t& operator=(const twinrx_gain_config_t& src)
+    {
         if (this != &src) {
-            this->index = src.index;
+            this->index    = src.index;
             this->sys_gain = src.sys_gain;
-            this->atten1 = src.atten1;
-            this->atten2 = src.atten2;
-            this->amp1 = src.amp1;
-            this->amp2 = src.amp2;
+            this->atten1   = src.atten1;
+            this->atten2   = src.atten2;
+            this->amp1     = src.amp1;
+            this->amp2     = src.amp2;
         }
         return *this;
     }
 
-    size_t         index;
-    double         sys_gain;
+    size_t index;
+    double sys_gain;
     uint8_t atten1;
     uint8_t atten2;
-    bool           amp1;
-    bool           amp2;
+    bool amp1;
+    bool amp2;
 };
 
-class twinrx_gain_table {
+class twinrx_gain_table
+{
 public:
-    static const twinrx_gain_table lookup_table(
-        twinrx_ctrl::signal_path_t signal_path,
+    static const twinrx_gain_table lookup_table(twinrx_ctrl::signal_path_t signal_path,
         twinrx_ctrl::preselector_path_t presel_path,
         std::string profile);
 
-    twinrx_gain_table(const std::vector<twinrx_gain_config_t>& tbl)
-    : _tbl(tbl) {}
+    twinrx_gain_table(const std::vector<twinrx_gain_config_t>& tbl) : _tbl(tbl) {}
 
     const twinrx_gain_config_t& find_by_index(size_t index) const;
 
-    inline size_t get_num_entries() const {
+    inline size_t get_num_entries() const
+    {
         return _tbl.size();
     }
 
@@ -68,6 +77,6 @@ private:
 };
 
 
-}}}} //namespaces
+}}}} // namespace uhd::usrp::dboard::twinrx
 
 #endif /* INCLUDED_DBOARD_TWINRX_GAIN_TABLES_HPP */
diff --git a/host/lib/usrp/dboard/twinrx/twinrx_ids.hpp b/host/lib/usrp/dboard/twinrx/twinrx_ids.hpp
index 599b1d456..118090701 100644
--- a/host/lib/usrp/dboard/twinrx/twinrx_ids.hpp
+++ b/host/lib/usrp/dboard/twinrx/twinrx_ids.hpp
@@ -8,9 +8,9 @@ using namespace uhd;
 using namespace usrp;
 
 namespace twinrx {
-    const dboard_id_t TWINRX_REV_A_ID(0x91);
-    const dboard_id_t TWINRX_REV_B_ID(0x93);
-    const dboard_id_t TWINRX_REV_C_ID(0x95);
-}
+const dboard_id_t TWINRX_REV_A_ID(0x91);
+const dboard_id_t TWINRX_REV_B_ID(0x93);
+const dboard_id_t TWINRX_REV_C_ID(0x95);
+} // namespace twinrx
 
 #endif
diff --git a/host/lib/usrp/dboard/twinrx/twinrx_io.hpp b/host/lib/usrp/dboard/twinrx/twinrx_io.hpp
index e3e475148..2949138dd 100644
--- a/host/lib/usrp/dboard/twinrx/twinrx_io.hpp
+++ b/host/lib/usrp/dboard/twinrx/twinrx_io.hpp
@@ -19,24 +19,35 @@ namespace uhd { namespace usrp { namespace dboard { namespace twinrx {
 static const uint32_t SET_ALL_BITS = 0xFFFFFFFF;
 
 namespace cpld {
-static wb_iface::wb_addr_type addr(uint8_t cpld_num, uint8_t cpld_addr) {
-    //Decode CPLD addressing for the following bitmap:
+static wb_iface::wb_addr_type addr(uint8_t cpld_num, uint8_t cpld_addr)
+{
+    // Decode CPLD addressing for the following bitmap:
     // {CPLD1_EN, CPLD2_EN, CPLD3_EN, CPLD4_EN, CPLD_ADDR[2:0]}
     uint8_t addr = 0;
     switch (cpld_num) {
-        case 1: addr = 0x8 << 3; break;
-        case 2: addr = 0x4 << 3; break;
-        case 3: addr = 0x2 << 3; break;
-        case 4: addr = 0x1 << 3; break;
-        default: UHD_THROW_INVALID_CODE_PATH();
+        case 1:
+            addr = 0x8 << 3;
+            break;
+        case 2:
+            addr = 0x4 << 3;
+            break;
+        case 3:
+            addr = 0x2 << 3;
+            break;
+        case 4:
+            addr = 0x1 << 3;
+            break;
+        default:
+            UHD_THROW_INVALID_CODE_PATH();
     }
     return static_cast<wb_iface::wb_addr_type>(addr | (cpld_addr & 0x7));
 }
 
-static uint32_t get_reg(wb_iface::wb_addr_type addr) {
+static uint32_t get_reg(wb_iface::wb_addr_type addr)
+{
     return static_cast<uint32_t>(addr) & 0x7;
 }
-}
+} // namespace cpld
 
 class twinrx_gpio : public wb_iface
 {
@@ -44,163 +55,196 @@ public:
     typedef std::shared_ptr<twinrx_gpio> sptr;
 
     //----------------------------------------------
-    //Public GPIO fields
-    UHD_DEFINE_SOFT_REG_FIELD(FIELD_LO2_CE_CH1,     /*width*/ 1, /*shift*/  0);     //GPIO[0]       OUT
-    UHD_DEFINE_SOFT_REG_FIELD(FIELD_LO2_CE_CH2,     /*width*/ 1, /*shift*/  1);     //GPIO[1]       OUT
-    UHD_DEFINE_SOFT_REG_FIELD(FIELD_LO2_MUXOUT_CH1, /*width*/ 1, /*shift*/  2);     //GPIO[2]       IN
-    UHD_DEFINE_SOFT_REG_FIELD(FIELD_LO2_MUXOUT_CH2, /*width*/ 1, /*shift*/  3);     //GPIO[3]       IN
-    UHD_DEFINE_SOFT_REG_FIELD(FIELD_LO2_LD_CH1,     /*width*/ 1, /*shift*/  4);     //GPIO[4]       IN
-    UHD_DEFINE_SOFT_REG_FIELD(FIELD_LO2_LD_CH2,     /*width*/ 1, /*shift*/  5);     //GPIO[5]       IN
-    // NO CONNECT                                                                   //GPIO[8:6]
-    // PRIVATE                                                                      //GPIO[15:9]
-    // NO CONNECT                                                                   //GPIO[16]
-    UHD_DEFINE_SOFT_REG_FIELD(FIELD_LO1_CE_CH1,     /*width*/ 1, /*shift*/ 17);     //GPIO[17]      OUT
-    UHD_DEFINE_SOFT_REG_FIELD(FIELD_LO1_CE_CH2,     /*width*/ 1, /*shift*/ 18);     //GPIO[18]      OUT
-    UHD_DEFINE_SOFT_REG_FIELD(FIELD_LO1_MUXOUT_CH1, /*width*/ 1, /*shift*/ 19);     //GPIO[19]      IN
-    UHD_DEFINE_SOFT_REG_FIELD(FIELD_LO1_MUXOUT_CH2, /*width*/ 1, /*shift*/ 20);     //GPIO[20]      IN
-    // NO CONNECT                                                                   //GPIO[21:23]
-    UHD_DEFINE_SOFT_REG_FIELD(FIELD_SWPS_CLK,       /*width*/ 1, /*shift*/ 24);     //GPIO[24]      IN
-    UHD_DEFINE_SOFT_REG_FIELD(FIELD_SWPS_PWR_GOOD,  /*width*/ 1, /*shift*/ 25);     //GPIO[25]      IN
-    UHD_DEFINE_SOFT_REG_FIELD(FIELD_SWPS_EN,        /*width*/ 1, /*shift*/ 26);     //GPIO[26]      OUT
-    // PRIVATE                                                                      //GPIO[27:31]
+    // Public GPIO fields
+    UHD_DEFINE_SOFT_REG_FIELD(FIELD_LO2_CE_CH1, /*width*/ 1, /*shift*/ 0); // GPIO[0] OUT
+    UHD_DEFINE_SOFT_REG_FIELD(FIELD_LO2_CE_CH2, /*width*/ 1, /*shift*/ 1); // GPIO[1] OUT
+    UHD_DEFINE_SOFT_REG_FIELD(
+        FIELD_LO2_MUXOUT_CH1, /*width*/ 1, /*shift*/ 2); // GPIO[2]       IN
+    UHD_DEFINE_SOFT_REG_FIELD(
+        FIELD_LO2_MUXOUT_CH2, /*width*/ 1, /*shift*/ 3); // GPIO[3]       IN
+    UHD_DEFINE_SOFT_REG_FIELD(FIELD_LO2_LD_CH1, /*width*/ 1, /*shift*/ 4); // GPIO[4] IN
+    UHD_DEFINE_SOFT_REG_FIELD(FIELD_LO2_LD_CH2, /*width*/ 1, /*shift*/ 5); // GPIO[5] IN
+    // NO CONNECT //GPIO[8:6] PRIVATE //GPIO[15:9] NO CONNECT //GPIO[16]
+    UHD_DEFINE_SOFT_REG_FIELD(
+        FIELD_LO1_CE_CH1, /*width*/ 1, /*shift*/ 17); // GPIO[17]      OUT
+    UHD_DEFINE_SOFT_REG_FIELD(
+        FIELD_LO1_CE_CH2, /*width*/ 1, /*shift*/ 18); // GPIO[18]      OUT
+    UHD_DEFINE_SOFT_REG_FIELD(
+        FIELD_LO1_MUXOUT_CH1, /*width*/ 1, /*shift*/ 19); // GPIO[19]      IN
+    UHD_DEFINE_SOFT_REG_FIELD(
+        FIELD_LO1_MUXOUT_CH2, /*width*/ 1, /*shift*/ 20); // GPIO[20]      IN
+    // NO CONNECT //GPIO[21:23]
+    UHD_DEFINE_SOFT_REG_FIELD(FIELD_SWPS_CLK, /*width*/ 1, /*shift*/ 24); // GPIO[24] IN
+    UHD_DEFINE_SOFT_REG_FIELD(
+        FIELD_SWPS_PWR_GOOD, /*width*/ 1, /*shift*/ 25); // GPIO[25]      IN
+    UHD_DEFINE_SOFT_REG_FIELD(FIELD_SWPS_EN, /*width*/ 1, /*shift*/ 26); // GPIO[26] OUT
+    // PRIVATE //GPIO[27:31]
     //----------------------------------------------
 
-    twinrx_gpio(dboard_iface::sptr iface) : _db_iface(iface) {
+    twinrx_gpio(dboard_iface::sptr iface) : _db_iface(iface)
+    {
         _db_iface->set_gpio_ddr(dboard_iface::UNIT_BOTH, GPIO_OUTPUT_MASK, SET_ALL_BITS);
         _db_iface->set_pin_ctrl(dboard_iface::UNIT_BOTH, GPIO_PINCTRL_MASK, SET_ALL_BITS);
         _db_iface->set_gpio_out(dboard_iface::UNIT_BOTH, 0, ~GPIO_PINCTRL_MASK);
     }
 
-    ~twinrx_gpio() {
+    ~twinrx_gpio()
+    {
         _db_iface->set_gpio_ddr(dboard_iface::UNIT_BOTH, ~GPIO_OUTPUT_MASK, SET_ALL_BITS);
     }
 
-    void set_field(const uhd::soft_reg_field_t field, const uint32_t value) {
+    void set_field(const uhd::soft_reg_field_t field, const uint32_t value)
+    {
         boost::lock_guard<boost::mutex> lock(_mutex);
         using namespace soft_reg_field;
 
-        _db_iface->set_gpio_out(dboard_iface::UNIT_BOTH,
-            (value << shift(field)),
-            mask<uint32_t>(field));
+        _db_iface->set_gpio_out(
+            dboard_iface::UNIT_BOTH, (value << shift(field)), mask<uint32_t>(field));
     }
 
-    uint32_t get_field(const uhd::soft_reg_field_t field) {
+    uint32_t get_field(const uhd::soft_reg_field_t field)
+    {
         boost::lock_guard<boost::mutex> lock(_mutex);
         using namespace soft_reg_field;
-        return (_db_iface->read_gpio(dboard_iface::UNIT_BOTH) & mask<uint32_t>(field)) >> shift(field);
+        return (_db_iface->read_gpio(dboard_iface::UNIT_BOTH) & mask<uint32_t>(field))
+               >> shift(field);
     }
 
     // CPLD register write-only interface
-    void poke32(const wb_addr_type addr, const uint32_t data) {
+    void poke32(const wb_addr_type addr, const uint32_t data)
+    {
         boost::lock_guard<boost::mutex> lock(_mutex);
         using namespace soft_reg_field;
 
-        //Step 1: Write the reg offset and data to the GPIO bus and de-assert all enables
+        // Step 1: Write the reg offset and data to the GPIO bus and de-assert all enables
         _db_iface->set_gpio_out(dboard_iface::UNIT_BOTH,
             (cpld::get_reg(addr) << shift(CPLD_FULL_ADDR)) | (data << shift(CPLD_DATA)),
-            mask<uint32_t>(CPLD_FULL_ADDR)|mask<uint32_t>(CPLD_DATA));
-        //Sleep for 166ns to ensure that we don't toggle the enables too quickly
-        //The underlying sleep function rounds to microsecond precision.
+            mask<uint32_t>(CPLD_FULL_ADDR) | mask<uint32_t>(CPLD_DATA));
+        // Sleep for 166ns to ensure that we don't toggle the enables too quickly
+        // The underlying sleep function rounds to microsecond precision.
         _db_iface->sleep(boost::chrono::nanoseconds(166));
-        //Step 2: Write the reg offset and data, and assert the necessary enable
+        // Step 2: Write the reg offset and data, and assert the necessary enable
         _db_iface->set_gpio_out(dboard_iface::UNIT_BOTH,
-            (static_cast<uint32_t>(addr) << shift(CPLD_FULL_ADDR)) | (data << shift(CPLD_DATA)),
-            mask<uint32_t>(CPLD_FULL_ADDR)|mask<uint32_t>(CPLD_DATA));
+            (static_cast<uint32_t>(addr) << shift(CPLD_FULL_ADDR))
+                | (data << shift(CPLD_DATA)),
+            mask<uint32_t>(CPLD_FULL_ADDR) | mask<uint32_t>(CPLD_DATA));
     }
 
-private:    //Members/definitions
-    static const uint32_t GPIO_OUTPUT_MASK   = 0xFC06FE03;
-    static const uint32_t GPIO_PINCTRL_MASK  = 0x00000000;
+private: // Members/definitions
+    static const uint32_t GPIO_OUTPUT_MASK  = 0xFC06FE03;
+    static const uint32_t GPIO_PINCTRL_MASK = 0x00000000;
 
-    //Private GPIO fields
-    UHD_DEFINE_SOFT_REG_FIELD(CPLD_FULL_ADDR, /*width*/ 7, /*shift*/  9);     //GPIO[15:9]
-    UHD_DEFINE_SOFT_REG_FIELD(CPLD_DATA,      /*width*/ 5, /*shift*/ 27);     //GPIO[31:27]
+    // Private GPIO fields
+    UHD_DEFINE_SOFT_REG_FIELD(CPLD_FULL_ADDR, /*width*/ 7, /*shift*/ 9); // GPIO[15:9]
+    UHD_DEFINE_SOFT_REG_FIELD(CPLD_DATA, /*width*/ 5, /*shift*/ 27); // GPIO[31:27]
 
-    //Members
-    dboard_iface::sptr  _db_iface;
-    boost::mutex        _mutex;
+    // Members
+    dboard_iface::sptr _db_iface;
+    boost::mutex _mutex;
 };
 
-class twinrx_cpld_regmap : public uhd::soft_regmap_t {
+class twinrx_cpld_regmap : public uhd::soft_regmap_t
+{
 public:
     typedef std::shared_ptr<twinrx_cpld_regmap> sptr;
 
     //----------------------------------------------
     // IF CCA: CPLD 1
     //----------------------------------------------
-    class if0_reg0_t : public uhd::soft_reg32_wo_t {
+    class if0_reg0_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(AMP_HB_IF1_EN_CH1,    /*width*/ 1, /*shift*/ 0);
-        UHD_DEFINE_SOFT_REG_FIELD(AMP_LO2_EN_CH1,       /*width*/ 1, /*shift*/ 1);
-        UHD_DEFINE_SOFT_REG_FIELD(AMP_LO2_EN_CH2,       /*width*/ 1, /*shift*/ 2);
-        UHD_DEFINE_SOFT_REG_FIELD(SW19_CTRL_CH2,        /*width*/ 1, /*shift*/ 3);
-        UHD_DEFINE_SOFT_REG_FIELD(SW20_CTRL_CH2,        /*width*/ 1, /*shift*/ 4);
-
-        if0_reg0_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 1, /*reg*/ 0), OPTIMIZED_FLUSH) {
+        UHD_DEFINE_SOFT_REG_FIELD(AMP_HB_IF1_EN_CH1, /*width*/ 1, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(AMP_LO2_EN_CH1, /*width*/ 1, /*shift*/ 1);
+        UHD_DEFINE_SOFT_REG_FIELD(AMP_LO2_EN_CH2, /*width*/ 1, /*shift*/ 2);
+        UHD_DEFINE_SOFT_REG_FIELD(SW19_CTRL_CH2, /*width*/ 1, /*shift*/ 3);
+        UHD_DEFINE_SOFT_REG_FIELD(SW20_CTRL_CH2, /*width*/ 1, /*shift*/ 4);
+
+        if0_reg0_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 1, /*reg*/ 0), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } if0_reg0;
 
-    class if0_reg1_t : public uhd::soft_reg32_wo_t {
+    class if0_reg1_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(SW20_CTRL_CH1,        /*width*/ 1, /*shift*/ 2);
+        UHD_DEFINE_SOFT_REG_FIELD(SW20_CTRL_CH1, /*width*/ 1, /*shift*/ 2);
 
-        if0_reg1_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 1, /*reg*/ 1), OPTIMIZED_FLUSH) {
+        if0_reg1_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 1, /*reg*/ 1), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } if0_reg1;
 
-    class if0_reg2_t : public uhd::soft_reg32_wo_t {
+    class if0_reg2_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(AMP_LB_IF1_EN_CH2,    /*width*/ 1, /*shift*/ 0);
-        UHD_DEFINE_SOFT_REG_FIELD(AMP_LB_IF1_EN_CH1,    /*width*/ 1, /*shift*/ 1);
-        UHD_DEFINE_SOFT_REG_FIELD(LO2_LE_CH1,           /*width*/ 1, /*shift*/ 3);
-        UHD_DEFINE_SOFT_REG_FIELD(LO2_LE_CH2,           /*width*/ 1, /*shift*/ 4);
-
-        if0_reg2_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 1, /*reg*/ 2), OPTIMIZED_FLUSH) {
+        UHD_DEFINE_SOFT_REG_FIELD(AMP_LB_IF1_EN_CH2, /*width*/ 1, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(AMP_LB_IF1_EN_CH1, /*width*/ 1, /*shift*/ 1);
+        UHD_DEFINE_SOFT_REG_FIELD(LO2_LE_CH1, /*width*/ 1, /*shift*/ 3);
+        UHD_DEFINE_SOFT_REG_FIELD(LO2_LE_CH2, /*width*/ 1, /*shift*/ 4);
+
+        if0_reg2_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 1, /*reg*/ 2), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } if0_reg2;
 
-    class if0_reg3_t : public uhd::soft_reg32_wo_t {
+    class if0_reg3_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(SW24_CTRL_CH1,        /*width*/ 1, /*shift*/ 1);
-        UHD_DEFINE_SOFT_REG_FIELD(SW13_CTRL_CH1,        /*width*/ 1, /*shift*/ 2);
-        UHD_DEFINE_SOFT_REG_FIELD(IF1_IF2_EN_CH1,       /*width*/ 1, /*shift*/ 3);
+        UHD_DEFINE_SOFT_REG_FIELD(SW24_CTRL_CH1, /*width*/ 1, /*shift*/ 1);
+        UHD_DEFINE_SOFT_REG_FIELD(SW13_CTRL_CH1, /*width*/ 1, /*shift*/ 2);
+        UHD_DEFINE_SOFT_REG_FIELD(IF1_IF2_EN_CH1, /*width*/ 1, /*shift*/ 3);
 
-        if0_reg3_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 1, /*reg*/ 3), OPTIMIZED_FLUSH) {
+        if0_reg3_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 1, /*reg*/ 3), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } if0_reg3;
 
-    class if0_reg4_t : public uhd::soft_reg32_wo_t {
+    class if0_reg4_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(SW21_CTRL_CH2,        /*width*/ 1, /*shift*/ 0);
-        UHD_DEFINE_SOFT_REG_FIELD(SW25_CTRL,            /*width*/ 1, /*shift*/ 1);
-        UHD_DEFINE_SOFT_REG_FIELD(IF1_IF2_EN_CH2,       /*width*/ 1, /*shift*/ 2);
-        UHD_DEFINE_SOFT_REG_FIELD(SW19_CTRL_CH1,        /*width*/ 1, /*shift*/ 3);
-        UHD_DEFINE_SOFT_REG_FIELD(SW21_CTRL_CH1,        /*width*/ 1, /*shift*/ 4);
-
-        if0_reg4_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 1, /*reg*/ 4), OPTIMIZED_FLUSH) {
+        UHD_DEFINE_SOFT_REG_FIELD(SW21_CTRL_CH2, /*width*/ 1, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(SW25_CTRL, /*width*/ 1, /*shift*/ 1);
+        UHD_DEFINE_SOFT_REG_FIELD(IF1_IF2_EN_CH2, /*width*/ 1, /*shift*/ 2);
+        UHD_DEFINE_SOFT_REG_FIELD(SW19_CTRL_CH1, /*width*/ 1, /*shift*/ 3);
+        UHD_DEFINE_SOFT_REG_FIELD(SW21_CTRL_CH1, /*width*/ 1, /*shift*/ 4);
+
+        if0_reg4_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 1, /*reg*/ 4), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } if0_reg4;
 
-    class if0_reg6_t : public uhd::soft_reg32_wo_t {
+    class if0_reg6_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(AMP_HB_IF1_EN_CH2,    /*width*/ 1, /*shift*/ 0);
-        UHD_DEFINE_SOFT_REG_FIELD(SW13_CTRL_CH2,        /*width*/ 1, /*shift*/ 2);
+        UHD_DEFINE_SOFT_REG_FIELD(AMP_HB_IF1_EN_CH2, /*width*/ 1, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(SW13_CTRL_CH2, /*width*/ 1, /*shift*/ 2);
 
-        if0_reg6_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 1, /*reg*/ 6), OPTIMIZED_FLUSH) {
+        if0_reg6_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 1, /*reg*/ 6), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } if0_reg6;
 
-    class if0_reg7_t : public uhd::soft_reg32_wo_t {
+    class if0_reg7_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(SW24_CTRL_CH2,        /*width*/ 1, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(SW24_CTRL_CH2, /*width*/ 1, /*shift*/ 0);
 
-        if0_reg7_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 1, /*reg*/ 7), OPTIMIZED_FLUSH) {
+        if0_reg7_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 1, /*reg*/ 7), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } if0_reg7;
@@ -208,90 +252,114 @@ public:
     //----------------------------------------------
     // RF CCA: CPLD 2
     //----------------------------------------------
-    class rf0_reg0_t : public uhd::soft_reg32_wo_t {
+    class rf0_reg0_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(ATTEN_IN_CH1,         /*width*/ 5, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(ATTEN_IN_CH1, /*width*/ 5, /*shift*/ 0);
 
-        rf0_reg0_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 2, /*reg*/ 0), OPTIMIZED_FLUSH) {
+        rf0_reg0_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 2, /*reg*/ 0), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf0_reg0;
 
-    class rf0_reg1_t : public uhd::soft_reg32_wo_t {
+    class rf0_reg1_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(SWPA1_CTL_CH1,        /*width*/ 1, /*shift*/ 1);
-        UHD_DEFINE_SOFT_REG_FIELD(HB_PREAMP_EN_CH1,     /*width*/ 1, /*shift*/ 2);
-        UHD_DEFINE_SOFT_REG_FIELD(LB_PREAMP_EN_CH1,     /*width*/ 1, /*shift*/ 3);
-        UHD_DEFINE_SOFT_REG_FIELD(SWPA3_CTRL_CH2,       /*width*/ 1, /*shift*/ 4);
-
-        rf0_reg1_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 2, /*reg*/ 1), OPTIMIZED_FLUSH) {
+        UHD_DEFINE_SOFT_REG_FIELD(SWPA1_CTL_CH1, /*width*/ 1, /*shift*/ 1);
+        UHD_DEFINE_SOFT_REG_FIELD(HB_PREAMP_EN_CH1, /*width*/ 1, /*shift*/ 2);
+        UHD_DEFINE_SOFT_REG_FIELD(LB_PREAMP_EN_CH1, /*width*/ 1, /*shift*/ 3);
+        UHD_DEFINE_SOFT_REG_FIELD(SWPA3_CTRL_CH2, /*width*/ 1, /*shift*/ 4);
+
+        rf0_reg1_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 2, /*reg*/ 1), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf0_reg1;
 
-    class rf0_reg2_t : public uhd::soft_reg32_wo_t {
+    class rf0_reg2_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(SW6_CTRL_CH1,         /*width*/ 1, /*shift*/ 0);
-        UHD_DEFINE_SOFT_REG_FIELD(SW5_CTRL_CH1,         /*width*/ 1, /*shift*/ 1);
-        UHD_DEFINE_SOFT_REG_FIELD(SW4_CTRL_CH1,         /*width*/ 1, /*shift*/ 2);
-        UHD_DEFINE_SOFT_REG_FIELD(LO1_LE_CH1,           /*width*/ 1, /*shift*/ 3);
-        UHD_DEFINE_SOFT_REG_FIELD(LO1_LE_CH2,           /*width*/ 1, /*shift*/ 4);
-
-        rf0_reg2_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 2, /*reg*/ 2), OPTIMIZED_FLUSH) {
+        UHD_DEFINE_SOFT_REG_FIELD(SW6_CTRL_CH1, /*width*/ 1, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(SW5_CTRL_CH1, /*width*/ 1, /*shift*/ 1);
+        UHD_DEFINE_SOFT_REG_FIELD(SW4_CTRL_CH1, /*width*/ 1, /*shift*/ 2);
+        UHD_DEFINE_SOFT_REG_FIELD(LO1_LE_CH1, /*width*/ 1, /*shift*/ 3);
+        UHD_DEFINE_SOFT_REG_FIELD(LO1_LE_CH2, /*width*/ 1, /*shift*/ 4);
+
+        rf0_reg2_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 2, /*reg*/ 2), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf0_reg2;
 
-    class rf0_reg3_t : public uhd::soft_reg32_wo_t {
+    class rf0_reg3_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(SW9_CTRL_CH2,         /*width*/ 2, /*shift*/ 0);
-        UHD_DEFINE_SOFT_REG_FIELD(SW7_CTRL_CH1,         /*width*/ 2, /*shift*/ 2);
+        UHD_DEFINE_SOFT_REG_FIELD(SW9_CTRL_CH2, /*width*/ 2, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(SW7_CTRL_CH1, /*width*/ 2, /*shift*/ 2);
 
-        rf0_reg3_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 2, /*reg*/ 3), OPTIMIZED_FLUSH) {
+        rf0_reg3_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 2, /*reg*/ 3), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf0_reg3;
 
-    class rf0_reg4_t : public uhd::soft_reg32_wo_t {
+    class rf0_reg4_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(ATTEN_IN_CH2,         /*width*/ 5, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(ATTEN_IN_CH2, /*width*/ 5, /*shift*/ 0);
 
-        rf0_reg4_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 2, /*reg*/ 4), OPTIMIZED_FLUSH) {
+        rf0_reg4_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 2, /*reg*/ 4), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf0_reg4;
 
-    class rf0_reg5_t : public uhd::soft_reg32_wo_t {
+    class rf0_reg5_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(SW9_CTRL_CH1,         /*width*/ 2, /*shift*/ 0);
-        UHD_DEFINE_SOFT_REG_FIELD(HB_PREAMP_EN_CH2,     /*width*/ 1, /*shift*/ 2);
-        UHD_DEFINE_SOFT_REG_FIELD(SW3_CTRL_CH1,         /*width*/ 1, /*shift*/ 4);
+        UHD_DEFINE_SOFT_REG_FIELD(SW9_CTRL_CH1, /*width*/ 2, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(HB_PREAMP_EN_CH2, /*width*/ 1, /*shift*/ 2);
+        UHD_DEFINE_SOFT_REG_FIELD(SW3_CTRL_CH1, /*width*/ 1, /*shift*/ 4);
 
-        rf0_reg5_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 2, /*reg*/ 5), OPTIMIZED_FLUSH) {
+        rf0_reg5_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 2, /*reg*/ 5), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf0_reg5;
 
-    class rf0_reg6_t : public uhd::soft_reg32_wo_t {
+    class rf0_reg6_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(SW6_CTRL_CH2,         /*width*/ 1, /*shift*/ 0);
-        UHD_DEFINE_SOFT_REG_FIELD(SW5_CTRL_CH2,         /*width*/ 1, /*shift*/ 1);
-        UHD_DEFINE_SOFT_REG_FIELD(SW4_CTRL_CH2,         /*width*/ 1, /*shift*/ 2);
-        UHD_DEFINE_SOFT_REG_FIELD(SWPA4_CTRL_CH2,       /*width*/ 1, /*shift*/ 4);
-
-        rf0_reg6_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 2, /*reg*/ 6), OPTIMIZED_FLUSH) {
+        UHD_DEFINE_SOFT_REG_FIELD(SW6_CTRL_CH2, /*width*/ 1, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(SW5_CTRL_CH2, /*width*/ 1, /*shift*/ 1);
+        UHD_DEFINE_SOFT_REG_FIELD(SW4_CTRL_CH2, /*width*/ 1, /*shift*/ 2);
+        UHD_DEFINE_SOFT_REG_FIELD(SWPA4_CTRL_CH2, /*width*/ 1, /*shift*/ 4);
+
+        rf0_reg6_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 2, /*reg*/ 6), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf0_reg6;
 
-    class rf0_reg7_t : public uhd::soft_reg32_wo_t {
+    class rf0_reg7_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(SWPA1_CTRL_CH2,       /*width*/ 1, /*shift*/ 0);
-        UHD_DEFINE_SOFT_REG_FIELD(SWPA3_CTRL_CH1,       /*width*/ 1, /*shift*/ 1);
-        UHD_DEFINE_SOFT_REG_FIELD(SW3_CTRL_CH2,         /*width*/ 1, /*shift*/ 2);
-        UHD_DEFINE_SOFT_REG_FIELD(SW7_CTRL_CH2,         /*width*/ 2, /*shift*/ 3);
-
-        rf0_reg7_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 2, /*reg*/ 7), OPTIMIZED_FLUSH) {
+        UHD_DEFINE_SOFT_REG_FIELD(SWPA1_CTRL_CH2, /*width*/ 1, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(SWPA3_CTRL_CH1, /*width*/ 1, /*shift*/ 1);
+        UHD_DEFINE_SOFT_REG_FIELD(SW3_CTRL_CH2, /*width*/ 1, /*shift*/ 2);
+        UHD_DEFINE_SOFT_REG_FIELD(SW7_CTRL_CH2, /*width*/ 2, /*shift*/ 3);
+
+        rf0_reg7_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 2, /*reg*/ 7), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf0_reg7;
@@ -299,91 +367,115 @@ public:
     //----------------------------------------------
     // RF CCA: CPLD 3
     //----------------------------------------------
-    class rf1_reg0_t : public uhd::soft_reg32_wo_t {
+    class rf1_reg0_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(ATTEN_HB_CH1,         /*width*/ 5, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(ATTEN_HB_CH1, /*width*/ 5, /*shift*/ 0);
 
-        rf1_reg0_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 3, /*reg*/ 0), OPTIMIZED_FLUSH) {
+        rf1_reg0_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 3, /*reg*/ 0), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf1_reg0;
 
-    class rf1_reg1_t : public uhd::soft_reg32_wo_t {
+    class rf1_reg1_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(SW17_CTRL_CH1,        /*width*/ 1, /*shift*/ 0);
-        UHD_DEFINE_SOFT_REG_FIELD(AMP_LO1_EN_CH1,       /*width*/ 1, /*shift*/ 1);
-        UHD_DEFINE_SOFT_REG_FIELD(SW16_CTRL_CH1,        /*width*/ 1, /*shift*/ 2);
-        UHD_DEFINE_SOFT_REG_FIELD(SW15_CTRL_CH1,        /*width*/ 1, /*shift*/ 3);
-        UHD_DEFINE_SOFT_REG_FIELD(SW14_CTRL_CH1,        /*width*/ 1, /*shift*/ 4);
-
-        rf1_reg1_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 3, /*reg*/ 1), OPTIMIZED_FLUSH) {
+        UHD_DEFINE_SOFT_REG_FIELD(SW17_CTRL_CH1, /*width*/ 1, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(AMP_LO1_EN_CH1, /*width*/ 1, /*shift*/ 1);
+        UHD_DEFINE_SOFT_REG_FIELD(SW16_CTRL_CH1, /*width*/ 1, /*shift*/ 2);
+        UHD_DEFINE_SOFT_REG_FIELD(SW15_CTRL_CH1, /*width*/ 1, /*shift*/ 3);
+        UHD_DEFINE_SOFT_REG_FIELD(SW14_CTRL_CH1, /*width*/ 1, /*shift*/ 4);
+
+        rf1_reg1_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 3, /*reg*/ 1), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf1_reg1;
 
-    class rf1_reg2_t : public uhd::soft_reg32_wo_t {
+    class rf1_reg2_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(SW12_CTRL_CH1,        /*width*/ 1, /*shift*/ 0);
-        UHD_DEFINE_SOFT_REG_FIELD(AMP_HB_EN_CH1,        /*width*/ 1, /*shift*/ 1);
+        UHD_DEFINE_SOFT_REG_FIELD(SW12_CTRL_CH1, /*width*/ 1, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(AMP_HB_EN_CH1, /*width*/ 1, /*shift*/ 1);
         UHD_DEFINE_SOFT_REG_FIELD(HB_PRESEL_PGA_EN_CH2, /*width*/ 1, /*shift*/ 2);
 
-        rf1_reg2_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 3, /*reg*/ 2), OPTIMIZED_FLUSH) {
+        rf1_reg2_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 3, /*reg*/ 2), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf1_reg2;
 
-    class rf1_reg3_t : public uhd::soft_reg32_wo_t {
+    class rf1_reg3_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(SW23_CTRL,            /*width*/ 1, /*shift*/ 0);
-        UHD_DEFINE_SOFT_REG_FIELD(SW22_CTRL_CH1,        /*width*/ 1, /*shift*/ 1);
-        UHD_DEFINE_SOFT_REG_FIELD(SW10_CTRL_CH1,        /*width*/ 2, /*shift*/ 2);
+        UHD_DEFINE_SOFT_REG_FIELD(SW23_CTRL, /*width*/ 1, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(SW22_CTRL_CH1, /*width*/ 1, /*shift*/ 1);
+        UHD_DEFINE_SOFT_REG_FIELD(SW10_CTRL_CH1, /*width*/ 2, /*shift*/ 2);
 
-        rf1_reg3_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 3, /*reg*/ 3), OPTIMIZED_FLUSH) {
+        rf1_reg3_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 3, /*reg*/ 3), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf1_reg3;
 
-    class rf1_reg4_t : public uhd::soft_reg32_wo_t {
+    class rf1_reg4_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(ATTEN_HB_CH2,         /*width*/ 5, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(ATTEN_HB_CH2, /*width*/ 5, /*shift*/ 0);
 
-        rf1_reg4_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 3, /*reg*/ 4), OPTIMIZED_FLUSH) {
+        rf1_reg4_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 3, /*reg*/ 4), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf1_reg4;
 
-    class rf1_reg5_t : public uhd::soft_reg32_wo_t {
+    class rf1_reg5_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(AMP_LO1_EN_CH2,       /*width*/ 1, /*shift*/ 0);
-        UHD_DEFINE_SOFT_REG_FIELD(SW15_CTRL_CH2,        /*width*/ 1, /*shift*/ 1);
-        UHD_DEFINE_SOFT_REG_FIELD(SW14_CTRL_CH2,        /*width*/ 1, /*shift*/ 2);
-        UHD_DEFINE_SOFT_REG_FIELD(SW18_CTRL_CH1,        /*width*/ 1, /*shift*/ 4);
-
-        rf1_reg5_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 3, /*reg*/ 5), OPTIMIZED_FLUSH) {
+        UHD_DEFINE_SOFT_REG_FIELD(AMP_LO1_EN_CH2, /*width*/ 1, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(SW15_CTRL_CH2, /*width*/ 1, /*shift*/ 1);
+        UHD_DEFINE_SOFT_REG_FIELD(SW14_CTRL_CH2, /*width*/ 1, /*shift*/ 2);
+        UHD_DEFINE_SOFT_REG_FIELD(SW18_CTRL_CH1, /*width*/ 1, /*shift*/ 4);
+
+        rf1_reg5_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 3, /*reg*/ 5), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf1_reg5;
 
-    class rf1_reg6_t : public uhd::soft_reg32_wo_t {
+    class rf1_reg6_t : public uhd::soft_reg32_wo_t
+    {
     public:
         UHD_DEFINE_SOFT_REG_FIELD(HB_PRESEL_PGA_EN_CH1, /*width*/ 1, /*shift*/ 0);
-        UHD_DEFINE_SOFT_REG_FIELD(SW17_CTRL_CH2,        /*width*/ 1, /*shift*/ 2);
-        UHD_DEFINE_SOFT_REG_FIELD(SW16_CTRL_CH2,        /*width*/ 1, /*shift*/ 3);
-        UHD_DEFINE_SOFT_REG_FIELD(PREAMP2_EN_CH2,       /*width*/ 1, /*shift*/ 4);
+        UHD_DEFINE_SOFT_REG_FIELD(SW17_CTRL_CH2, /*width*/ 1, /*shift*/ 2);
+        UHD_DEFINE_SOFT_REG_FIELD(SW16_CTRL_CH2, /*width*/ 1, /*shift*/ 3);
+        UHD_DEFINE_SOFT_REG_FIELD(PREAMP2_EN_CH2, /*width*/ 1, /*shift*/ 4);
 
-        rf1_reg6_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 3, /*reg*/ 6), OPTIMIZED_FLUSH) {
+        rf1_reg6_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 3, /*reg*/ 6), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf1_reg6;
 
-    class rf1_reg7_t : public uhd::soft_reg32_wo_t {
+    class rf1_reg7_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(SW22_CTRL_CH2,        /*width*/ 1, /*shift*/ 0);
-        UHD_DEFINE_SOFT_REG_FIELD(SW10_CTRL_CH2,        /*width*/ 2, /*shift*/ 1);
-        UHD_DEFINE_SOFT_REG_FIELD(SW12_CTRL_CH2,        /*width*/ 1, /*shift*/ 3);
-        UHD_DEFINE_SOFT_REG_FIELD(AMP_HB_EN_CH2,        /*width*/ 1, /*shift*/ 4);
-
-        rf1_reg7_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 3, /*reg*/ 7), OPTIMIZED_FLUSH) {
+        UHD_DEFINE_SOFT_REG_FIELD(SW22_CTRL_CH2, /*width*/ 1, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(SW10_CTRL_CH2, /*width*/ 2, /*shift*/ 1);
+        UHD_DEFINE_SOFT_REG_FIELD(SW12_CTRL_CH2, /*width*/ 1, /*shift*/ 3);
+        UHD_DEFINE_SOFT_REG_FIELD(AMP_HB_EN_CH2, /*width*/ 1, /*shift*/ 4);
+
+        rf1_reg7_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 3, /*reg*/ 7), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf1_reg7;
@@ -391,77 +483,99 @@ public:
     //----------------------------------------------
     // RF CCA: CPLD 4
     //----------------------------------------------
-    class rf2_reg0_t : public uhd::soft_reg32_wo_t {
+    class rf2_reg0_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(ATTEN_LB_CH1,         /*width*/ 5, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(ATTEN_LB_CH1, /*width*/ 5, /*shift*/ 0);
 
-        rf2_reg0_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 4, /*reg*/ 0), OPTIMIZED_FLUSH) {
+        rf2_reg0_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 4, /*reg*/ 0), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf2_reg0;
 
-    class rf2_reg2_t : public uhd::soft_reg32_wo_t {
+    class rf2_reg2_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(SW11_CTRL_CH1,        /*width*/ 1, /*shift*/ 0);
-        UHD_DEFINE_SOFT_REG_FIELD(AMP_LB_EN_CH1,        /*width*/ 1, /*shift*/ 1);
-        UHD_DEFINE_SOFT_REG_FIELD(SWPA2_CTRL_CH1,       /*width*/ 1, /*shift*/ 2);
+        UHD_DEFINE_SOFT_REG_FIELD(SW11_CTRL_CH1, /*width*/ 1, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(AMP_LB_EN_CH1, /*width*/ 1, /*shift*/ 1);
+        UHD_DEFINE_SOFT_REG_FIELD(SWPA2_CTRL_CH1, /*width*/ 1, /*shift*/ 2);
 
-        rf2_reg2_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 4, /*reg*/ 2), OPTIMIZED_FLUSH) {
+        rf2_reg2_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 4, /*reg*/ 2), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf2_reg2;
 
-    class rf2_reg3_t : public uhd::soft_reg32_wo_t {
+    class rf2_reg3_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(PREAMP2_EN_CH1,       /*width*/ 1, /*shift*/ 0);
-        UHD_DEFINE_SOFT_REG_FIELD(SW18_CTRL_CH2,        /*width*/ 1, /*shift*/ 1);
-        UHD_DEFINE_SOFT_REG_FIELD(SW8_CTRL_CH1,         /*width*/ 2, /*shift*/ 2);
+        UHD_DEFINE_SOFT_REG_FIELD(PREAMP2_EN_CH1, /*width*/ 1, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(SW18_CTRL_CH2, /*width*/ 1, /*shift*/ 1);
+        UHD_DEFINE_SOFT_REG_FIELD(SW8_CTRL_CH1, /*width*/ 2, /*shift*/ 2);
 
-        rf2_reg3_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 4, /*reg*/ 3), OPTIMIZED_FLUSH) {
+        rf2_reg3_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 4, /*reg*/ 3), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf2_reg3;
 
-    class rf2_reg4_t : public uhd::soft_reg32_wo_t {
+    class rf2_reg4_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(ATTEN_LB_CH2,         /*width*/ 5, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(ATTEN_LB_CH2, /*width*/ 5, /*shift*/ 0);
 
-        rf2_reg4_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 4, /*reg*/ 4), OPTIMIZED_FLUSH) {
+        rf2_reg4_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 4, /*reg*/ 4), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf2_reg4;
 
-    class rf2_reg5_t : public uhd::soft_reg32_wo_t {
+    class rf2_reg5_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(SWPA2_CTRL_CH2,       /*width*/ 1, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(SWPA2_CTRL_CH2, /*width*/ 1, /*shift*/ 0);
 
-        rf2_reg5_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 4, /*reg*/ 5), OPTIMIZED_FLUSH) {
+        rf2_reg5_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 4, /*reg*/ 5), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf2_reg5;
 
-    class rf2_reg6_t : public uhd::soft_reg32_wo_t {
+    class rf2_reg6_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(LB_PREAMP_EN_CH2,     /*width*/ 1, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(LB_PREAMP_EN_CH2, /*width*/ 1, /*shift*/ 0);
 
-        rf2_reg6_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 4, /*reg*/ 6), OPTIMIZED_FLUSH) {
+        rf2_reg6_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 4, /*reg*/ 6), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf2_reg6;
 
-    class rf2_reg7_t : public uhd::soft_reg32_wo_t {
+    class rf2_reg7_t : public uhd::soft_reg32_wo_t
+    {
     public:
-        UHD_DEFINE_SOFT_REG_FIELD(SWPA4_CTRL_CH1,       /*width*/ 1, /*shift*/ 0);
-        UHD_DEFINE_SOFT_REG_FIELD(SW8_CTRL_CH2,         /*width*/ 2, /*shift*/ 1);
-        UHD_DEFINE_SOFT_REG_FIELD(SW11_CTRL_CH2,        /*width*/ 1, /*shift*/ 3);
-        UHD_DEFINE_SOFT_REG_FIELD(AMP_LB_EN_CH2,        /*width*/ 1, /*shift*/ 4);
-
-        rf2_reg7_t(): uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 4, /*reg*/ 7), OPTIMIZED_FLUSH) {
+        UHD_DEFINE_SOFT_REG_FIELD(SWPA4_CTRL_CH1, /*width*/ 1, /*shift*/ 0);
+        UHD_DEFINE_SOFT_REG_FIELD(SW8_CTRL_CH2, /*width*/ 2, /*shift*/ 1);
+        UHD_DEFINE_SOFT_REG_FIELD(SW11_CTRL_CH2, /*width*/ 1, /*shift*/ 3);
+        UHD_DEFINE_SOFT_REG_FIELD(AMP_LB_EN_CH2, /*width*/ 1, /*shift*/ 4);
+
+        rf2_reg7_t()
+            : uhd::soft_reg32_wo_t(cpld::addr(/*cpld*/ 4, /*reg*/ 7), OPTIMIZED_FLUSH)
+        {
             set(REGISTER, 0);
         }
     } rf2_reg7;
 
-    twinrx_cpld_regmap() : soft_regmap_t("twinrx_cpld") {
+    twinrx_cpld_regmap() : soft_regmap_t("twinrx_cpld")
+    {
         // IF CCA: CPLD 1
         add_to_map(if0_reg0, "if0_reg0");
         add_to_map(if0_reg1, "if0_reg1");
@@ -499,6 +613,6 @@ public:
     }
 };
 
-}}}} //namespaces
+}}}} // namespace uhd::usrp::dboard::twinrx
 
 #endif /* INCLUDED_DBOARD_TWINRX_IO_HPP */