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authorTrung N Tran <trung.tran@ettus.com>2017-11-29 10:01:01 -0800
committerMartin Braun <martin.braun@ettus.com>2017-12-22 15:05:07 -0800
commit61774a09613eed51a42496f8689b707417b360f2 (patch)
tree6e443642a6f92591eea968c277eee6e1ab127888 /host/lib/usrp/dboard/magnesium
parent44b117be95dac3dd15c988e4e7d01b49f82d1a0c (diff)
downloaduhd-61774a09613eed51a42496f8689b707417b360f2.tar.gz
uhd-61774a09613eed51a42496f8689b707417b360f2.tar.bz2
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mg: fix TX dsa bug
DSA value was set at wrong value since it is at upper 6 bits of DSA register. Added comment.
Diffstat (limited to 'host/lib/usrp/dboard/magnesium')
-rw-r--r--host/lib/usrp/dboard/magnesium/magnesium_radio_ctrl_gain.cpp4
1 files changed, 3 insertions, 1 deletions
diff --git a/host/lib/usrp/dboard/magnesium/magnesium_radio_ctrl_gain.cpp b/host/lib/usrp/dboard/magnesium/magnesium_radio_ctrl_gain.cpp
index b3d01df2c..ff4683fe5 100644
--- a/host/lib/usrp/dboard/magnesium/magnesium_radio_ctrl_gain.cpp
+++ b/host/lib/usrp/dboard/magnesium/magnesium_radio_ctrl_gain.cpp
@@ -107,6 +107,8 @@ void magnesium_radio_ctrl_impl::_set_dsa_val(
const direction_t dir,
const uint32_t dsa_val
) {
+ // The DSA register holds 12 bits. The lower 6 bits are for RX, the upper
+ // 6 bits are for TX.
if (dir == RX_DIRECTION or dir == DX_DIRECTION){
UHD_LOG_TRACE(unique_id(),
__func__ << "(chan=" << chan << ", dir=RX"
@@ -117,7 +119,7 @@ void magnesium_radio_ctrl_impl::_set_dsa_val(
UHD_LOG_TRACE(unique_id(),
__func__ << "(chan=" << chan << ", dir=TX"
<< ", dsa_val=" << dsa_val << ")")
- _gpio[chan]->set_gpio_out(dsa_val, 0x0FC0);
+ _gpio[chan]->set_gpio_out(dsa_val<<6, 0x0FC0);
}
}