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authorSugandha Gupta <sugandha.gupta@ettus.com>2019-11-26 17:45:34 -0800
committerMartin Braun <martin.braun@ettus.com>2019-12-02 21:21:56 -0800
commit58f56fe25b62ab21693c8fd4e32cc2d00da85338 (patch)
treeb78995dfec3deff25197d4f1d1819b681f91084a /host/lib/usrp/dboard/e3xx/e31x_radio_control_impl.hpp
parentb8ba43193ab763d3e9e70e0743da08c49c421549 (diff)
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e31x: Fix filter bank and antenna switching for channel 0
The filter bank and antenna switches have different configuration for channel 0 and channel 1. This commit fixes the issue where channel 0 produces only noise due to incorrect switches.
Diffstat (limited to 'host/lib/usrp/dboard/e3xx/e31x_radio_control_impl.hpp')
-rw-r--r--host/lib/usrp/dboard/e3xx/e31x_radio_control_impl.hpp42
1 files changed, 28 insertions, 14 deletions
diff --git a/host/lib/usrp/dboard/e3xx/e31x_radio_control_impl.hpp b/host/lib/usrp/dboard/e3xx/e31x_radio_control_impl.hpp
index c51d74203..1c37f4077 100644
--- a/host/lib/usrp/dboard/e3xx/e31x_radio_control_impl.hpp
+++ b/host/lib/usrp/dboard/e3xx/e31x_radio_control_impl.hpp
@@ -62,32 +62,46 @@ private:
};
enum rx_sw1_t {
- RX_SW1_LB_B2 = 4,
- RX_SW1_LB_B3 = 2,
- RX_SW1_LB_B4 = 0,
- RX_SW1_LB_B5 = 1,
- RX_SW1_LB_B6 = 3,
- RX_SW1_LB_B7 = 5,
+ RX2_SW1_LB_B2 = 5,
+ RX2_SW1_LB_B3 = 3,
+ RX2_SW1_LB_B4 = 1,
+ RX2_SW1_LB_B5 = 0,
+ RX2_SW1_LB_B6 = 2,
+ RX2_SW1_LB_B7 = 4,
+ RX1_SW1_LB_B2 = 4,
+ RX1_SW1_LB_B3 = 2,
+ RX1_SW1_LB_B4 = 0,
+ RX1_SW1_LB_B5 = 1,
+ RX1_SW1_LB_B6 = 3,
+ RX1_SW1_LB_B7 = 5,
RX_SW1_OFF = 7
};
enum rx_swc_t {
- RX_SWC_LB_B2 = 2,
- RX_SWC_LB_B3 = 3,
- RX_SWC_LB_B4 = 1,
+ RX2_SWC_LB_B2 = 1,
+ RX2_SWC_LB_B3 = 3,
+ RX2_SWC_LB_B4 = 2,
+ RX1_SWC_LB_B2 = 2,
+ RX1_SWC_LB_B3 = 3,
+ RX1_SWC_LB_B4 = 1,
RX_SWC_OFF = 0
};
enum rx_swb_t {
- RX_SWB_LB_B5 = 2,
- RX_SWB_LB_B6 = 3,
- RX_SWB_LB_B7 = 1,
+ RX2_SWB_LB_B5 = 1,
+ RX2_SWB_LB_B6 = 3,
+ RX2_SWB_LB_B7 = 2,
+ RX1_SWB_LB_B5 = 2,
+ RX1_SWB_LB_B6 = 3,
+ RX1_SWB_LB_B7 = 1,
RX_SWB_OFF = 0
};
enum vcrx_sw_t {
- VCRX_SW_LB = 1,
- VCRX_SW_HB = 2,
+ VCRX_RX_SW_LB = 1,
+ VCRX_RX_SW_HB = 2,
+ VCRX_TXRX_SW_LB = 2,
+ VCRX_TXRX_SW_HB = 1,
VCRX_SW_OFF = 0 //or 3
};