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authorJosh Blum <josh@joshknows.com>2012-08-08 12:48:40 -0700
committerJosh Blum <josh@joshknows.com>2012-08-08 12:48:40 -0700
commit09de3c0768d2961ec3668882b4284e0db3b37eb8 (patch)
treec1e1ce1f476cf3ac5f36708987b188612168d858 /host/lib/usrp/dboard/db_sbx_version4.cpp
parentd18fc6f0f1fe934cd8684171d966561a36fb134c (diff)
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sbx/wbx: clear R/N counters before tuning the LO
This helps consistent phase offset between mixers when a timed tune is performed.
Diffstat (limited to 'host/lib/usrp/dboard/db_sbx_version4.cpp')
-rw-r--r--host/lib/usrp/dboard/db_sbx_version4.cpp5
1 files changed, 5 insertions, 0 deletions
diff --git a/host/lib/usrp/dboard/db_sbx_version4.cpp b/host/lib/usrp/dboard/db_sbx_version4.cpp
index f091caab7..27fd68b05 100644
--- a/host/lib/usrp/dboard/db_sbx_version4.cpp
+++ b/host/lib/usrp/dboard/db_sbx_version4.cpp
@@ -168,6 +168,11 @@ double sbx_xcvr::sbx_version4::set_lo_freq(dboard_iface::unit_t unit, double tar
UHD_ASSERT_THROW(rfdivsel_to_enum.has_key(RFdiv));
regs.rf_divider_select = rfdivsel_to_enum[RFdiv];
+ //reset the N and R counter
+ regs.counter_reset = adf4351_regs_t::COUNTER_RESET_ENABLED;
+ self_base->get_iface()->write_spi(unit, spi_config_t::EDGE_RISE, regs.get_reg(2), 32);
+ regs.counter_reset = adf4351_regs_t::COUNTER_RESET_DISABLED;
+
//write the registers
//correct power-up sequence to write registers (5, 4, 3, 2, 1, 0)
int addr;