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| author | Philip Balister <philip@opensdr.com> | 2010-10-27 06:27:05 -0400 |
|---|---|---|
| committer | Philip Balister <philip@opensdr.com> | 2010-10-27 06:27:05 -0400 |
| commit | fbdb002223f54bedbc7a4093494011c1b266fa75 (patch) | |
| tree | c8ba9446f117893cb28c00b91f953b5339c71f5f /host/lib/usrp/dboard/db_dbsrx.cpp | |
| parent | db0e3e574e9058ad51cacea91ccc42f0baed95fa (diff) | |
| parent | ef8ed898cbc6cb6cd1994d2a8b090112f4f3a664 (diff) | |
| download | uhd-fbdb002223f54bedbc7a4093494011c1b266fa75.tar.gz uhd-fbdb002223f54bedbc7a4093494011c1b266fa75.tar.bz2 uhd-fbdb002223f54bedbc7a4093494011c1b266fa75.zip | |
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Diffstat (limited to 'host/lib/usrp/dboard/db_dbsrx.cpp')
| -rw-r--r-- | host/lib/usrp/dboard/db_dbsrx.cpp | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/host/lib/usrp/dboard/db_dbsrx.cpp b/host/lib/usrp/dboard/db_dbsrx.cpp index 939a79e58..aecd7249d 100644 --- a/host/lib/usrp/dboard/db_dbsrx.cpp +++ b/host/lib/usrp/dboard/db_dbsrx.cpp @@ -162,15 +162,10 @@ static dboard_base::sptr make_dbsrx(dboard_base::ctor_args_t args){ return dboard_base::sptr(new dbsrx(args)); } -//dbid for USRP2 version UHD_STATIC_BLOCK(reg_dbsrx_dboard){ - //register the factory function for the rx dbid + //register the factory function for the rx dbid (others version) dboard_manager::register_dboard(0x000D, &make_dbsrx, "DBSRX"); -} - -//dbid for USRP1 version -UHD_STATIC_BLOCK(reg_dbsrx_on_usrp1_dboard){ - //register the factory function for the rx dbid + //register the factory function for the rx dbid (USRP1 version) dboard_manager::register_dboard(0x0002, &make_dbsrx, "DBSRX"); } @@ -241,8 +236,10 @@ void dbsrx::set_lo_freq(double target_freq){ bool update_filter_settings = false; //choose refclock std::vector<double> clock_rates = this->get_iface()->get_clock_rates(dboard_iface::UNIT_RX); + const double max_clock_rate = std::sorted(clock_rates).back(); BOOST_FOREACH(ref_clock, std::reversed(std::sorted(clock_rates))){ if (ref_clock > 27.0e6) continue; + if (size_t(max_clock_rate/ref_clock)%2 == 1) continue; //reject asymmetric clocks (odd divisors) //choose m_divider such that filter tuning constraint is met m = 31; |