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| author | Josh Blum <josh@joshknows.com> | 2011-10-07 17:30:42 -0700 | 
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-11-03 20:37:11 -0700 | 
| commit | 861e66848f05001fcaca4fe91dbf67cd186649dc (patch) | |
| tree | 33f685249fe9580c14eacc3ff2e25d08798ebfac /host/lib/usrp/cores | |
| parent | 65fb4d225204b4ee2b7c73fc0ec393cfff9d6149 (diff) | |
| download | uhd-861e66848f05001fcaca4fe91dbf67cd186649dc.tar.gz uhd-861e66848f05001fcaca4fe91dbf67cd186649dc.tar.bz2 uhd-861e66848f05001fcaca4fe91dbf67cd186649dc.zip  | |
usrp2: work on alternative OTW formats
Diffstat (limited to 'host/lib/usrp/cores')
| -rw-r--r-- | host/lib/usrp/cores/rx_dsp_core_200.cpp | 21 | ||||
| -rw-r--r-- | host/lib/usrp/cores/rx_dsp_core_200.hpp | 1 | 
2 files changed, 20 insertions, 2 deletions
diff --git a/host/lib/usrp/cores/rx_dsp_core_200.cpp b/host/lib/usrp/cores/rx_dsp_core_200.cpp index d562c64db..023216a09 100644 --- a/host/lib/usrp/cores/rx_dsp_core_200.cpp +++ b/host/lib/usrp/cores/rx_dsp_core_200.cpp @@ -42,6 +42,7 @@  #define REG_RX_CTRL_VRT_TLR        _ctrl_base + 24  #define REG_RX_CTRL_NSAMPS_PP      _ctrl_base + 28  #define REG_RX_CTRL_NCHANNELS      _ctrl_base + 32 +#define REG_RX_CTRL_FORMAT         _ctrl_base + 36  template <class T> T ceil_log2(T num){      return std::ceil(std::log(num)/std::log(T(2))); @@ -162,7 +163,7 @@ public:      }      double get_scaling_adjustment(void){ -        return _scaling_adjustment; +        return _scaling_adjustment/_fxpt_scale_adj;      }      double set_freq(const double freq_){ @@ -192,12 +193,28 @@ public:          if (_continuous_streaming) issue_stream_command(stream_cmd_t::STREAM_MODE_START_CONTINUOUS);      } +    void set_format(const std::string &format, const unsigned scale){ +        unsigned format_word = 0; +        if (format == "sc16"){ +            format_word = 0; +            _fxpt_scale_adj = 32767.; +        } +        else if (format == "sc8"){ +            format_word = (1 << 18); +            _fxpt_scale_adj = 32767./scale; +        } +        else throw uhd::value_error("USRP RX cannot handle requested wire format: " + format); + +        const unsigned scale_word = scale & 0x3ffff; //18 bits; +        _iface->poke32(REG_RX_CTRL_FORMAT, format_word | scale_word); +    } +  private:      wb_iface::sptr _iface;      const size_t _dsp_base, _ctrl_base;      double _tick_rate, _link_rate;      bool _continuous_streaming; -    double _scaling_adjustment; +    double _scaling_adjustment, _fxpt_scale_adj;  };  rx_dsp_core_200::sptr rx_dsp_core_200::make(wb_iface::sptr iface, const size_t dsp_base, const size_t ctrl_base, const boost::uint32_t sid, const bool lingering_packet){ diff --git a/host/lib/usrp/cores/rx_dsp_core_200.hpp b/host/lib/usrp/cores/rx_dsp_core_200.hpp index 391cc8441..ddd6f2abf 100644 --- a/host/lib/usrp/cores/rx_dsp_core_200.hpp +++ b/host/lib/usrp/cores/rx_dsp_core_200.hpp @@ -56,6 +56,7 @@ public:      virtual void handle_overflow(void) = 0; +    virtual void set_format(const std::string &format, const unsigned scale) = 0;  };  #endif /* INCLUDED_LIBUHD_USRP_RX_DSP_CORE_200_HPP */  | 
