Clean up build process

- Removed stale files (i2c_core_100, spi_core_100)
- Made more compilation condiational; disabling some devices will
  disable dependencies as well so they don't get compiled in by default.

5 files changed, 21 insertions, 283 deletions

diff --git a/host/lib/usrp/cores/CMakeLists.txt b/host/lib/usrp/cores/CMakeLists.txt
index cba0ba5f3..5d6c5d182 100644
--- a/host/lib/usrp/cores/CMakeLists.txt
+++ b/host/lib/usrp/cores/CMakeLists.txt
@@ -10,28 +10,32 @@
 
 INCLUDE_DIRECTORIES(${CMAKE_CURRENT_SOURCE_DIR})
 
+IF(ENABLE_B100 OR ENABLE_USRP2)
+    LIBUHD_APPEND_SOURCES(
+        ${CMAKE_CURRENT_SOURCE_DIR}/gpio_core_200.cpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/i2c_core_200.cpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/rx_dsp_core_200.cpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/time64_core_200.cpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/tx_dsp_core_200.cpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/user_settings_core_200.cpp
+    )
+ENDIF(ENABLE_B100 OR ENABLE_USRP2)
+
+
 LIBUHD_APPEND_SOURCES(
-    ${CMAKE_CURRENT_SOURCE_DIR}/gpio_core_200.cpp
-    ${CMAKE_CURRENT_SOURCE_DIR}/i2c_core_100.cpp
-    ${CMAKE_CURRENT_SOURCE_DIR}/i2c_core_200.cpp
-    ${CMAKE_CURRENT_SOURCE_DIR}/spi_core_100.cpp
-    ${CMAKE_CURRENT_SOURCE_DIR}/time64_core_200.cpp
-    ${CMAKE_CURRENT_SOURCE_DIR}/rx_dsp_core_200.cpp
-    ${CMAKE_CURRENT_SOURCE_DIR}/tx_dsp_core_200.cpp
+    ${CMAKE_CURRENT_SOURCE_DIR}/dma_fifo_core_3000.cpp
+    ${CMAKE_CURRENT_SOURCE_DIR}/dsp_core_utils.cpp
+    ${CMAKE_CURRENT_SOURCE_DIR}/gpio_atr_3000.cpp
+    ${CMAKE_CURRENT_SOURCE_DIR}/i2c_core_100_wb32.cpp
+    ${CMAKE_CURRENT_SOURCE_DIR}/radio_ctrl_core_3000.cpp
+    ${CMAKE_CURRENT_SOURCE_DIR}/rx_dsp_core_3000.cpp
     ${CMAKE_CURRENT_SOURCE_DIR}/rx_frontend_core_200.cpp
     ${CMAKE_CURRENT_SOURCE_DIR}/rx_frontend_core_3000.cpp
-    ${CMAKE_CURRENT_SOURCE_DIR}/tx_frontend_core_200.cpp
-    ${CMAKE_CURRENT_SOURCE_DIR}/user_settings_core_200.cpp
     ${CMAKE_CURRENT_SOURCE_DIR}/rx_vita_core_3000.cpp
-    ${CMAKE_CURRENT_SOURCE_DIR}/tx_vita_core_3000.cpp
-    ${CMAKE_CURRENT_SOURCE_DIR}/time_core_3000.cpp
     ${CMAKE_CURRENT_SOURCE_DIR}/spi_core_3000.cpp
-    ${CMAKE_CURRENT_SOURCE_DIR}/i2c_core_100_wb32.cpp
-    ${CMAKE_CURRENT_SOURCE_DIR}/dsp_core_utils.cpp
-    ${CMAKE_CURRENT_SOURCE_DIR}/rx_dsp_core_3000.cpp
+    ${CMAKE_CURRENT_SOURCE_DIR}/time_core_3000.cpp
     ${CMAKE_CURRENT_SOURCE_DIR}/tx_dsp_core_3000.cpp
-    ${CMAKE_CURRENT_SOURCE_DIR}/radio_ctrl_core_3000.cpp
-    ${CMAKE_CURRENT_SOURCE_DIR}/gpio_atr_3000.cpp
-    ${CMAKE_CURRENT_SOURCE_DIR}/dma_fifo_core_3000.cpp
+    ${CMAKE_CURRENT_SOURCE_DIR}/tx_frontend_core_200.cpp
+    ${CMAKE_CURRENT_SOURCE_DIR}/tx_vita_core_3000.cpp
     ${CMAKE_CURRENT_SOURCE_DIR}/user_settings_core_3000.cpp
 )
diff --git a/host/lib/usrp/cores/i2c_core_100.cpp b/host/lib/usrp/cores/i2c_core_100.cpp
deleted file mode 100644
index 2585e4a64..000000000
--- a/host/lib/usrp/cores/i2c_core_100.cpp
+++ /dev/null
@@ -1,133 +0,0 @@
-//
-// Copyright 2011,2014 Ettus Research LLC
-//
-// SPDX-License-Identifier: GPL-3.0
-//
-
-#include "i2c_core_100.hpp"
-#include <uhd/exception.hpp>
-#include <uhd/utils/log.hpp>
-#include <boost/thread/thread.hpp> //sleep
-
-#define REG_I2C_PRESCALER_LO _base + 0
-#define REG_I2C_PRESCALER_HI _base + 2
-#define REG_I2C_CTRL         _base + 4
-#define REG_I2C_DATA         _base + 6
-#define REG_I2C_CMD_STATUS   _base + 8
-
-//
-// STA, STO, RD, WR, and IACK bits are cleared automatically
-//
-
-#define	I2C_CTRL_EN	(1 << 7)	// core enable
-#define	I2C_CTRL_IE	(1 << 6)	// interrupt enable
-
-#define	I2C_CMD_START	(1 << 7)	// generate (repeated) start condition
-#define I2C_CMD_STOP	(1 << 6)	// generate stop condition
-#define	I2C_CMD_RD	(1 << 5)	// read from slave
-#define I2C_CMD_WR	(1 << 4)	// write to slave
-#define	I2C_CMD_NACK	(1 << 3)	// when a rcvr, send ACK (ACK=0) or NACK (ACK=1)
-#define I2C_CMD_RSVD_2	(1 << 2)	// reserved
-#define	I2C_CMD_RSVD_1	(1 << 1)	// reserved
-#define I2C_CMD_IACK	(1 << 0)	// set to clear pending interrupt
-
-#define I2C_ST_RXACK	(1 << 7)	// Received acknowledgement from slave (1 = NAK, 0 = ACK)
-#define	I2C_ST_BUSY	(1 << 6)	// 1 after START signal detected; 0 after STOP signal detected
-#define	I2C_ST_AL	(1 << 5)	// Arbitration lost.  1 when core lost arbitration
-#define	I2C_ST_RSVD_4	(1 << 4)	// reserved
-#define	I2C_ST_RSVD_3	(1 << 3)	// reserved
-#define	I2C_ST_RSVD_2	(1 << 2)	// reserved
-#define I2C_ST_TIP	(1 << 1)	// Transfer-in-progress
-#define	I2C_ST_IP	(1 << 0)	// Interrupt pending
-
-using namespace uhd;
-
-i2c_core_100::~i2c_core_100(void){
-    /* NOP */
-}
-
-class i2c_core_100_impl : public i2c_core_100{
-public:
-    i2c_core_100_impl(wb_iface::sptr iface, const size_t base):
-        _iface(iface), _base(base)
-    {
-        //init I2C FPGA interface.
-        _iface->poke16(REG_I2C_CTRL, 0x0000);
-        //set prescalers to operate at 400kHz: WB_CLK is 64MHz...
-        static const uint32_t i2c_datarate = 400000;
-        static const uint32_t wishbone_clk = 64000000; //FIXME should go somewhere else
-        uint16_t prescaler = wishbone_clk / (i2c_datarate*5) - 1;
-        _iface->poke16(REG_I2C_PRESCALER_LO, prescaler & 0xFF);
-        _iface->poke16(REG_I2C_PRESCALER_HI, (prescaler >> 8) & 0xFF);
-        _iface->poke16(REG_I2C_CTRL, I2C_CTRL_EN); //enable I2C core
-    }
-
-    void write_i2c(
-        uint16_t addr,
-        const byte_vector_t &bytes
-    ){
-        _iface->poke16(REG_I2C_DATA, (addr << 1) | 0); //addr and read bit (0)
-        _iface->poke16(REG_I2C_CMD_STATUS, I2C_CMD_WR | I2C_CMD_START | (bytes.size() == 0 ? I2C_CMD_STOP : 0));
-
-        //wait for previous transfer to complete
-        if (not wait_chk_ack()) {
-            _iface->poke16(REG_I2C_CMD_STATUS, I2C_CMD_STOP);
-            return;
-        }
-
-        for (size_t i = 0; i < bytes.size(); i++) {
-            _iface->poke16(REG_I2C_DATA, bytes[i]);
-            _iface->poke16(REG_I2C_CMD_STATUS, I2C_CMD_WR | ((i == (bytes.size() - 1)) ? I2C_CMD_STOP : 0));
-            if(!wait_chk_ack()) {
-                _iface->poke16(REG_I2C_CMD_STATUS, I2C_CMD_STOP);
-                return;
-            }
-        }
-    }
-
-    byte_vector_t read_i2c(
-        uint16_t addr,
-        size_t num_bytes
-    ){
-        byte_vector_t bytes;
-        if (num_bytes == 0) return bytes;
-
-        while (_iface->peek16(REG_I2C_CMD_STATUS) & I2C_ST_BUSY){
-            /* NOP */
-        }
-
-        _iface->poke16(REG_I2C_DATA, (addr << 1) | 1); //addr and read bit (1)
-        _iface->poke16(REG_I2C_CMD_STATUS, I2C_CMD_WR | I2C_CMD_START);
-        //wait for previous transfer to complete
-        if (not wait_chk_ack()) {
-            _iface->poke16(REG_I2C_CMD_STATUS, I2C_CMD_STOP);
-        }
-        for (size_t i = 0; i < num_bytes; i++) {
-            _iface->poke16(REG_I2C_CMD_STATUS, I2C_CMD_RD | ((num_bytes == i+1) ? (I2C_CMD_STOP | I2C_CMD_NACK) : 0));
-            i2c_wait();
-            bytes.push_back(uint8_t(_iface->peek16(REG_I2C_DATA)));
-        }
-        return bytes;
-    }
-
-private:
-    void i2c_wait(void) {
-        for (size_t i = 0; i < 100; i++){
-            if ((_iface->peek16(REG_I2C_CMD_STATUS) & I2C_ST_TIP) == 0) return;
-            boost::this_thread::sleep(boost::posix_time::milliseconds(1));
-        }
-        UHD_LOGGER_ERROR("CORES") << "i2c_core_100: i2c_wait timeout" ;
-    }
-
-    bool wait_chk_ack(void){
-        i2c_wait();
-        return (_iface->peek16(REG_I2C_CMD_STATUS) & I2C_ST_RXACK) == 0;
-    }
-
-    wb_iface::sptr _iface;
-    const size_t _base;
-};
-
-i2c_core_100::sptr i2c_core_100::make(wb_iface::sptr iface, const size_t base){
-    return sptr(new i2c_core_100_impl(iface, base));
-}
diff --git a/host/lib/usrp/cores/i2c_core_100.hpp b/host/lib/usrp/cores/i2c_core_100.hpp
deleted file mode 100644
index 42e37d7da..000000000
--- a/host/lib/usrp/cores/i2c_core_100.hpp
+++ /dev/null
@@ -1,26 +0,0 @@
-//
-// Copyright 2011,2014 Ettus Research LLC
-//
-// SPDX-License-Identifier: GPL-3.0
-//
-
-#ifndef INCLUDED_LIBUHD_USRP_I2C_CORE_100_HPP
-#define INCLUDED_LIBUHD_USRP_I2C_CORE_100_HPP
-
-#include <uhd/config.hpp>
-#include <uhd/types/serial.hpp>
-#include <boost/utility.hpp>
-#include <boost/shared_ptr.hpp>
-#include <uhd/types/wb_iface.hpp>
-
-class i2c_core_100 : boost::noncopyable, public uhd::i2c_iface{
-public:
-    typedef boost::shared_ptr<i2c_core_100> sptr;
-
-    virtual ~i2c_core_100(void) = 0;
-
-    //! makes a new i2c core from iface and slave base
-    static sptr make(uhd::wb_iface::sptr iface, const size_t base);
-};
-
-#endif /* INCLUDED_LIBUHD_USRP_I2C_CORE_100_HPP */
diff --git a/host/lib/usrp/cores/spi_core_100.cpp b/host/lib/usrp/cores/spi_core_100.cpp
deleted file mode 100644
index 3e2ec63f1..000000000
--- a/host/lib/usrp/cores/spi_core_100.cpp
+++ /dev/null
@@ -1,81 +0,0 @@
-//
-// Copyright 2011,2014 Ettus Research LLC
-//
-// SPDX-License-Identifier: GPL-3.0
-//
-
-#include "spi_core_100.hpp"
-#include <uhd/exception.hpp>
-#include <uhd/utils/log.hpp>
-#include <boost/thread/thread.hpp> //sleep
-
-#define REG_SPI_TXRX0 _base + 0
-#define REG_SPI_TXRX1 _base + 4
-#define REG_SPI_TXRX2 _base + 8
-#define REG_SPI_TXRX3 _base + 12
-#define REG_SPI_CTRL  _base + 16
-#define REG_SPI_DIV   _base + 20
-#define REG_SPI_SS    _base + 24
-
-//spi ctrl register bit definitions
-#define SPI_CTRL_ASS      (1<<13)
-#define SPI_CTRL_IE       (1<<12)
-#define SPI_CTRL_LSB      (1<<11)
-#define SPI_CTRL_TXNEG    (1<<10) //mosi edge, push on falling edge when 1
-#define SPI_CTRL_RXNEG    (1<< 9) //miso edge, latch on falling edge when 1
-#define SPI_CTRL_GO_BSY   (1<< 8)
-#define SPI_CTRL_CHAR_LEN_MASK 0x7F
-
-using namespace uhd;
-
-spi_core_100::~spi_core_100(void){
-    /* NOP */
-}
-
-class spi_core_100_impl : public spi_core_100{
-public:
-    spi_core_100_impl(wb_iface::sptr iface, const size_t base):
-        _iface(iface), _base(base) { /* NOP */}
-
-    uint32_t transact_spi(
-        int which_slave,
-        const spi_config_t &config,
-        uint32_t data,
-        size_t num_bits,
-        bool readback
-    ){
-        UHD_ASSERT_THROW(num_bits <= 32 and (num_bits % 8) == 0);
-
-        int edge_flags = ((config.miso_edge==spi_config_t::EDGE_FALL) ? SPI_CTRL_RXNEG : 0) |
-                         ((config.mosi_edge==spi_config_t::EDGE_FALL) ? 0 : SPI_CTRL_TXNEG)
-                         ;
-        uint16_t ctrl = SPI_CTRL_ASS | (SPI_CTRL_CHAR_LEN_MASK & num_bits) | edge_flags;
-
-        spi_wait();
-        _iface->poke16(REG_SPI_DIV, 0x0001); // = fpga_clk / 4
-        _iface->poke32(REG_SPI_SS, which_slave & 0xFFFF);
-        _iface->poke32(REG_SPI_TXRX0, data);
-        _iface->poke16(REG_SPI_CTRL, ctrl);
-        _iface->poke16(REG_SPI_CTRL, ctrl | SPI_CTRL_GO_BSY);
-
-        if (not readback) return 0;
-        spi_wait();
-        return _iface->peek32(REG_SPI_TXRX0);
-    }
-
-private:
-    void spi_wait(void) {
-        for (size_t i = 0; i < 100; i++){
-            if ((_iface->peek16(REG_SPI_CTRL) & SPI_CTRL_GO_BSY) == 0) return;
-            boost::this_thread::sleep(boost::posix_time::milliseconds(1));
-        }
-        UHD_LOGGER_ERROR("CORES") << "spi_core_100: spi_wait timeout" ;
-    }
-
-    wb_iface::sptr _iface;
-    const size_t _base;
-};
-
-spi_core_100::sptr spi_core_100::make(wb_iface::sptr iface, const size_t base){
-    return sptr(new spi_core_100_impl(iface, base));
-}
diff --git a/host/lib/usrp/cores/spi_core_100.hpp b/host/lib/usrp/cores/spi_core_100.hpp
deleted file mode 100644
index 36e136466..000000000
--- a/host/lib/usrp/cores/spi_core_100.hpp
+++ /dev/null
@@ -1,26 +0,0 @@
-//
-// Copyright 2011,2014 Ettus Research LLC
-//
-// SPDX-License-Identifier: GPL-3.0
-//
-
-#ifndef INCLUDED_LIBUHD_USRP_SPI_CORE_100_HPP
-#define INCLUDED_LIBUHD_USRP_SPI_CORE_100_HPP
-
-#include <uhd/config.hpp>
-#include <uhd/types/serial.hpp>
-#include <boost/utility.hpp>
-#include <boost/shared_ptr.hpp>
-#include <uhd/types/wb_iface.hpp>
-
-class spi_core_100 : boost::noncopyable, public uhd::spi_iface{
-public:
-    typedef boost::shared_ptr<spi_core_100> sptr;
-
-    virtual ~spi_core_100(void) = 0;
-
-    //! makes a new spi core from iface and slave base
-    static sptr make(uhd::wb_iface::sptr iface, const size_t base);
-};
-
-#endif /* INCLUDED_LIBUHD_USRP_SPI_CORE_100_HPP */