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author | Josh Blum <josh@joshknows.com> | 2012-04-10 14:29:28 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2012-04-10 14:29:28 -0700 |
commit | 12ea88585e83100ed6f229808c4492445ca53e28 (patch) | |
tree | d9d08ee28a552fe7f798293bf46b14490e324c4e /host/lib/usrp/cores | |
parent | 76f794330649b4fed0bff3617b13c9aa648b5382 (diff) | |
parent | cc421709426601ded6949d041364dcf5b102b849 (diff) | |
download | uhd-12ea88585e83100ed6f229808c4492445ca53e28.tar.gz uhd-12ea88585e83100ed6f229808c4492445ca53e28.tar.bz2 uhd-12ea88585e83100ed6f229808c4492445ca53e28.zip |
Merge branch 'master' into next
Diffstat (limited to 'host/lib/usrp/cores')
-rw-r--r-- | host/lib/usrp/cores/rx_dsp_core_200.cpp | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/host/lib/usrp/cores/rx_dsp_core_200.cpp b/host/lib/usrp/cores/rx_dsp_core_200.cpp index 4b60f111c..cf8db1927 100644 --- a/host/lib/usrp/cores/rx_dsp_core_200.cpp +++ b/host/lib/usrp/cores/rx_dsp_core_200.cpp @@ -38,13 +38,12 @@ #define REG_RX_CTRL_STREAM_CMD _ctrl_base + 0 #define REG_RX_CTRL_TIME_HI _ctrl_base + 4 #define REG_RX_CTRL_TIME_LO _ctrl_base + 8 -#define REG_RX_CTRL_CLEAR _ctrl_base + 12 +#define REG_RX_CTRL_FORMAT _ctrl_base + 12 #define REG_RX_CTRL_VRT_HDR _ctrl_base + 16 #define REG_RX_CTRL_VRT_SID _ctrl_base + 20 #define REG_RX_CTRL_VRT_TLR _ctrl_base + 24 #define REG_RX_CTRL_NSAMPS_PP _ctrl_base + 28 #define REG_RX_CTRL_NCHANNELS _ctrl_base + 32 -#define REG_RX_CTRL_FORMAT REG_RX_CTRL_CLEAR //re-use clear address template <class T> T ceil_log2(T num){ return std::ceil(std::log(num)/std::log(T(2))); @@ -78,8 +77,7 @@ public: } void clear(void){ - _iface->poke32(REG_RX_CTRL_CLEAR, 1); //reset - _iface->poke32(REG_RX_CTRL_NCHANNELS, 1); + _iface->poke32(REG_RX_CTRL_NCHANNELS, 1); //also reset _iface->poke32(REG_RX_CTRL_VRT_HDR, 0 | (0x1 << 28) //if data with stream id | (0x1 << 26) //has trailer |