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| author | Sugandha Gupta <sugandha.gupta@ettus.com> | 2019-01-25 11:34:47 -0800 |
|---|---|---|
| committer | Brent Stapleton <brent.stapleton@ettus.com> | 2019-05-01 15:17:23 -0700 |
| commit | 178b35569b1a25180a80a23b945b10b04c9f10f5 (patch) | |
| tree | 3adb6f78ebd148867a50526c60fe7bf9694a4a72 /host/lib/usrp/common | |
| parent | 8a400f6a30942c9d6d3596f6989720eb4cff058b (diff) | |
| download | uhd-178b35569b1a25180a80a23b945b10b04c9f10f5.tar.gz uhd-178b35569b1a25180a80a23b945b10b04c9f10f5.tar.bz2 uhd-178b35569b1a25180a80a23b945b10b04c9f10f5.zip | |
e310/e320: Move E310 to MPM architecture and refactor
- Turns the E310 into an MPM device (like N3xx, E320)
- Factor out common code between E320 and E310, maximize sharing between
the two devices
- Remove all pre-MPM E310 code that is no longer needed
- Modify MPM to remove all existing overlays before applying new ones
(this is necessary to enable idle image mode for E310)
Co-authored-by: Virendra Kakade <virendra.kakade@ni.com>
Signed-off-by: Virendra Kakade <virendra.kakade@ni.com>
Diffstat (limited to 'host/lib/usrp/common')
| -rw-r--r-- | host/lib/usrp/common/ad9361_driver/ad9361_device.cpp | 2 | ||||
| -rw-r--r-- | host/lib/usrp/common/ad9361_driver/ad9361_device.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp index f0e10871e..e12519c36 100644 --- a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp +++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp @@ -1916,7 +1916,7 @@ double ad9361_device_t::set_clock_rate(const double req_rate) /* This function returns the RX / TX rate between AD9361 and the FPGA. */ -double ad9361_device_t::get_clock_rate() +double ad9361_device_t::get_clock_rate() const { return _baseband_bw; } diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.h b/host/lib/usrp/common/ad9361_driver/ad9361_device.h index 57f71193f..96a105438 100644 --- a/host/lib/usrp/common/ad9361_driver/ad9361_device.h +++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.h @@ -162,7 +162,7 @@ public: void set_io_iface(ad9361_io::sptr io_iface); /* Get the current clock rate. */ - double get_clock_rate(); + double get_clock_rate() const; /* This function sets the RX / TX rate between AD9361 and the FPGA, and * thus determines the interpolation / decimation required in the FPGA to |