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authorAshish Chaudhari <ashish@ettus.com>2015-10-15 16:19:47 -0700
committerAshish Chaudhari <ashish@ettus.com>2015-10-15 16:19:47 -0700
commit6f93ac01b519b5e01b01d7b8bcc106e58fd50721 (patch)
tree20a45813fc01be561d1974e83efd242a1196396d /host/lib/usrp/common/ad9361_ctrl.hpp
parentea982f5f0d4b138f230638624c5e17fa3902706d (diff)
parenteb2f57a6241ce04a3d89c5f41557658387440c3f (diff)
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Merge branch 'master' into ashish/gpio_atr_redux
Diffstat (limited to 'host/lib/usrp/common/ad9361_ctrl.hpp')
-rw-r--r--host/lib/usrp/common/ad9361_ctrl.hpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/host/lib/usrp/common/ad9361_ctrl.hpp b/host/lib/usrp/common/ad9361_ctrl.hpp
index 5c438ee9c..8cd75d539 100644
--- a/host/lib/usrp/common/ad9361_ctrl.hpp
+++ b/host/lib/usrp/common/ad9361_ctrl.hpp
@@ -89,8 +89,10 @@ public:
//! get the clock rate range for the frontend
static uhd::meta_range_t get_clock_rate_range(void)
{
- //return uhd::meta_range_t(220e3, 61.44e6);
- return uhd::meta_range_t(5e6, ad9361_device_t::AD9361_MAX_CLOCK_RATE); //5 MHz DCM low end
+ return uhd::meta_range_t(
+ ad9361_device_t::AD9361_MIN_CLOCK_RATE,
+ ad9361_device_t::AD9361_MAX_CLOCK_RATE
+ );
}
//! set the filter bandwidth for the frontend's analog low pass