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| author | Brent Stapleton <brent.stapleton@ettus.com> | 2018-07-03 13:58:56 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2018-07-11 12:42:45 -0700 |
| commit | 05722dcc51a09084865736651e46326041dd6038 (patch) | |
| tree | 75730f1966144b07ae4784b625723853e3de8bbc /host/lib/usrp/b200/b200_impl.cpp | |
| parent | b39358f490a24ffe4b8b29227736b8d2eb40b956 (diff) | |
| download | uhd-05722dcc51a09084865736651e46326041dd6038.tar.gz uhd-05722dcc51a09084865736651e46326041dd6038.tar.bz2 uhd-05722dcc51a09084865736651e46326041dd6038.zip | |
mpm: n3xx: Factor out component updating
- Refactoring component (FPGA, DTS) updating functions out of
n3xx.py into their own components.py. The ZynqComponent class now
defines the methods to update these two components.
- Adding super().__init__() to the PeriphManagerBase class. This is
needed to get the multiple inheritance used in N3XX now to work, and
(apparently) good Python practice.
Diffstat (limited to 'host/lib/usrp/b200/b200_impl.cpp')
0 files changed, 0 insertions, 0 deletions