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authorBalint Seeber <balint@ettus.com>2013-11-19 13:17:25 -0800
committerBalint Seeber <balint@ettus.com>2013-11-19 13:17:25 -0800
commit01cfe2118f0bd72719809d2539c61df46a164fec (patch)
treea93b693341d0e7b9c37844fabcd996ed626ba543 /host/lib/usrp/b200/b200_impl.cpp
parentdb6541583a9c42df79600b47ab2184ee59c46e6a (diff)
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b200: increase FPGA VREQ transfer size to 512 if operating over USB3
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